DS CS 304 Lab Manual
DS CS 304 Lab Manual
DS CS 304 Lab Manual
DEPARTMENT
OF
COMPUTER SCIENCE ENGINEERING
LAB MANUAL (CS-304)
“DIGITAL SYSTEMS”
Name: ______________________________________
Semester: ___________________________________
Branch: _____________________________________
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Index
S. No. Particulars Page No.
1 Vision and Mission of the Institute
2 Vision and Mission of the Department
3 Programme Educational Objective (PEOs)
4 Programme Specific Outcomes (PSOs)
5 Programme Outcomes (POs)
6 Course Outcomes (COs)
7 CO-PO Matrix
8 CO-PSO Matrix
9 University Scheme
10 Syllabus
11 Academic Calendar
12 List of Experiments
13 Lab Time Table (Individual & Class)
14 Laboratory Plan
15 Lab Manual
16 Important Viva questions
17 Attendance Record
18 Internal Assessment Record of attainment of Course Outcomes
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VISION
MISSION
To establish state of art infrastructure and facilities, this will pave the way for
dissemination of technical knowledge with passion and commitment.
To impart industry relevant skill based training and aid in overall development of
students.
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VISION
MISSION
To build strong teaching, learning and ethical environment for imparting quality
M1
education.
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Able to design and develop interdisciplinary and innovative hardware and software
PEO 2:
solutions.
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DIGITAL SYSTEMS
LABORATORY
Upon the completion of Communication and Transmission lines Laboratory, the student will be
able to:
Course Name: DIGITAL SYSTEMS
CS-304.1 Design and analyze various types of gates, Verify de-morgans theorem
CS-304.2 Design and analyze half and full adder and subtractor
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CO Vs PO
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 1 1 2 2 2 1 1 1 1 1 1
CO2 2 1 1 1 1 2 1 1 1 1 2 1
CO3 2 2 2 2 1 1 1 2 1 1 1 1
CO4 2 2 2 2 1 2 1 1 1 2 1 1
CO5 2 2 2 2 2 2 1 1 2 2 1 1
Average 2 1.6 1.6 1.8 1.4 1.8 1 1.2 1.2 1.4 1.2 1
CO Vs PSO
PSO1 PSO2 PSO3 PSO4
CO1 1 1 1 1
CO2 2 2 1 1
CO3 1 1 1 2
CO4 1 1 2 2
CO5 1 2 1 2
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SCHEME
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SYLLABUS
RAJIV GANDHI PROUDYOGIKI VISHWAVIDYALAYA BHOPAL
III -Semester
Unit 1: Review of number systems and number base conversions. Binary codes, Boolean algebra,
Boolean functions, Logic gates. Simplification of Boolean functions, Karnaugh map methods, SOP-POS
simplification, NAND-NOR implementation.
Unit 2: Combinational Logic: Half adder, Half subtractor, Full adder, Full subtractor, look- ahead carry
generator,BCD adder, Series and parallel addition, Multiplexer - Demultiplexer, encoder- decoder,
arithmetic circuits, ALU
Unit 3 : Sequential logic: flip flops, D,T, S-R, J-K Master- Slave, racing condition, Edge & Level triggered
circuits, Shift registers, Asynchronous and synchronous counters, their types and state diagrams.
Semiconductor memories, Introduction to digital ICs 2716, 2732 etc. & their address decoding. Modern
trends in semiconductor memories such as DRAM, FLASH RAM etc. Designing with ROM and PLA.
Unit 4 : Introduction to A/D & D/A convertors & their types, sample and hold circuits, Voltage to
Frequency & Frequency to Voltage conversion. Multivibrators :Bistable, Monostable, Astable, Schmitt
trigger, IC 555 & Its applications. TTL, PMOS, CMOS and NMOS logic. Interfacing between TTL to MOS.
Unit 5 : Introduction to Digital Communication: Nyquist sampling theorem, time division multiplexing,
PCM, quantization error, introduction to BPSK & BFSK modulation schemes. Shannon’s theorem for
channel capacity.
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List of Experiments:
1. To study and verify the truth tables of various Logic gates
2. To verify the properties of NAND and NOR gates as Universal Building Blocks.
3. Simplification and implementation of a Boolean function
4. Implementation of basic Boolean arithmetic logic circuits such as Half-adder,
Half-subtractor, Full adder and Full subtractor
5. Conversion from Binary to Gray and Gray to Binary code
6. To construct a binary multiplier using combinational logic and to verify with the
truth table
7. To verify 2-bit Magnitude comparator for all possible conditions
8. Generation of various logical functions using 8-to-1 multiplexer
9. Construction of a 4-bit ripple counter and study of its operation
10. Operation of IC-555 Timer as Monostable, Astable and Bistablemultivibrators
11. To characterize binary ladder type digital to analog (D/A) and analog to digital
(A/D) convertor
12. Comparison of various Logic families
13. Design and implementation of various types of flip-flops using JK flip-flop
14. To study natural sampling of continuous time waveforms using different sampling
rates
15. To study Pulse-Code modulation with Time-division multiplexing (PCM-TDM)
16. To study generation and detection of BPSK and QPSK waveforms
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ACADEMIC CALENDER
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LIST OF EXPERIMENTS
S. No Name of Experiment Page No. Course
Outcome
TO STUDY AND TEST OF OPERATION OF ALL
1 CO1
LOGIC GATES FOR VARIOUS IC’S
(IC#7400,IC#7402,IC# 7408,IC#7432,IC#7486).
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LABORATORY PLAN
Planned Date
Exp. CO Actual Date of HOD
Experiment of Remarks
No. Completion Verification
Completion
VERIFICATION OF
2 DEMORGAN’S THEOREM. CO1
TO CONSTRUCT OF HALF
3 ADDER AND FULL ADDER CO2
TO CONSTRUCT OF HALF
SUBTRACTOR AND FULL
4 SUBTRACTOR CIRCUITS. CO2
VERIFICATION OF
VERSATILITY OF NAND
5 GATE. CO3
VERIFICATION OF
6 VERSATILITY OF NOR GATE. CO3
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Experiment No-1
Aim: - To study and test of operation of all logic gates for various IC’s (IC#7400, IC#7403,
IC#7408, IC#74332, IC#7486
Theory:-
Logic gates:-
Logic circuits that perform the logical operation of AND, OR & NOT are called gates. These
gates produce a Logic 1 & Logic 0 o/p signal and thus know as a Logic gates. These gates are
AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates.
(1). AND gate:-The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot ( . ) is used to show the AND operation i.e. A.B
(2).OR gate:-The OR gate is an electronic circuit that gives a high output (1) if one or more
of its inputs are high. A plus (+) is used to show the OR operation.
(3).NOT gate:- The NOT gate is an electronic circuit that produces an inverted version of the
input at its output.It is also known as an inverter. If the input variable is A, the inverted
(4)NAND gate: -The NAND gate operates as an AND gate followed by a NOT gate.
It acts in the manner of the logical operation "and" followed by negation. The output is "false"
(5).NOR gate :-This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate.
The outputs of all NOR gates are low if any of the inputs are high.
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The symbol is an OR gate with a small circle on the output. The small circle represents
inversion.
(6).EXOR gate:-The 'Exclusive-OR' gate is a circuit which will give a high output if either, but
not both, of its two inputs are high. An encircled plus sign (+) is used to show the EXOR
operation.
(7).EXNOR gate:-The 'Exclusive-NOR' gate circuit does the opposite to the EXOR gate. It will
give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR
gate with a small circle on the output. The small circle represents inversion.
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Not Gate
And Gate
A B A.B(A AND B)
1.AND GATE-(IC-7411)
This operation is represented by a dot. The logic operation AND is interrupted by means
that z=1 if and only if x and y =1 ; otherwise z = 0
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X Y F=X.Y
2. OR GATE-(IC-7412)
This operation is represented by ‘+’ sign . It means that output is high in case any one of the
I/Ps is high
X Y F=X+Y
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X F=X’
4. EXCLUSIVE OR GATE:
The EX-OR operation gives high output if one of the inputs is high. The Boolean for XOR
operation can be written as
Y=X+Y
= X’Y + XY’
This operation can be implemented using basic AND, OR and invert gates. The symbol and
truth table for XOR gate is given in Fig.(a) and (b) . The pin diagram of popular XOR gate
IC is shown in fig.
X Y F=x’y+xy’
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The EX-NOR operation give high output for both inputs low and both inputs high. The Ex-NOR
is written as
F=X’Y’+XY
This operation is implemented using basic AND, OR, and invert gates .The basic logic circuit
and symbol for the EX-NOR are shown in fig.
X Y F=x’y’+xy
PROCEDURE :
RESULT: The Truth table for all the logic gates is verified
CONCLUSION:
1.AND GATE- Output is high when all the inputs are high
3.EX-OR GATE –Output is high when number of input 1’s are odd.
Experiment No-2
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Theory:-
DeMorgan's Theorems:
a. (A + B)’ = A’* B’
b. (A*B)’ = A’ + B’
Note: * = AND operation
Theorem 1:
The compliment of the product of two variables is equal to the sum of the compliment of each
variable.
Thus according to De-Morgan’s laws or De-Morgan’s theorem if A and B are the two variables
or Boolean numbers. Then accordingly
(A.B)’ = A’ + B’
Theorem 2:
The compliment of the sum of two variables is equal to the product of the compliment of each
variable.
Thus according to De Morgan’s theorem if A and B are the two variables then.
(A + B)’ = A’.B’
PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly
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Experiment No-3
Theory:-
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Half Adder:-It is a combinational circuit that performs addition of two bits. This circuit has two
inputs and two outputs. . Two of the inputs variables denoted by A & B represent the two
significant bits to be added. The two outputs are designated as the symbols”S” for sum &”C” for
carry. The binary variable S gives the value of least significant bit of the sum. The binary
variable C gives the output carry.
Input Output
Carry Sum
A B C S
OBSERVATION
Full Adder:-A full adder is a combinational circuit that forms arithmetic sum of three input bits.
It consists of three inputs & two outputs. Two of the inputs variables denoted by X&Y represent
the two significant bits to be added. The third input Z represents the carry from the previous
lower significant position. The need for the two outputs arises because the arithmetic sum of
three binary digits ranges in the value from 0-3 and binary 2&3 need two digits. The two outputs
are designated as the symbols”S” for sum &”C” for carry. The binary variable S gives the value
of least significant bit of the sum. The binary variable C gives the output carry.
S=AÅB
S=A’B+AB’
C=AB
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X Y Z C S
From the truth table logical expression for S & C outputs are:
S=XÅYÅZ
S=XY’Z’+X’YZ’ +XYZ+X’Y’Z
C=XY+XZ+YZ
PROCEDURE:
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RESULT : The Truth table for Full Adder and Half Adder is verified
PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly
Experiment No-4
Aim: - To construct of half subtractor and full subtractor circuits
A combinational circuit which performs the subtraction of two bits is called half subtractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
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Difference=A ⊕ B
Borrow=A’.B
FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called full subtractor. The
three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be
implemented with two half subtractors and one OR gate.
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HALF SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT
S.No
A B DIFF BORR
1.
2.
3.
4.
FULL SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT
S.No
A B C DIFF BORR
1.
2.
3.
4.
5.
6.
7.
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8.
RESULT : The Truth table for Full subtractor and Half subtractor is verified
PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly
Experiment No-5
Theory:-
NAND GATE-(IC-7450):-NAND function is complement of AND and is an abbreviation for “AND”. Its
graphic symbol which consists of an AND graphic symbol following by a small circle. The NAND &
NOR gates are extensively used as standard logic gates and are in fact far more popular than AND or OR
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gates, NAND and NOR gates are easily constructed with transistor circuits and because Boolean function
can be easily implemented with them, that is why are popularly know as universal gates.
F=X.
X Y F’=(X.Y)’
Y
PROCEDURE:
2. Set the input switches according to the truth tables as shown in the first row.
3. Monitor the output for the proper indication. If the light is off. Place a 0 under
Column Z and write “off” in the LED column. If the light is ON, place a 1 under
4. Repeat steps 2 and 3 for the remaining rows of the truth tables.
5. Repeat the above steps for verifying the truth tables in the case of a 3-input AND
gate by selecting 3input switches and 073 monitoring the output on the Lamp out.
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RESULT: The Truth tables for NAND GATE gates are verified
PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly
Experiment No-6
Theory:-
NOR GATE( IC-7427):- The NOR function is the complement of the OR function and its name
an OR graphic symbol followed by a small circle.
The NAND & NOR gates are extensively used as standard logic gates and are in fact far more
popular than AND or OR gates , This is become NAND and NOR gates are easily constructed
with transistor circuits and because Boolean function can be easily implemented with them, that
is why are popularly know as universal gates.
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X Y F=X+Y F’=(X.Y)’
PROCEDURE:
2. Set the input switches according to the truth tables as shown in the first row.
3. Monitor the output for the proper indication. If the light is off. Place a 0 under
Column Z and write “off” in the LED column. If the light is ON, place a 1 under
4. Repeat steps 2 and 3 for the remaining rows of the truth tables.
5. Repeat the above steps for verifying the truth tables in the case of a 3-input AND
gate by selecting 3input switches and 073 monitoring the output on the Lamp out.
RESULT: The Truth tables for NAND GATE gates are verified
PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly
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Experiment-No-7
Theory:-
1) Basic flip flop : - A flip flop can be constructed from two NAND gates or two NOR gates .the
cross coupled connections from the o/p of one gate be i/p of another constitute the feedback path
,each flip flop has two o/p Q & Q' and two i/p set and reset ,the type of flip flop is sometimes
called direct coupled RS flip flop or SR latch.In basic flip flop circuit with NOR gate we must
remember that o/p is 1 only when all i/p are 0. as starting point is assume that set i/p is 1 and
reset i/p is 0, since gate 2 has an i/p of 1, it’s o/p must be 0,its o/p Q' must be 0, which puts both
input of gates to the o/p Q is 1, when the set i/p is returned to 0,the o/p remains the same at one
i/p at gate 2 at 1.That causes o/p Q to stay at 0 which leaves both i/p of gates no. 1 at 0.So Q is
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at 1. A f-f has two useful states when Q =1 and Q'=0 ,it is in the set state . When Q =0&Q'=1 it
is clear state .Under normal conditions both i/p remains at 0 unless the state of the flip flop has
to be changed. The application of momentary 1 to the set i/p causes the flip flop to go to set state
.The set state i/p must go back to 0 before 1 is supplied to reset i/p .The NAND basic flip flop
circuit . Operates with both i/p normally at 1 under the state of f-f has to be changed. The
application at momentary 0 to set i/p has o/p Q to go to 1 and Q' to 0. The flip flop in the set state
.After the set i/p causes a transition to the clear state when both i/p go to 1, a condition avoided
in the f-f operation .
2) Clocked RS Flip Flop : By adding Gates to the i/p of the basic circuit. of the flip flop
can be made to respond to the i/p level during the occurrence clock pulse. This f-f consist of
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basic NOR and two NAND gates the o/p of the two AND gates remains at 0 as long as the
clock pulse is 0 regardless of S & R. i/p values when clock pulse goes to 1 information from S &
R i/p is allowed to reach the basic f-f , the set state is 1 with set R=0 & CP = 1.To change to clear
state the i/p must be S=0, R=1 & CP =1, with both S = 1, R =1, the occurrence of clock pulse
causes both i/p to go 0.
Q(t+1)=S+R'Q
PROCEDURE:
1.Connect the input terminal of flip flop to high and low terminal of the logic circuit .
4.Vary the input (high/low) in the input terminals of various Flip flops.
OBSERVATIONS :
The truth table obtained matches with function of logic gates and hence verified.The truth table
that has been prepared as per the requirements and connection made. All the functions of the
multiple matches and verified as per the truth table.
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RESULT:
Truth table for RS is verified and the result was checked through LED’S.
PRECAUTIONS:
1.The connections should be made properly
2.The trainer kit should be handled prope
Experiment-No-8
Aim: - Study & Verify JK Flip Flop.
Theory:-
J K Flip Flop : J K Flip Flop is a refinement of RS Flip Flop in that the indeterminate state of
RS type is defined in JK type. Input J & K Behaves like input S & R. to set and clear Flip Flop
when inputs are applied to both J & K Simultaneously Flip Flop switches to its complementary
State. In this type of Flip Flop output Q is AND with Clock pulse, inputs so that the i/p are
available to the Flip Flop only when Q and CP both are 1.
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PROCEDURE:
1.Connect the input terminal of flip flop to high and low terminal of the logic circuit .
4.Vary the input (high/low) in the input terminals of various Flip flops.
OBSERVATIONS :
The truth table obtained matches with function of logic gates and hence verified.The truth table
that has been prepared as per the requirements and connection made. All the functions of the
multiple matches and verified as per the truth table.
RESULT:
Truth table for RS & JK flip-flop is verified and the result was checked through LED’S.
PRECAUTIONS:
1.The connections should be made properly
2.The trainer kit should be handled proper
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Experiment No-9
Theory:-
Multiplexer means transmitting a large no. of information unit over a small no. of channels or
lines. A digital multiplexer is a combinational circuit.That receives binary information from one
of 2n input data lines & directs it to a Single output lines. the selection of a particular input data
line for output is Determine by a set of selection input. A 2 n x 1 multiplexer has 2n input data
lines & n input selection lines whose bit combinations determine which input data are selected
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for the output. Each of the four data inputs I0 through I3 is applied to one input of an and gate.
The two selection inputs s1 & s0 are decoded to select a particular AND gate . The outputs of the
AND gates are applied to single OR gate to provide the single output. The multiplexer has six
inputs and one output. A multiplexer is also called data selectors, since it selects one of the many
inputs and steers the binary information to the output line.
Circuit Diagram
Truth Table
S0 S1 Output
input S0 S1 output
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Demultiplexer is a digital device that directs information from a single input to one of several
output which means one is to many. This enable to transmit the information on one of the 2n
possible output lines .the decoder can function as Demultiplexer if e line is taken as data input
line and line a and b are taken as selection lines. This is shown in figure of Demultiplexer. a
decoder with an enable input is referred to as decoder/Demultiplexer. It is enable to input that
makes a circuit a Demultiplexer. Decoder/Demultiplexer circuits can be connected together to
form a larger decoder circuits. fig. shows two 3*8 decoders which enable inputs connected to
form 4*16 decoders.
PROCEDURE :
1. Switch on the trainer and check the power supply .
2. Note that the supply voltage is +5v.
3. Study pin configuration of the 74150 circuit 7493 is provided mechanical switches which
has been in the trainer to choose correct input (1 Hz) to pin 14 of 7493 and corresponding
patch the output of 7493 ABCD TO THE INPUT OF 74150 .
4. The LED,s are connected to the 7493 counts from 0 to 15 the single output channel of the
multiplexer is energized alternately the 16 inputs to 74150 IC can be given through logic
switches also thus the trainer highlights how a 16 bit information is otherwise indicated
as 16*1 multiplexing..
5. Study the pin configuration of 74154-ckt. The device consists of 16 counter which is
provided in a trainer to give input to the Demultiplexer.
6. The clock input (1 Hz.) to pin 14 of 7493 and corresponding path the output of 7493
ABCD to the input of 74154 G1 and G2.the slope points of 74154 are to grounded
7. The LED’s are connected to output of demultiplexer.As the 7493 count from 0-15 the
output channel 1-16 of Demultiplexer are alternatively ABCD input can be given through
logic switch also.
8. The trainer highlights has a 4 bit information is being transmitted through 16 channels
which is indicated 4-16 Demultiplexer
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CIRCUIT DIAGRAM
OBSERVATIONS:
The truth table obtained matches with function of logic gates and hence verified.
The truth table that has been prepared as per the requirements and connection made. All
the functions of the multiple matches are verified as per the truth table.
RESULT:
Truth table for the MUX & DEMUX has been verified.
PRECAUTIONS:
1. The connections should be made properly
2. The trainer kit should be handled properly
EXPERIMENT NO. 10
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Aim: To Design and verify the truth table of code conversion from BCD to Excess-3
using basic Logic Gates.
Objective:
Design of different combinational circuits and their applications using basic
logic gates.
Creation and observation of the excess 3 code representation sequence
Exercising the design of code conversion logic circuits,
Creating the truth table of conversion functions from BCD to EXCESS 3
code
Developing skills in simplification of specified logical functions
Apparatus Required:
Prototyping board (breadboard)
DC Power Supply 5V Batery
Light Emitting Diode (LED)
Digital ICs: 7404 :Hex Inverter
7408 :Quad 2 input AND
7432 :Quad 2 input OR
Connecting Wires
Theory:
Code Converters: A code converter is a combinational circuit that must be inserted between the
two systems, to make them compatible even though each uses different code for same
information. It means that a code converter is a code translator from one code to the other. The
code converter is used since to systems using two different codes but they need to use the same
information. So the code converter is the solution.
BCD Codes: Numeric codes represent numeric information i.e. only numbers as a series of 0’s
and 1’s. Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD)
codes. A BCD code is one, in which the digits of a decimal number are encoded-one at a time
into group of four binary digits. There are a large number of BCD codes in order to represent
decimal digits0, 1, 2 …9, it is necessary to use a sequence of at least four binary digits. Such a
sequence of binary digits which represents a decimal digit is called code word.
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manner as BCD except that decimal number 3 is added to the each decimal unit before encoding
it to binary.
Circuit Diagram:
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INPUTS(BCD) OUTPUTS(Excess-3)
A B C D W X Y Z
Eqautions:
Z=D
Y = CD+C’D’=CD(C+D)’
W = B’(C+D) +B(C+D)’
Procedure :
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7. Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1 is
OFF Apply the various combination of inputs according to the truth table and observe the
condition of Output LEDs.
Observation Table: Input Variable: A B C D
Output Variable: W X Y Z
INPUTS(LED) OUTPUTS(LED)
A B C D W X Y Z
Calculation:
Kmap Simplification:
For W:
For X:
For Y
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For Z
Boolean Expression: W =
X =
Y=
Z=
Result and Discussions: Excess-3 code is a 4-bit unweighted code and can be obtained from the
corresponding value of BCD code by adding three to each coded number.Excess-3 code is self
complemnting in nature because 1’s complement of the coded number yields 9’s complement of
number itself.
Conclusion: BCD to Excess-3 code converter has been designed using basic logic gates and its
truth table verified.
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