Intersil ISL9238IRTZ Datasheet

DATASHEET
ISL9238 FN8877
Buck-Boost Narrow VDC Battery Charger with SMBus Interface and USB OTG Rev.3.00
Sep 7, 2017
The ISL9238 is a buck-boost Narrow Output Voltage DC (NVDC)

chargers. The ISL9238 provides the NVDC charging function,
Features
system bus regulation and protection features for tablet, • Buck-boost NVDC charger for 1-, 2-, 3-, or 4-cell Li-ion batteries
ultrabook, notebook, power bank, and any USB-C interface • Input voltage range 3.2V to 23.4V (no dead zone)
platform. Intersil’s advanced R3™ Technology is used to
provide high light-load efficiency and fast transient response. • System output voltage 2.4V to 18.304V
In Charging mode the ISL9238 takes input power from a wide • Autonomous charging option (automatic end of charging)
range of DC power sources (conventional AC/DC charger • System power monitor PSYS output, IMVP compliant
adapters, USB PD ports, travel adapters, etc.) and safely charges
battery packs with up to 4-series cell Li-ion batteries. • Up to 1MHz switching frequency
As a NVDC topology charger, it also regulates the system output to • Adapter current and battery current monitor (AMON/BMON)
a narrow DC range for stable system bus voltage. The system • PROCHOT# open-drain output, IMVP compliant
power can be provided from the adapter, battery or a combination
• Allows trickle charging of depleted battery
of both. The ISL9238 can operate with only a battery, only an
adapter or both connected. For Intel IMVP8 compliant systems • Ideal diode control in Turbo mode
the ISL9238 includes PSYS (System power monitor) functionality, • Reverse buck, boost and buck-boost operation from battery
which provides an analog signal representing total platform
power. The PSYS output will connect to a wide range of Intersil • Two-level adapter current limit available
IMVP8 core regulators to provide an IMVP8 compliant power • Battery Ship mode option
domain function.
• SMBus and auto-increment I2C compatible
The ISL9238 supports reverse buck, boost, or buck-boost
operation to input port from 2- to 4-cell batteries. • 4x4 32 Ld TQFN package
The ISL9238 has serial communication using SMBus/I2C that
allows programming of many critical parameters to deliver a
Applications
customized solution. • 1 to 4-cell tablet, ultrabook, notebook, power bank, and any
USB-C interface portable device requiring batteries
Related Literature
• For a full list of related documents please visit our web pages
- ISL9238 product page
OPTIONAL Rs1
VADP VSYS
Q1 Q4
L1
Q2 Q3
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
LGATE2
BOOT1
BOOT2
VSYS
CSIN
CSOP
CSIP
ASGATE Rs2
CSON
ADP
ACIN
ISL9238
ACOK
BGATE
PROCHOT# GND
AMON/BMON VBAT
VBAT
BATGONE
OTGPG/CMOUT
OTGEN/CMIN
PSYS
COMP
VDDP
PROG
SDA
VDD
SCL
DCIN
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FN8877 Rev.3.00 Page 1 of 45

Sep 7, 2017
ISL9238
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ISL9238 Buck-Boost Charger with USB OTG . . . . . . . . . . . . . 33
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Programming Charger Option . . . . . . . . . . . . . . . . . . . . . . . . . 34
Autonomous Charging Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 7 Battery Ship Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Battery Learn Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 8 Turbo Mode Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Two-Level Adapter Current Limit. . . . . . . . . . . . . . . . . . . . . . . 36
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SMBUS Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . .14 PSYS Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Trickle Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .14 System Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Charger Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
USB OTG (On the Go) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General SMBus Architecture . . . . . . . . . . . . . . . . . . . . . . . . .18 Stand-Alone Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Adapter Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . 39
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Battery Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . 39
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . 39
SMBus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Way Overcurrent Protection (WOCP) . . . . . . . . . . . . . . . . . . . 39
Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . 39
SMBus and I2C Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . 19 Switching Power MOSFET Gate Capacitance . . . . . . . . . . . . 39
ISL9238 SMBus Commands . . . . . . . . . . . . . . . . . . . . . . . . . .19 Adapter Input Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General Application Information . . . . . . . . . . . . . . . . . . . . . . 40
Setting Charging Current Limit . . . . . . . . . . . . . . . . . . . . . . . 21 Select the LC Output Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Setting Adapter Current Limit . . . . . . . . . . . . . . . . . . . . . . . . 21 Select the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Select the Switching Power MOSFET . . . . . . . . . . . . . . . . . . . 41
Setting Two-Level Adapter Current Limit Duration . . . . . . . . 22 Select the Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 41
Setting Maximum Charging Voltage or System Regulating
Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Setting Minimum System Voltage . . . . . . . . . . . . . . . . . . . . . . 23 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Setting PROCHOT# Threshold for Adapter Overcurrent
Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Setting PROCHOT# Threshold for Battery Over Discharging Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Current Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting PROCHOT# Debounce Time and Duration Time. . . . 24
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OTG Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OTG Current Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Input Voltage Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FN8877 Rev.3.00 Page 2 of 45

Sep 7, 2017
ISL9238
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG.
(Notes 4, 5) PART MARKING (°C) (RoHS COMPLIANT) DWG. #
ISL9238HRTZ (Note 1) 9238H -10 to +100 32 Ld 4x4 TQFN L32.4x4D
ISL9238IRTZ (Note 2) 9238I -40 to +100 32 Ld 4x4 TQFN L32.4x4D
ISL9238EVAL1Z Evaluation Board
NOTES:
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit, or “-T7A” suffix for 250 unit tape and reel options. Refer to TB347 for details on reel specifications.
2. Add “-T” suffix for 6k unit tape and reel option. Refer to TB347 for details on reel specifications.
3. Add “-T” suffix for 6k unit or “-TK” suffix for 1k unit tape and reel options. Refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), see product information page for ISL9238. For more information on MSL, see TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER I2C READ ADDRESS I2C WRITE ADDRESS
ISL9238 0b00010011 (0x13H) 0b00010010 (0x12H)
ISL9238A 0b00011011 (0x1BH) 0b00011010 (0x1AH)
FN8877 Rev.3.00 Page 3 of 45

Sep 7, 2017
ISL9238
Pin Configuration
ISL9238
(32 LD 4x4 TQFN)
TOP VIEW
OTGPG/CMOUT
AMON/BMON
BATGONE
BGATE
COMP
PROG
PSYS
VBAT
32 31 30 29 28 27 26 25
CSON 1 24 ACOK
CSOP 2 23 PROCHOT#
VSYS 3 22 SCL
BOOT2 4 GND 21 SDA

(BOTTOM PAD)
UGATE2 5 20 OTGEN/CMIN
PHASE2 6 19 ACIN
LGATE2 7 18 VDD
VDDP 8 17 DCIN
9 10 11 12 13 14 15 16
LGATE1
PHASE1
UGATE1
BOOT1
ASGATE
CSIN
ADP
CSIP
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
BOTTOM PAD GND Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. It should also be used as the
thermal pad for heat dissipation.
1 CSON Battery current sense “–” input. Connect to battery current resistor negative input. Place a 0.1µF ceramic capacitor
between CSOP to CSON to provide Differential mode filtering.
2 CSOP Battery current sense “+” input. Connect to battery current resistor positive input. Place a 0.1µF ceramic capacitor
between CSOP to CSON to provide Differential mode filtering.
3 VSYS Provides feedback voltage for MaxSystemVoltage regulation.
4 BOOT2 High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot
capacitor is charged through an internal boot diode connected from the VDDP to BOOT2 pins when the PHASE2 pin
drops below VDDP minus the voltage drop across the internal boot diode.
5 UGATE2 High-side MOSFET Q4 gate drive.
6 PHASE2 Current return path for the high-side MOSFET Q4 gate drive. Connect this pin to the node consisting of the high-side
MOSFET Q4 source, the low-side MOSFET Q3 drain and the one terminal of the inductor.
7 LGATE2 Low-side MOSFET Q3 gate drive.
8 VDDP Power supply for the gate drivers. Connect to VDD pin through a 4.7Ω resistor and connect a 1µF ceramic capacitor to
GND.
9 LGATE1 Low-side MOSFET Q2 gate drive.
10 PHASE1 Current return path for the high-side MOSFET Q1 gate drive. Connect this pin to the node consisting of the high-side
MOSFET Q1 source, the low-side MOSFET Q2 drain and the input terminal of the inductor.
11 UGATE1 High-side MOSFET Q1 gate drive.
12 BOOT1 High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 and PHASE1 pins. The boot
capacitor is charged through an internal boot diode connected from the VDDP to BOOT1 pins when the PHASE1 pin
drops below VDDP minus the voltage drop across the internal boot diode.
FN8877 Rev.3.00 Page 4 of 45

Sep 7, 2017
ISL9238
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
13 ASGATE Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional, if it is not used, leave ASGATE pin
floating.
When ASGATE turns on, it is clamped 10V below ADP pin voltage.
14 CSIN Adapter current sense “-” input.
15 CSIP Adapter current sense “+” input. The modulator also uses this for sensing input voltage in forward mode and output
voltage in reverse mode.
16 ADP Adapter input. Used to sense adapter voltage. When adapter voltage is higher than 3.2V, AGATE is turned on.
ADP pin is also one of the two internal low power LDO inputs.
17 DCIN Input of an internal LDO providing power to the IC. Connect a diode OR from adapter and system outputs. Bypass this
pin with an MLCC capacitor.
18 VDD Output of the internal LDO; provide the bias power for the internal analog and digital circuit. Connect a 1µF ceramic
capacitor to GND.
If VDD is pulled below 2V more than 1ms, ISL9238 will reset all the SMBus register values to the default.
19 ACIN Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN
pin voltage is greater than 0.8V.
20 OTGEN/ OTG function enable pin or stand-alone comparator input pin.
CMIN Pull high to enable OTG function. The OTG function is enabled when the control register is written to select OTG mode
and when the battery voltage is above 5.2V.
When OTG function is not selected, this pin is the general purpose stand-alone comparator input.
21 SDA SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor
according to SMBus specification.
22 SCL SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor
according to SMBus specification.
23 PROCHOT# Open-drain output. Pulled low when ACHOT, DCHOT or Low_VSYS is detected. IMVP-8 compliant. SMBus command to
pull low with OTGCURRENT, BAGONE, ACOK, and general purpose comparator (refer to Table 15 on page 28).
24 ACOK Adapter presence indicator output to indicate the adapter is ready.
25 BATGONE Input pin to the IC. Logic high on this pin indicates the battery has been removed. Logic low on this pin indicates the
battery is present.
BATGONE pin logic high will force BGATE FET to turn-off in any circumstances.
26 OTGPG/ Open-drain output. OTG function output power-good indicator or the stand-alone comparator output.
CMOUT When OTG function is enabled, low if OTG output voltage is not within regulation window.
When OTG function is not used, it is the general purpose comparator output.
27 PROG A resistor from PROG pin to GND sets the following configurations:
1. Default number of the battery cells in series, 1-, 2-, 3-, or 4-cell.
2. Default switching frequency 733kHz or 1MHz.
3. Default adapter current limit value 0.476A or 1.5A.
4. Autonomous Charging mode enable or disable
Refer to Table 23 for programming options.
28 COMP Error amplifier output. Connect a compensation network externally from COMP to GND.
29 AMON/ Adapter current, OTG output current, battery charging current, or battery discharging current monitor output.
BMON VAMON = 18x(VCSIP-VCSIN) for adapter current monitor
VOTGCMON = 18x(VCSIN-VCSIP) for OTG output current monitor
VBMON_DISCHARGING = 18x(VCSON-VCSOP) for battery discharging current monitor
VBMON_CHARGING = 36x(VCSOP-VCSON) for battery charging current monitor
30 PSYS Current source output that indicates the whole platform power consumption.
PSYS gain = 1.44µA/W (default) or 0.723µA/W
31 VBAT Battery voltage sensing. Used for trickle charging detection and Ideal Diode mode control. Connect to >1µF ceramic
capacitor from VBAT pin to GND.
VBAT pin is also one of the two internal low power LDO inputs.
32 BGATE Gate drive output to the P-channel FET connecting the system and the battery. This pin can go high to disconnect the
battery, low to connect the battery or operate in a Linear mode to regulate trickle charge current during trickle charge.
When BGATE turns on, it is clamped 10V below VSYS pin voltage.
FN8877 Rev.3.00 Page 5 of 45

Sep 7, 2017
ISL9238
Block Diagram
ADP DRV ASGATE
VBAT
DCIN + DRV ACOK
CMP
3.2V -
5V + ACIN
LDO LOW - 0.8V
PWR
LDO
VDD
+ BOOT1
CMP
3.8V -
UGATE1
+ DAC
CMP PHASE1
- AND
2.7V
CNTL
PROG LOGIC
MODULATOR AND DRIVER

SMBUS/I2C FOR OC/
DIGITAL OV/UV/
LGATE1
BUCK/BOOST PWM
BATGONE
CONTROL OT
AND
SCL FUSE
LOGIC GND
BUF
SDA
LGATE2
PROCHOT# DRV VDDP

VINDAC
+ PHASE2
CSIP
-
ACFB
UGATE2
CCFB VSYSDA C
+
PSYS MULT
VADP VSYS LOOP
- SELECTOR BOOT2
VBAT
ACDAC
+ COMP
CSIP + 18x ACFB
- ERROR
CSIN _ AMPLIFIER 5P2 + VBAT
CMP
- 5.2V
CCDAC OTGDAC +
AMON + + +
AMON/ CMP
18x CCFB - CSIP - 2.4V
BMON - -
BMON
TRICKLE VSYS
CONTROL BGATE LOGIC
DRIVER BGATE
+ CSOP
+ CSIP
CMP 36x
- OTGDAC - CSON
OTGPG/CMOUT
+ OTG +
CMP CONTROL 5P2 18x
- -
1.2V/2V
OTGEN/CMIN
FIGURE 2. BLOCK DIAGRAM
FN8877 Rev.3.00 Page 6 of 45

Sep 7, 2017
ISL9238
Simplified Application Circuit

VADP Rs1 VSYS
20m
Q1 Q4
L1
Q2 Q3
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
LGATE2
BOOT1
BOOT2
VSYS
CSIN
CSOP
CSIP
Rs2
ASGATE 10m
CSON
ADP
ACIN
ACOK ISL9238, ISL9238A

ISL9238
PROCHOT# GND BGATE
AMON/BMON VBAT
VBAT
BATGONE
OTGPG/CMOUT
OTGEN/CMIN
PSYS
PROG
VDDP
COMP
SDA
VDD
SCL
DCIN
VADP VSYS
FIGURE 3. SIMPLIFIED APPLICATION DIAGRAM
FN8877 Rev.3.00 Page 7 of 45

Sep 7, 2017
ISL9238
Absolute Maximum Ratings Thermal Information

CSIP, CSIN, DCIN, ADP, ASGATE . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +28V 32 Ld TQFN Package (Notes 6, 7) . . . . . . . 37 2
PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-2V(<20ns) to +28V Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-10°C to +100°C
BOOT1, UGATE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +33V Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
PHASE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +24V Storage Temperature Range (TS) . . . . . . . . . . . . . . . . . . . .-65°C to +175°C
PHASE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 2V(<20ns) to +24V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
BOOT2, UGATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +29V
LGATE1, LGATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +6.5V
LGATE1, LGATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 2V(<20ns) to +6.5V Recommended Operating Conditions
VBAT, VSYS, CSOP, CSON, BGATE . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V Ambient Temperature
VDD, VDDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V HRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
AMON/BMON, PSYS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
OTGEN, BATGONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Adapter voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4V to +23V
ACIN, ACOK, PROCHOT#, OTGPG . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
CLK, DAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT1-PHASE1, BOOT2-PHASE2 . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ACIN, SDA, SCL, DCIN, ACOK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating conditions: ADP = CSIP = CSIN = 5V and 20V, VSYS = VBAT = CSOP = CSON = 8V, unless otherwise
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified.
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 8) TYP (Note 8) UNIT
UVLO/ACOK
VADP UVLO Rising VADP_UVLO_r 3.1 3.3 3.5 V
VADP UVLO Hysteresis VADP_UVLO_h 600 mV
VBAT UVLO Rising VBAT_UVLO_r 2.30 2.45 2.65 V
VBAT UVLO Hysteresis VBAT_UVLO_h 400 mV
VBAT 5P2V Rising VBAT_5P2_r 5.05 5.20 5.65 V
VBAT 5P2V Hysteresis VBAT_5P2_h 490 mV
VDD 2P7 POR Falling, SMBus and VDD_2P7_f 2.50 2.70 2.9 V
BGATE/BMON Active Threshold
VDD 2P7 POR Hysteresis VDD_2P7_h 150 mV
VDD 3P8 POR Rising, Modulator and VDD_3P8_r 3.6 3.8 3.9 V
Gate Driver Active
VDD 3P8 POR Hysteresis VDD_3P8_h 150 mV
ACIN Rising ACIN_r 0.775 0.800 0.825 V
ACIN Hysteresis ACIN_h 50 mV
FN8877 Rev.3.00 Page 8 of 45

Sep 7, 2017
ISL9238
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)
MIN MAX
LINEAR REGULATOR
VDD Output Voltage VDD 6V < VDCIN < 23V, no load 4.5 5.0 5.5 V
VDD Dropout Voltage VDD_dp 30mA, VDCIN = 4V 85 mV
VDD Overcurrent Threshold VDD_OC HRTZ 80 115 150 mA
VDD Overcurrent Threshold IRTZ 75 115 150 mA
Battery Current IBAT1 Battery only, BGATE on, PSYS OFF, BMON OFF, 24 50 µA
VBAT = 16.8V, DCIN current comes from battery,
IBAT = IVBAT + ICSOP + ICSON + IDCIN + IVSYS
IBAT2 Battery only, BGATE on, PSYS OFF, BMON ON, 74 µA
IBAT3 Battery only, BGATE on, PSYS ON, BMON OFF, 905 1055 µA
ADAPTER CURRENT REGULATION, Rs1 = 20mΩ
Adapter Current Accuracy CSIP-CSIN = 80mV 4 A
-2 2 %
CSIP-CSIN = 40mV 2 A
-2.5 2.5 %
CSIP-CSIN = 10mV 0.5 A
-10 10 %
Adapter Current PROCHOT# Threshold IADP_HOT_TH10 ACProchot = 0x1580H (5504mA) 5504 mA
Rs1 = 20mΩ -1.5 1.5 %
ACProchot = 0x0A80H (2688mA) 2688 mA
-3.0 3.0 %
ACProchot = 0x0400H (1024mA) 1024 mA
-6.0 6.0 %
SYSTEM VOLTAGE REGULATION
Maximum System Voltage Accuracy HRTZ MaxSystemVoltage for 1-cell (4.2V) -0.75 0.75 %
MaxSystemVoltage for 1-cell (8.4V) -0.6 0.6 %
MaxSystemVoltage for 3-cell and 4-cell (12.6V -0.5 0.5 %
and 16.8V)
IRTZ MaxSystemVoltage for 1-cell (4.2V) -0.85 0.85 %
MaxSystemVoltage for 1-cell (8.4V) -0.7 0.7 %
MaxSystemVoltage for 3-cell and 4-cell (12.6V 0.55 0.50 %
and 16.8V)
Minimum System Voltage Accuracy -3 3 %
Input Voltage Regulation Accuracy 4.096V 3.98 4.22 %
FN8877 Rev.3.00 Page 9 of 45

Sep 7, 2017
ISL9238
MIN MAX
CHARGE CURRENT REGULATION, Rs2 = 10mΩ (LIMITS APPLY ACROSS TEMPERATURE RANGE OF 0°C TO +85°C)
Charge Current Accuracy CSOP-CSON = 60mV 6.03 A
-2 2 %
CSOP-CSON = 20mV 2.01 A
-4 4 %
-5 6 %
-10 12 %
BGATE CLAMP
VSYS-VBGATE ON Charging enabled 6.80 8.30 9.16 V
VSYS-VBGATE OFF Charging disabled 0 V
ASGATE CLAMP
VADP-VASGATE ON 12 V
VSYS-VBGATE OFF 0 V
TRICKLE CHARGING CURRENT REGULATION, Rs2 = 10mΩ (LIMITS APPLY ACROSS TEMPERATURE RANGE OF 0°C TO +85°C)
Trickle Charge Current Accuracy Trickle, options 512mA 410 512 614 mA
Trickle, options 256mA 205 256 334 mA
Trickle, 128mA 77 128 192 mA
Trickle, 64mA 16 64 128 mA
Fast Charge to Trickle Charge VSYS - VBGATE 4.23 5.18 5.97 V
Threshold
Trickle Charge to Fast Charge VSYS - VBGATE 55 130 210 mV
Threshold Hysteresis
Fast Charge to Trickle Charge BGATE VSYS > 7V, VFB >> VREF 1.15 V
Threshold
Trickle Charge to Fast Charge BGATE VSYS > 7V, VFB >> VREF 50 mV
Threshold Hysteresis
IDEAL DIODE MODE
Entering Ideal Diode Mode VSYS BGATE off, VSYS falling 100 150 200 mV
Voltage Threshold VVBAT - VVSYS
Exiting Ideal Diode Mode Battery Rs2 = 10mΩ 110 200 290 mA
Discharging Current Threshold
Exiting Ideal Diode Mode Battery Rs2 = 10mΩ 50 130 200 mA
Charging Current Threshold
BGATE Source VSYS - BGATE = 2V, charging disabled 4 6 10 mA
BGATE Sink BGATE - GND = 2V, charging enabled 20 30 40 µA
BGATE Sink BGATE - GND = 2V, in Ideal Diode mode 6 µA
AMON/BMON
INPUT CURRENT SENSE AMPLIFIER, Rs1 = 20mΩ
CSIP/CSIN Input Voltage Range VCSIP/N 4 23 V/V
AMON Gain 17.97 V/V
AMON Accuracy VCSIP - VCSIN = 100mV (5A), CSIP = 5V - 20V -2 2 %
VAMON = 17.9 * (CSIP - CSIN)
VCSIP - VCSIN = 20mV (1A), CSIP = 5V - 20V -5 5 %
VCSIP - VCSIN = 10mV (0.5A), CSIP = 5V - 20V -10 10 %
VCSIP - VCSIN = 2mV (0.1A), CSIP = 5V - 20V -40 40 %
FN8877 Rev.3.00 Page 10 of 45

Sep 7, 2017
ISL9238
MIN MAX
Reverse AMON Gain 17.9 V/V
AMON Accuracy VCSIN - VCSIP = 80mV (4A), CSIP = 4V - 22V -2.5 2.5 %
VAMON = 17.9 * (CSIN - CSIP) VCSIN - VCSIP = 20mV (1A), CSIP = 4V - 22V -6.5 4.5 %
VCSIN - VCSIP = 10mV (0.5A), CSIP = 4V - 22V -12 9 %
VCSIN - VCSIP = 5.12mV (0.256A), CSIP = 4V - 22V -25 25 %
AMON Minimum Output Voltage VCSIP - VCSIN = 0V 30 mV
DISCHARGE CURRENT SENSE AMPLIFIER, Rs2 = 10mΩ
BMON Gain (Battery Discharging) 17.78 V/V
BMON Accuracy VCSON - VCSOP = 100mV (10A), VCSON = 8V -2 2 %
VBMON = 17.9 * (VCSON - VCSOP)
VCSON - VCSOP = 20mV (2A), VCSON = 8V -7.0 -1.5 3.0 %
VCSON - VCSOP = 10mV (1A), VCSON = 8V -10.5 -2.5 5.5 %
VCSON - VCSOP = 6mV (0.6A), VCSON = 8V -17 -4 12 %
BMON Gain (Battery Charging) Limits apply across temperature range of 0°C to 35.7 V/V
+85°C
BMON Accuracy VCSOP - VCSON = 60mV (6A), VCSON = 8V -3 3 %
VBMON = 35.7* (VCSON - VCSOP) VCSOP - VCSON = 40mV (4A), VCSON = 8V -4 4 %
VCSOP - VCSON = 10mV (1A), VCSON = 8V -10 10 %
VCSOP - VCSON = 5mV (0.5A), VCSON = 8V -25 25 %
BMON Minimum Output Voltage VCSOP - VCSON = 0V 30 mV
Discharging Current PROCHOT# IDIS_HOT_TH DCProchot = 2.048A 1.77 2.08 2.39 A
Threshold, Rs2 = 10mΩ
Discharging Current PROCHOT# IDIS_HOT_TH DCProchot = 12A 10.8 13.5 17 A
Threshold, Battery Only, Rs2 = 10mΩ
DCProchot = 6A 5.35 6.5 8 A
AMON/BMON Source Resistance (Note 9) 5 Ω
AMON/BMON Sink Resistance (Note 9) 5 Ω
BATGONE AND OTGEN
High-Level Input Voltage 0.9 V
Low-Level Input Voltage 0.4 V
Input Leakage Current VBATGONE = 3.3V, 5V; VOTGEN = 3.3V, 5V 1 µA
PROCHOT#
PROCHOT# Debounce Time Prochot# Debounce register Bit<1:0> = 11 0.85 1 1.15 ms
Prochot# Debounce register Bit<1:0> = 10 425 500 575 µs
PROCHOT# Duration Time Prochot# Duration register Bit<2:0> = 011 8.5 10 11.5 ms
Prochot# Duration register Bit<2:0> = 001 17 20 23 ms
Low VSYS PROCHOT# Trip Threshold VLOW_VSYS_HOT Control1 register Bit<1:0> = 00 5.8 6.0 6.2 V
Control1 register Bit<1:0> = 01 6.1 6.3 6.5 V
FN8877 Rev.3.00 Page 11 of 45

Sep 7, 2017
ISL9238
MIN MAX
PSYS
PSYS Output Current IPSYS VCSIP = 19V, VCSIP-CSIN = 80mV, -5 5 %
Rs1 = 20mΩ Control3 Bit<9> = 1 VBAT = 12V, VCSOP-CSON = 10mV
Rs2 = 10mΩ
VCSIP = 19V, VCSIP-CSIN = 80mV, -5.3 5.3 %
IPSYS= 1.493 x Power + 1.43µA
VBAT = 12V, VCSOP-CSON = -10mV
IPSYS VCSIP = 19V, VCSIP-CSIN = 0mV, -7 7 %
Control3 Bit<9> = 0 VBAT = 8.4V, VCSOP-CSON = 20mV
VCSIP = 19V, VCSIP-CSIN = 0mV, -15 15 %
VBAT = 4.2V, VCSOP-CSON = 10mV
Maximum PSYS Output Voltage VPSYS_MAX 4 V
OTG
OTG Voltage OTGVoltage register = 5.12V 4.95 5.03 5.12 V
OTG Current (5V to 12V) OTGCurrent register = 512mA 435 512 589 mA
OTGCurrent register = 1024mA 922 1024 1126 mA
OTGCurrent register = 4096mA 3975 4096 4240 mA
GENERAL PURPOSE COMPARATOR
General Purpose Comparator Rising Reference = 1.2V 1.15 1.2 1.25 V
Threshold
Reference = 2V 1.95 2 2.05 V
General Purpose Comparator Reference = 1.2V 30 60 90 mV
Hysteresis
Reference = 2V 30 60 90 mV
PROTECTION
VSYS Overvoltage Rising Threshold MaxSystemVoltage register value = 8.4V 8.95 9.15 9.35 V
VSYS Overvoltage Hysteresis 250 400 550 mV
Adapter Way Overcurrent Rising Rs1 = 20mΩ 7.5 12 18 A
Threshold (Note 9)
Adapter Way Overcurrent Hysteresis 5 6.6 8 A
Battery Discharge Way Overcurrent Rs2 = 10mΩ 10 20 32 A
Rising Threshold (Note 9)
Battery Discharge Way Overcurrent 7.5 9 10.5 A
Hysteresis (Note 9)
Over-Temperature Threshold (Note 9) 140 150 160 °C
Adapter Overvoltage Rising Threshold 22.5 23.4 24 V
Adapter Overvoltage Hysteresis 150 350 500 mV
OTG Undervoltage Falling Threshold OTG voltage = 5.004V 3.45 3.80 4.25 V
OTG Overvoltage Rising Threshold OTG voltage = 5.004V 5.8 6.2 6.6 V
FN8877 Rev.3.00 Page 12 of 45

Sep 7, 2017
ISL9238
MIN MAX
OSCILLATOR
Oscillator Frequency. Digital Core Only 0.85 1 1.15 MHz
Digital Debounce Time Accuracy -15 15 %
(Note 9)
MISCELLANEOUS
Switching Frequency Accuracy COMP>1.7V and not in period stretching -15 15 %
Battery Learn Mode Auto-Exit MinSystemVoltage = 5.376V 5.05 5.35 5.7 V
Threshold Control1 register Bit<13> = 1
Battery Learn Mode Auto-Exit 180 330 480 mV
Hysteresis (Note 9)
SMBus
SDA/SCL Input Low Voltage 3.3V 0.8 V
SDA/SCL Input High Voltage 3.3V 2 V
SDA/SCL Input Bias Current 3.3V 1 µA
SDA, Output Sink Current SDA = 0.4V, on 4 mA
SMBus Frequency fSMB 10 400 kHz
GATE DRIVER
UGATE1 Pull-Up Resistance UG1RPU 100mA source current 800 1200 mΩ
UGATE1 Source Current UG1SRC UGATE1 - PHASE1 = 2.5V 1.3 2 A
UGATE1 Pull-Down Resistance UG1RPD 100mA sink current 350 475 mΩ
UGATE1 Sink Current UG1SNK UGATE1 - PHASE1 = 2.5V 1.9 2.8 A
LGATE1 Pull-Up Resistance LG1RPU 100mA source current 800 1200 mΩ
LGATE1 Source Current LG1SRC LGATE1 - GND = 2.5V 1.3 2 A
LGATE1 Pull-Down Resistance LG1RPD 100mA sink current 300 450 mΩ
LGATE1 Sink Current LG1SNK LGATE1 - GND = 2.5V 2.3 3.5 A
LGATE2 Pull-Up Resistance LG2RPU 100mA source current 800 1200 mΩ
LGATE2 Source Current LG2SRC LGATE2 - GND = 2.5V 1.3 2 A
LGATE2 Pull-Down Resistance LG2RPD 100mA sink current 300 450 mΩ
LGATE2 Sink Current LG2SNK LGATE2 - GND = 2.5V 2.3 3.5 A
UGATE2 Pull-Up Resistance UG2RPU 100mA source current 800 1200 mΩ
UGATE2 Source Current UG2SRC UGATE2 - PHASE2 = 2.5V 1.3 2 A
UGATE2 Pull-Down Resistance UG2RPD 100mA sink current 300 450 mΩ
UGATE2 Sink Current UG2SNK UGATE2 - PHASE2 = 2.5V 2.3 3.5 A
UGATE1 to LGATE1 Dead Time tUG1LG1DEAD 10 20 40 ns
LGATE1 to UGATE1 Dead Time tLG1UG1DEAD 10 20 40 ns
LGATE2 to UGATE2 Dead Time tLG2UG2DEAD 10 20 40 ns
UGATE2 to LGATE2 Dead Time tUG2LG2DEAD 10 20 40 ns
FN8877 Rev.3.00 Page 13 of 45

Sep 7, 2017
ISL9238
SMBUS Timing Specification (Note 9)
MIN MAX
PARAMETERS SYMBOL TEST CONDITIONS (Note 8) TYP (Note 8) UNIT
SMBus Frequency FSMB 10 400 kHz
Bus Free Time tBUF 4.7 µs
Start Condition Hold Time from SCL tHD:STA 4 µs
Start Condition Set-Up Time from SCL tSU:STA 4.7 µs
Stop Condition Set-Up Time from SCL tSU:STO 4 µs
SDA Hold Time from SCL tHD:DAT 300 ns
SDA Set-Up Time from SCL tSU:DAT 250 ns
SCL Low Period tLOW 4.7 µs
SCL High Period tHIGH 4 µs
SMBus Inactivity Timeout Maximum charging period without a SMBus 175 s

Write to MaxSystemVoltage or ChargeCurrent
register
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Limits established by characterization and are not production tested.
Gate Driver Timing Diagram

PWM
tLGFUGR tFU
tRU
UGATE 1V
LGATE 1V
tRL
tFL tUGFLGR
FIGURE 4. GATE DRIVER TIMING DIAGRAM
FN8877 Rev.3.00 Page 14 of 45

Sep 7, 2017
ISL9238
Typical Performance
FIGURE 5. ADAPTER INSERTION, VADP = 2OV, VBAT = 11V, FIGURE 6. ADAPTER INSERTION, VADP = 2OV, VBAT = 11V,
CHARGECURRENT = 0A CHARGECURRENT = 0A (Figure 5 ZOOM IN)
FIGURE 7. ADAPTER REMOVAL, VADP = 2OV, VBAT = 11V, CHARGECURRENT = 0A
FIGURE 8. ADAPTER VOLTAGE RAMPS UP, BOOST -> FIGURE 9. ADAPTER VOLTAGE RAMPS DOWN, BUCK ->
BUCK-BOOST -> BUCK OPERATION MODE TRANSITION BUCK-BOOST -> BOOST OPERATION MODE TRANSITION
FN8877 Rev.3.00 Page 15 of 45

Sep 7, 2017
ISL9238
Typical Performance (Continued)
FIGURE 10. BOOST MODE, OUTPUT VOLTAGE LOOP TO ADAPTER FIGURE 11. BOOST MODE, CHARGING CURRENT LOOP TO ADAPTER
CURRENT LOOP TRANSITION. VADP = 5V, CURRENT LOOP TRANSITION. VADP = 5V,
MAXSYSTEMVOLTAGE = 12.576V, VBAT = 11V, SYSTEM MAXSYSTEMVOLTAGE = 12.5766V, VBAT = 11V, SYSTEM
LOAD 0.5A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A, LOAD 0.5A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A CHARGECURRENT = 1A
FIGURE 12. BUCK-BOOST MODE, OUTPUT VOLTAGE LOOP TO FIGURE 13. BUCK-BOOST MODE, CHARGING CURRENT LOOP TO
ADAPTER CURRENT LOOP TRANSITION. VADP = 12V, ADAPTER CURRENT LOOP TRANSITION. VADP = 12V,
LOAD 1A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A, LOAD 1A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
FN8877 Rev.3.00 Page 16 of 45

Sep 7, 2017
ISL9238
FIGURE 14. BUCK MODE, OUTPUT VOLTAGE LOOP TO ADAPTER FIGURE 15. BUCK MODE, CHARGING CURRENT LOOP TO ADAPTER
CURRENT LOOP TRANSITION. VADP = 20V, CURRENT LOOP TRANSITION. VADP = 20V,
LOAD 2A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A, LOAD 2A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
FIGURE 16. BOOST MODE, OUTPUT VOLTAGE LOOP TO INPUT FIGURE 17. BOOST MODE, CHARGING CURRENT LOOP TO INPUT
VOLTAGE LOOP TRANSITION. VADP = 5.004V, VOLTAGE LOOP TRANSITION. VADP = 5.004V,
MAXSYSTEMVOLTAGE = 12.576V, VBAT = 11V, MAXSYSTEMVOLTAGE = 12.576V, VBAT = 11V,
VINDAC = 4.437V, SYSTEM LOAD 0A TO 10A STEP, VINDAC = 4.437V, SYSTEM LOAD 0A TO 10A STEP,
CHARGECURRENT = 0A CHARGECURRENT = 0.5A
FN8877 Rev.3.00 Page 17 of 45

Sep 7, 2017
ISL9238
FIGURE 18. OTG MODE ENABLE, OTG ENABLE 150ms DEBOUNCE TIME FIGURE 19. OTG MODE 0.5A TO 2A TRANSIENT LOAD,
OTG VOLTAGE = 5.12V
General SMBus Architecture START and STOP Conditions

Figure 22 START condition is a HIGH to LOW transition of the SDA
VDD SMB line while SCL is HIGH.
INPUT SMBUS SLAVE The STOP condition is a LOW to HIGH transition on the SDA line
SCL
while SCL is HIGH. A STOP condition must be sent before each
OUTPUT CONTROL STATE START condition.
MACHINE
SMBUS MASTER INPUT INPUT REGISTERS
MEMORY
SCL SDA etc...
CONTROL OUTPUT OUTPUT CONTROL
SDA
CPU INPUT
SDA
INPUT SMBUS SLAVE
CONTROL OUTPUT
SCL
OUTPUT CONTROL STATE
SCL
MACHINE S P
INPUT REGISTERS
MEMORY
SDA etc...
START STOP
SCL SDA OUTPUT CONTROL CONDITION CONDITION
FIGURE 22. START AND STOP WAVEFORMS

TO OTHER
SLAVE DEVICES
FIGURE 20. GENERAL SMBus ARCHITECTURE Acknowledge

Each address and data transmission uses 9 clock pulses. The
Data Validity ninth pulse is the Acknowledge bit (ACK). After the start
The data on the SDA line must be stable during the HIGH period condition, the master sends 7 slave address bits and a R/W bit
of the SCL, unless generating a START or STOP condition. The during the next 8 clock pulses. During the 9th clock pulse, the
HIGH or LOW state of the data line can only change when the device that recognizes its own address holds the data line low to
clock signal on the SCL line is LOW. Refer to Figure 21. acknowledge (Refer to Figure 23). The acknowledge bit is also
used by both the master and the slave to acknowledge receipt of
register addresses and data.
SDA
SCL
DATA LINE CHANGE

STABLE OF DATA
DATA VALID ALLOWED
FIGURE 21. DATA VALIDITY
FN8877 Rev.3.00 Page 18 of 45

Sep 7, 2017
ISL9238
SMBus and I2C Compatibility

MSB The ISL9238 SMBus minimum input logic high voltage is 2V, so it
SDA is compatible with I2C with higher than 2V pull-up power supply.
The ISL9238 SMBus registers are 16 bits, so it is compatible with
SCL 1 2 8 9 16 bits I2C or 8 bits I2C with auto-increment capability.
START ACKNOWLEDGE ISL9238 SMBus Commands

FROM SLAVE
The ISL9238 receives control inputs from the SMBus interface after
FIGURE 23. ACKNOWLEDGE ON THE SMBus Power-On Reset (POR). The serial interface complies with the
System Management Bus Specification, which can be downloaded
from www.smbus.org. The ISL9238 uses the SMBus Read-word and
SMBus Transactions Write-word protocols (see Figure 24) to communicate with the host
All transactions start with a control byte sent from the SMBus system and a smart battery. The ISL9238 is an SMBus slave device
master device. The control byte begins with a Start condition, and does not initiate communication on the bus. It responds to the
followed by 7 bits of slave address (0001001) and the R/W bit. 7-bit address 0b0001001_ as follows:
The R/W bit is 0 for a WRITE or 1 for a READ. If any slave device
on the SMBus bus recognizes its address, it will acknowledge by Read and Write address for ISL9238 is:
pulling the Serial Data (SDA) line low for the last clock cycle in Read address = 0b00010011 (0X13H)/0b00011011 (0X1BH)
the control byte. If no slave exists at that address or it is not ready
to communicate, the data line will be one, indicating a not Write address = 0b00010010 (0X12H)/0b00011010 (0X1AH)
acknowledge condition. The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs
Once the control byte is sent and the ISL9238 acknowledges it, that can accommodate slow edges. Choose pull-up resistors for
the second byte sent by the master must be a register address SDA and SCL to achieve rise times according to the SMBus
byte such as 0x14 for the ChargeCurrent register. The register specifications.
address byte tells the ISL9238 which register the master will The illustration in this datasheet is based on current sensing
write or read. See Table 2 on page 20 for details of the registers. resistors Rs1 = 20mΩand Rs2 = 10mΩ unless otherwise
Once the ISL9238 receives a register address byte, it will respond specified.
with an acknowledge.
Byte Format
Every byte put on the SDA line must be 8 bits long and must be
followed by an acknowledge bit. Data is transferred with the
Most Significant Bit first (MSB) and the least significant bit last
(LSB). The LO BYTE data is transferred before the HI BYTE data.
For example, when writing 0x41A0, 0xA0 is written first and 0x41
is written second.
WRITE TO A REGISTER
SLAVE REGISTER LO BYTE HI BYTE
S A A A A P
ADDR + W ADDR DATA DATA
READ FROM A REGISTER

SLAVE REGISTER SLAVE LO BYTE HI BYTE
S A A P S A A N P
ADDR + W ADDR ADDR + R DATA DATA
DRIVEN BY THE
S START A ACKNOWLEDGE
MASTER
NO
P STOP N P DRIVEN BY THE IC
ACKNOWLEDGE
FIGURE 24. SMBus READ AND WRITE PROTOCOL
FN8877 Rev.3.00 Page 19 of 45

Sep 7, 2017
ISL9238
TABLE 2. REGISTER SUMMARY

REGISTER REGISTER READ/ NUMBER OF
NAMES ADDRESS WRITE BITS DESCRIPTION DEFAULT
ChargeCurrentLimit 0x14 R/W 11 [12:2]11-bit, LSB size 4mA, total range 6080mA with 0A
10mΩ RS2
MaxSystemVoltage 0x15 R/W 12 [14:3]12-bit, LSB size 8mV, total range 18.304V 4.192V for 1-cell
8.384V for 2-cell
12.576V for 3-cell
16.768V for 4-cell
T1 and T2 0x38 R/W 6 Configure two-level adapter current limit duration 0x000h
Control0 0x39 R/W 16 Configure various charger options 0x0000h
Information1 0x3A R 16 Indicate various charger status 0x0000h
AdapterCurrentLimit2 0x3B R/W 11 [12:2]11-bit, LSB size 4mA, total range 6080mA with 1500mA
20mΩ RS1
Control1 0x3C R/W 16 Configure various charger options 0x0000h
Control2 0x3D R/W 16 Configure various charger options 0x0000h
MinSystemVoltage 0x3E R/W 6 [13:8]6-bit, LSB size 256mV, total range 13.824V 2.56V for 1-cell
5.12V for 2-cell
7.68V for 3-cell
10.24V for 4-cell
AdapterCurrentLimit1 0x3F R/W 11 [12:2]11-bit, LSB size 4mA, total range 6080mA with Set by PROG pin
20mΩ RS1
Revision ID 0x44 R 8 Revision ID register - Read only N/A
0x01 - Rev1
0x02 - Rev2
ACProchot# 0x47 R/W 6 [12:7] adapter current Prochot# threshold 3.072A
Default 3.072A, 128mA resolution for 20mΩ Rs1.
DCProchot# 0x48 R/W 6 [13:8] Battery discharging current Prochot# threshold 4.096A
Default 4.096A, 256mA resolution for 10mΩ Rs2.
OTG Voltage 0x49 R/W 12 [14:3] 12-bit, LSB size 12mV, total range 27.456V 5.004V
OTG mode voltage reference
OTG Current 0x4A R/W 6 [12:7] 6-bit, LSB size 128mAV, total range 4.096A 0.512A
OTG mode maximum current limit
VIN Voltage 0x4B R/W 6 [13:8] 6-bit, LSB size 341.3mV, total range 18.432mV 4.096V
VIN loop voltage reference
Control3 0x4C R/W 16 Configure various charger options 0x0000h
Information2 0x4D R 16 Indicate various charger status 0x0000h
Control4 0x4E R/W 8 [7:0] 8-bit, Configure various charger options 0x0000h
Manufacturer ID 0xFE R 8 Manufacturers ID register – 0x49 - Read only 0x0049h
Device ID 0xFF R 8 Device ID register - 0x0C- Read only 0x000Ch
FN8877 Rev.3.00 Page 20 of 45

Sep 7, 2017
ISL9238
Setting Charging Current Limit TABLE 4. ChargeCurrentLimit REGISTER 0x14H (11-BIT, 8mA STEP,
5mΩ SENSE RESISTOR, x36)
To set the charging current limit, write a 16-bit ChargeCurrentLimit BIT DESCRIPTION
command (0x14H or 0b00010100) using the Write-word protocol
shown in Figure 24 on page 19 and the data format shown in <1:0> Not used
Table 3 for a 10mΩ Rs2 or Table 4 for a 5mΩ Rs2. <2> 0 = Add 0mA of charge current limit.
1 = Add 8mA of charge current limit.
The ISL9238 limits the charging current by limiting the
<3> 0 = Add 0mA of charge current limit.
CSOP-CSON voltage. By using the recommended current sense
resistor values Rs1 = 20mΩand Rs2 = 10mΩ, the register’s LSB
always translates to 4mA of charging current. The <4> 0 = Add 0mA of charge current limit.
ChargeCurrentLimit register accepts any charging current 1 = Add 32mA of charge current limit.
command but only the valid register bits will be written to the <5> 0 = Add 0mA of charge current limit.
register and the maximum values is clamped at 6080mA for 1 = Add 64mA of charge current limit.
Rs2 = 10mΩ. <6> 0 = Add 0mA of charge current limit.
After POR, the ChargeCurrentLimit register is reset to 0x0000H. To
set the battery charging current value, write a non-zero number to <7> 0 = Add 0mA of charge current limit.
the ChargeCurrentLimit register. The ChargeCurrentLimit register 1 = Add 256mA of charge current limit.
can be read back to verify its content. <8> 0 = Add 0mA of charge current limit.
Table 24 shows the conditions to enable fast charging according to
the ChargeCurrentLimit register setting.
TABLE 3. ChargeCurrentLimit REGISTER 0x14H (11-BIT, 4mA STEP, <10> 0 = Add 0mA of charge current limit.
10mΩ SENSE RESISTOR, x36) 1 = Add 2048mA of charge current limit.
BIT DESCRIPTION <11> 0 = Add 0mA of charge current limit.
<1:0> Not used
<2> 0 = Add 0mA of charge current limit. <12> 0 = Add 0mA of charge current limit.
<3> 0 = Add 0mA of charge current limit. <13:15> Not used
1 = Add 8mA of charge current limit. Maximum <12:2> = 10111110000 12160mA
1 = Add 16mA of charge current limit. Setting Adapter Current Limit
To set the adapter current limit, write a 16-bit
AdapterCurrentLimit1 command (0x3FH or 0b00111111) and/or
<6> 0 = Add 0mA of charge current limit. AdapterCurrentLimit2 command (0x3BH or 0b00111011) using
1 = Add 64mA of charge current limit. the Write-word protocol shown in Figure 24 on page 19 and the
<7> 0 = Add 0mA of charge current limit. data format shown in Table 5 on page 22 for a 20mΩ Rs1 or
1 = Add 128mA of charge current limit. Table 6 on page 22 for a 10mΩ Rs1.
The ISL9238 limits the adapter current by limiting the CSIP-CSIN
voltage. By using the recommended current sense resistor values,
<9> 0 = Add 0mA of charge current limit. the register’s LSB always translates to 4mA of adapter current. Any
1 = Add 512mA of charge current limit. adapter current limit command will be accepted but only the valid
<10> 0 = Add 0mA of charge current limit. register bits will be written to the AdapterCurrentLimit1 and
1 = Add 1024mA of charge current limit. AdapterCurrentLimit2 registers and the maximum values is
<11> 0 = Add 0mA of charge current limit. clamped at 6080mA for Rs1 = 20mΩ.
After adapter POR, the AdapterCurrentLimit1 register is reset to
<12> 0 = Add 0mA of charge current limit. the value programmed through the PROG pin resistor. The
1 = Add 4096mA of charge current limit. AdapterCurrentLimit2 register is set to its default value of 1.5A or
<13:15> Not used keep the value that is written to it previously if battery is present
Maximum <12:2> = 10111110000 6080mA first. The AdapterCurrentLimit1 and AdapterCurrentLimit2
registers can be read back to verify their content.
To set a second level adapter current limit, write a 16-bit
AdapterCurrentLimit2 (0x3BH or 0b00111011) command using
the Write-word protocol shown in Figure 24 and the data format as
shown in Table 5 for a 20mΩ Rs1 or Table 6 for a 10mΩ Rs1.
FN8877 Rev.3.00 Page 21 of 45

Sep 7, 2017
ISL9238
The AdapterCurrentLimit2 register has the same specification as TABLE 6. AdapterCurrentLimit1 REGISTER 0x3FH AND
the AdapterCurrentLimit1 register. Refer to “Two-Level Adapter AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, 8mA
Current Limit” on page 36 for detailed operation. STEP, 10mΩ SENSE RESISTOR, x18) (Continued)
TABLE 5. AdapterCurrentLimit1 REGISTER 0x3FH AND BIT DESCRIPTION

AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, <9> 0 = Add 0mA of adapter current limit.
4mA STEP, 20mΩ SENSE RESISTOR, x18) 1 = Add 1024mA of adapter current limit.
BIT DESCRIPTION <10> 0 = Add 0mA of adapter current limit.
<1:0> Not used 1 = Add 2048mA of adapter current limit.
<2> 0 = Add 0mA of adapter current limit. <11> 0 = Add 0mA of adapter current limit.
1 = Add 4mA of adapter current limit. 1 = Add 4096mA of adapter current limit.
<3> 0 = Add 0mA of adapter current limit. <12> 0 = Add 0mA of adapter current limit.
1 = Add 8mA of adapter current limit. 1 = Add 8192mA of adapter current limit.
<4> 0 = Add 0mA of adapter current limit. <13:15> Not used
1 = Add 16mA of adapter current limit.
Maximum <12:4> = 10111110000 12160mA
<5> 0 = Add 0mA of adapter current limit.
Setting Two-Level Adapter Current Limit
1 = Add 64mA of adapter current limit. Duration
<7> 0 = Add 0mA of adapter current limit. For a two-level adapter current limit, write a 16-bit T1 and T2
1 = Add 128mA of adapter current limit. command (0x38H or 0b00111000) using the Write-word protocol
shown in Figure 24 and the data format shown in Table 5 or
Table 6 to set the AdapterCurrentLimit1 duration t1. Write a
16-bit T2 command (0x38H or 0b00111000) to set
<9> 0 = Add 0mA of adapter current limit. AdapterCurrentLimit2 duration t2. T1 and T2 register accepts any
1 = Add 512mA of adapter current limit. command but only the valid register bits will be written. Refer to
<10> 0 = Add 0mA of adapter current limit. “Two-Level Adapter Current Limit” on page 36 for detailed
1 = Add 1024mA of adapter current limit. operation.
<11> 0 = Add 0mA of adapter current limit. TABLE 7. T1 AND T2 REGISTER 0x38H
BIT DESCRIPTION
1 = Add 4096mA of adapter current limit. <2:0> 000 = 10ms (default)
T1 001 = 20ms
<13:15> Not used 010 = 15ms
Maximum <12:4> = 10111110000 6080mA 011 = 5ms
100 = 1ms
101 = 0.5ms
TABLE 6. AdapterCurrentLimit1 REGISTER 0x3FH AND 110 = 0.1ms
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, 8mA 111 = 0ms
STEP, 10mΩ SENSE RESISTOR, x18) <7:3> Not used
BIT DESCRIPTION <10:8> 000 = 10µs (default)
T2 001 = 100µs
<1:0> Not used.
010 = 500µs
<2> 0 = Add 0mA of adapter current limit. 011 = 1ms
1 = Add 8mA of adapter current limit. 100 = 300µs
101 = 750µs
110 = 2ms
1 = Add 16mA of adapter current limit. 111 = 10ms
<4> 0 = Add 0mA of adapter current limit. <15:11> Not used



FN8877 Rev.3.00 Page 22 of 45

Sep 7, 2017
ISL9238
Setting Maximum Charging Voltage or Setting Minimum System Voltage

System Regulating Voltage To set the minimum system voltage, write a 16-bit
To set the maximum charging voltage or the system regulating MinSystemVoltage command (0x3EH or 0b00111110) using the
voltage, write a 16-bit MaxSystemVoltage command (0x15H or Write-word protocol shown in Figure 24 on page 19 and the data
0b00010101) using the Write-word protocol shown in Figure 24 on format as shown in Table 9.
page 19 and the data format as shown in Table 8. The minimum system voltage range is 256mV to 13.824V. The
The maximum system voltage range is 8mV to 18.304V. The MinSystemVoltage register accepts any voltage command but only
MaxSystemVoltage register accepts any voltage command but the valid register bits will be written to the register. The
only the valid register bits will be written to the register and the MinSystemVoltage register value should be set lower than the
maximum values is clamped at 18.304V. ISL9238 accepts a 0V MaxSystemVoltage register value and the maximum value is
command, but register value does not change. clamped at 13.824V.
The MaxSystemVoltage register sets the battery full charging The MinSystemVoltage register sets the battery voltage threshold
voltage limit. The MaxSystemVoltage register setting also is the for entry and exit of the Trickle Charging mode and for entry and
system bus voltage regulation point when battery is absent or exit of the Learn mode. The VBAT pin is used to sense the battery
battery is present but is not in Charging mode. See “System voltage to compare with the MinSystemVoltage register setting.
Voltage Regulation” on page 37 for details. Refer to “Trickle Charging” on page 37 and “Battery Learn Mode”
on page 36 for details.
The VSYS pin is used to sense the battery voltage for maximum
charging voltage regulation. The VSYS pin is also the system bus The MinSystemVoltage register setting also is the system voltage
voltage regulation sense point. regulation point when it is in Trickle Charging mode. The CSON
pin is the system voltage regulation sense point in Trickle
TABLE 8. MaxSystemVoltage REGISTER 0x15H (8mV STEP) Charging mode. Refer to “System Voltage Regulation” on
BIT DESCRIPTION page 37” for details.
<2:0> Not used TABLE 9. MinSystemVoltage REGISTER 0x3EH
<3> 0 = Add 0mV of charge voltage. BIT DESCRIPTION
1 = Add 8mV of charge voltage.
<7:0> Not used
<4> 0 = Add 0mV of charge voltage.
<15:14> Not used
<11> 0 = Add 0mV of charge voltage. Maximum 13824mV
Setting PROCHOT# Threshold for Adapter
1 = Add 4096mV of charge voltage. Overcurrent Condition
<13> 0 = Add 0mV of charge voltage. To set the PROCHOT# assertion threshold for adapter overcurrent
1 = Add 8192mV of charge voltage. condition, write a 16-bit ACProchot# command (0x47H or
<14> 0 = Add 0mV of charge voltage. 0b01000111) using the Write-word protocol shown in Table 24 on
1 = Add 16384mV of charge voltage. page 19 and the data format shown in Table 10 on page 24. By
<15> Not used
using the recommended current sense resistor values, the
register’s LSB always translates to 128mA of adapter current. The
Maximum 18304mV ACProchot# register accepts any current command but only the
valid register bits will be written to the register and the maximum
value is clamped at 6400mA for Rs1 = 20mΩ.
After POR, the ACProchot# register is reset to 0x0C00H. The
ACProchot# register can be read back to verify its content.
FN8877 Rev.3.00 Page 23 of 45

Sep 7, 2017
ISL9238
If the adapter current exceeds the ACProchot# register setting, TABLE 11. DCPROCHOT# REGISTER 0x48H (10mΩ SENSING
PROCHOT# signal will assert after the debounce time programmed RESISTOR, 256mA STEP, x18 GAIN)
by the Control2 register Bit<10:9> and latch on for a minimum time
BIT DESCRIPTION
programmed by Control2 register Bit<8:6>.
<7:0> Not used
TABLE 10. ACProchot# REGISTER 0x47H (20mΩ SENSING RESISTOR,
<8> 0 = Add 0mA of DCProchot# threshold.
128mA STEP, x18 GAIN)
1 = Add 256mA of DCProchot# threshold.
BIT DESCRIPTION
<9> 0 = Add 0mA of DCProchot# threshold.
<6:0> Not used 1 = Add 512mA of DCProchot# threshold.
<7> 0 = Add 0mA of ACProchot# threshold. <10> 0 = Add 0mA of DCProchot# threshold.
1 = Add 128mA of ACProchot# threshold. 1 = Add 1024mA of DCProchot# threshold.
<11> 0 = Add 0mA of ACProchot# threshold. <15:14> Not used.
1 = Add 2048mA of ACProchot# threshold.
Maximum <13:8> = 110010, 12800mA
<12> 0 = Add 0mA of ACProchot# threshold.
1 = Add 4096mA of ACProchot# threshold. Setting PROCHOT# Debounce Time and
<15:13> Not used Duration Time
Maximum <12:7> = 110010, 6400mA Control2 register Bit<10:9> configures the PROCHOT# signal
debounce time before its assertion for ACProchot# and
Setting PROCHOT# Threshold for Battery DCProchot#. The low system voltage Prochot# has a fixed
Over Discharging Current Condition debounce time of 10µs.
To set the PROCHOT# signal assertion threshold for battery over Control2 register Bit<8:6> configures the minimum duration of
discharging current condition, write a 16-bit DCProchot# Prochot# signal once asserted.
command (0x48H or 0b01001000) using the Write-word protocol
shown in Figure 24 on page 19 and the data format shown in Control Registers
Table 11. By using the recommended current sense resistor Control0, Control1, Control2, Control3, and Control4 registers
values, the register’s LSB always translates to 256mA of adapter configure the operation of the ISL9238. To change certain functions
current. The DCProchot# register accepts any current command or options after POR, write an 8-bit control command to Control0
but only the valid register bits will be written to the register and the register (0x39H or 0b00111001) or a 16-bit control command to
maximum values is clamped at 12.8A for Rs2 = 10mΩ. Control1 register (0x3CH or 0b00111100) or Control2 register
After POR, the DCProchot# register is reset to 0x1000H. The (0x3DH or 0b00111101) or Control3 register (0x4CH or
DCProchot# register can be read back to verify its content. 0b00111100) or Control4 register (0x4EH or 0b00111101) using
the Write-word protocol shown in Figure 24 on page 19 and the
If the battery discharging current exceeds the DCProchot# register data format shown in Tables 12, 13, 14, and 15 on page 16,
setting, the PROCHOT# signal will assert after the debounce time respectively.
programmed by the Control2 register Bit<10:9> and latch on for a
minimum time programmed by Control2 register Bit<8:6>.
In battery only and Low Power mode, the DCProchot# threshold
is set by Control0 register Bit<4:3>.
In battery only mode, DCProchot# function works only when
PSYS is enabled, since enabling PSYS will activate the internal
comparator reference. The Information register Bit<15>
indicates if the internal comparator reference is active or not.
When the adapter is present, the internal comparator reference
is always active.
FN8877 Rev.3.00 Page 24 of 45

Sep 7, 2017
ISL9238
TABLE 12. CONTROL0 REGISTER 0x39H
BIT BIT NAME DESCRIPTION
<15:13> Forward Buck and Bit<15:13> adjusts phase comparator threshold offset for forward buck and buck-boost
Buck-Boost Phase
Comparator Threshold Offset REV1 REV2
000 = 0mV 000 = 0mV
001 = 0.5mV 001 = 1mV
010 = 1mV 010 = 2mV
011 = 1.5mV 011 = 3mV
100 = -2mV 100 = -4mV
101 = -1.5mV 101 = -3mV
110 = -1mV 110 = -2mV
111 = -0.5mV 111 = -1mV
<12:10> Forward and Reverse Boost Bit<12:10> adjusts phase comparator threshold offset for forward and reverse boost
Phase Comparator Threshold 000 = 0mV
Offset 001 = 0.5mV
010 = 1mV
011 = 1.5mV
100 = -2mV
101 = -1.5mV
110 = -1mV
111 = -0.5mV
<9,8,0> Reverse Buck and Bit<9,8,0> adjusts phase comparator threshold offset for forward and reverse boost
Buck-Boost Phase
Comparator Threshold Offset REV1 REV2
000 = 0mV 000 = 0mV
001 = 0.5mV 001 = 1mV
010 = 1mV 010 = 2mV
011 = 1.5mV 011 = 3mV
100 = -2mV 100 = -4mV
101 = -1.5mV 101 = -3mV
110 = -1mV 110 = -2mV
111 = -0.5mV 111 = -1mV
<7> SMBus Timeout The ISL9238 includes a timer to insure the SMBus master is active and to prevent overcharging the battery.
If the adapter is present and if the ISL9238 does not receive a write to the MaxChargeVoltage or
ChargeCurrentLimit register within 175s, ISL9238 will terminate charging. If a timeout occurs, writing the
MaxChargeVoltage or ChargeCurrentLimit register will re-enable charging.
0 = Enable the SMBus timeout function.
1 = Disable the SMBus timeout function.
<6:5> High-Side FET Short Bit<6:5> configures the high-side FET short detection PHASE node voltage threshold during low-side FET
Detection Threshold turning on.
00 = 400mV (default)
01 = 500mV
10 = 600mV
11 = 800mV
FN8877 Rev.3.00 Page 25 of 45

Sep 7, 2017
ISL9238
TABLE 12. CONTROL0 REGISTER 0x39H (Continued)
<4:3> DCProchot# Threshold in Bit<4:3> only configures the battery discharging current DCProchot# threshold in battery only Low Power
Battery Only Low Power mode indicated by the Information1 register 0x3A Bit<15>. If PSYS is enabled, battery discharge current
Mode DCProchot# threshold is set by the DCProchot# register 0x48 setting.
Rs2 = 10mΩ Rs2 = 20mΩ Rs2 = 5mΩ

Bit<4:3> (A) (A) (A)
00 12 (Default) 6 24
01 10 5 20
10 8 4 16
11 6 3 12
<2> Input Voltage Regulation Bit<2> disables or enables the input voltage regulation loop.
Loop 0 = Enable (default)
1 = Disable
<1> Not used
TABLE 13. CONTROL1 REGISTER 0x3CH

<15:14> General Purpose Bit<15:14> configures the general purpose comparator assertion debounce time.
Comparator Assertion 00 = 2µs (default)
Debounce Time 01 = 12µs
10 = 2ms
11 = 5s
13 Exit Learn Mode Option Bit<13> provides the option to Exit Learn mode when battery voltage is lower than MinSystemVoltage
register setting.
0 = Stay in Learn mode even if VBAT < MinSystemVoltage register setting (default)
1 = Exit Learn mode if VBAT < MinSystemVoltage register setting
12 Learn Mode Bit<12> enables or disables the Battery Learn mode.

0 = Disable (default)
1 = Enable
To enter Learn mode, BATGONE pin needs to be low, i.e., battery must be present.
11 OTG Function Bit<11> enables or disables OTG function.

1 = Enable
10 Audio Filter Bit<10> enables or disables the audio filter function.

1 = Enable
<9:8> Switching Frequency Bit<9:8> configures the switching frequency and overrides the switching frequency set by PROG pin.
00 = Switching frequency set by PROG pin (default)
01 = 839kHz
10 = 723kHz
11 = 635kHz
To keep the switching frequency set by PROG pin resistor, leave Bit<9:8> as it is or write code 00, which sets
the same frequency as the PROG pin resistor does.
7 Not used, When writing, write 0
6 Turbo Bit<6> enables or disables Turbo mode. When the turbo function is enabled, BGATE FET turns on in Turbo
mode. Refer to Table 24 on page 36 for BGATE ON/OFF truth table.
0 = Enable (default)
1 = Disable
5 AMON/BMON Function Bit<5> enables or disables the current monitor function AMON and BMON.
0 = Enable AMON/BMON (default)
1 = Disable AMON/BMON
Bit<5> is only valid in battery only mode. When adapter is present, AMON/BMON is automatically enabled
and Bit<5> becomes invalid.
FN8877 Rev.3.00 Page 26 of 45

Sep 7, 2017
ISL9238
TABLE 13. CONTROL1 REGISTER 0x3CH (Continued)
4 AMON or BMON Bit<4> selects AMON or BMON as the output of AMON/BMON pin.
0 = AMON (default)
1 = BMON
3 PSYS Bit<3> enables or disable system power monitor PSYS function.

1 = Enable
2 VSYS Bit<2> enables or disables the buck-boost charger switching VSYS output. When disabled, ISL9238 stops
switching and forces BGATE FET on.
0 = Enable (default)
1 = Disable
<1:0> Low_VSYS_Prochot# Bit<1:0> configures the Low_VSYS_Prochot# assertion threshold.

Reference 00 = 6.0V (default)
01 = 6.3V
10 = 6.6V
11 = 6.9V
For 1-cell configuration, the Low_VSYS_Prochot# assertion threshold is fixed 2.4V.
TABLE 14. CONTROL2 REGISTER 0x3DH

<15:14> Trickle Charging Current Bit<15:14> configures the charging current in Trickle Charging mode.
00 = 256mA (default)
01 = 128mA
10 = 64mA
11 = 512mA
13 OTG Function Enable Bit<13> configures the OTG function debounce time from when the ISL9238 receives the OTG enable
Debounce Time command.
0 = 1.3s (default)
1 = 150ms
12 Two-Level Adapter Current Bit<12> enables or disables the two-level adapter current limit function.
Limit Function 0 = Disable (default)
1 = Enable
11 Adapter Insertion to Bit<11> configures the debounce time from adapter insertion to ACOK asserted high.
Switching Debounce 0 = 1.3s (default)
1 = 150ms
After VDD POR, for the first time adapter plugged in, the ASGATE turn-on delay is always 150ms, regardless
of the Bit<11> setting. This bit only sets the ASGATE turn-on delay after ASGATE turns off at least one-time
when VDD is above it POR value and Bit<11> default is 0 for 1.3s.
<10:9> Prochot# Debounce Bit<10:9> configures the Prochot# debounce time before its assertion for ACProchot# and DCProchot#.
00: 7µs (default)
01: 100µs
10: 500µs
11: 1ms
The Low_VSYS_Prochot# has fixed 10µs debounce time.
<8:6> Prochot# Duration Bit<8:6> configures the minimum duration of Prochot# signal once asserted.
000 = 10ms (default)
001 = 20ms
010 = 15ms
011 = 5ms
100 = 1ms
101 = 500µs
110 = 100µs
111 = 0s
5 ASGATE in OTG Mode Bit<5> turns on or off the ASGATE FET in OTG mode.
0 = Turn ON ASGATE in OTG mode (default)
1 = Turn OFF ASGATE in OTG mode
FN8877 Rev.3.00 Page 27 of 45

Sep 7, 2017
ISL9238
TABLE 14. CONTROL2 REGISTER 0x3DH (Continued)

4 CMIN Reference Bit<4> configures the general purpose comparator reference voltage.
0 = 1.2V (default)
1 = 2V
3 General Purpose Bit<3> enables or disabled the general purpose comparator.

Comparator 0 = Enable (default)
1 = Disable
2 CMOUT Polarity Bit<2> configures the general purpose comparator output polarity once asserted. The comparator reference
voltage is connected at the inverting input node.
0 = CMOUT is High when CMIN is higher than reference (default)
1 = CMOUT is Low when CMIN is higher than reference
1 WOCP Function Bit<1> enables or disables the WOC (Way Overcurrent) fault protection function.
0 = Enable WOCP (default)
1 = Disable WOCP
0 Battery OVP Function Bit<0> enables or disables the Battery OV (Overvoltage) fault protection function.
0 = Disable Battery OVP (default)
1 = Enable Battery OVP
TABLE 15. CONTROL3 REGISTER 0x4CH
15 Reread PROG Pin Resistor Bit<15> reread PROG pin resistor or not.
0 = Reread PROG pin resistor
1 = Do not reread PROG pin resistor
14 Reload ACLIM When Bit<14> reload AdapterCurrentLimit1 register set by PROG pin resistor.
Adapter Is Plugged In 0 = Reload AdapterCurrentLimit1 register
1 = Do not reload
13 Autonomous Charging Bit<13> configures autonomous charging termination time.

Termination Time 0 = 20ms
1 = 200ms
<12:11> Charger Timeout Bit<12:11> configures SMBus charger timeout time.

00 = 175s (default)
01 = 87.5s
10 = 43.75s
11 = 5s
10 BGATE OFF Bit<10> enables or disables Battery Ship mode.
0 = Idle
1 = Force BGATE MOSFET OFF (enable Battery Ship mode)
9 PSYS Gain Bit<9> configures the system power monitor PSYS output gain.
0 = 1.44µA/W (default)
1 = 0.723µA/W
8 Exit IDM Timer Bit<8> configures Ideal Diode mode exit timer when battery discharge current is less than 300mA.
0 = 40ms (default)
1 = 80ms
7 Autonomous Charging Bit<7> enables Autonomous Charging mode.
Mode 0 = Enable Autonomous Charging mode
1 = Battery charging current control through SMBus
6 AC and CC Feedback Gain Bit<6> configures AC and CC feedback gain for high current.
0 = Idle
1 = x0.5
5 Input Current Limit Loop Bit<5> disables input current limit loop.
0 = Enable input current limit loop
1 = Disable input current limit loop
4 Input Current Limit Loop Bit<4> disables input current limit loop when BATGONE = 1.
when BATGONE = 1 0 = Enable ACLIM when BATGONE = 1
1 = Disable ACLIM when BATGONE = 1
FN8877 Rev.3.00 Page 28 of 45

Sep 7, 2017
ISL9238
TABLE 15. CONTROL3 REGISTER 0x4CH (Continued)
3 AMON/BMON Direction Bit<3> configures AMON/BMON direction.

0 = Adapter current monitor/battery charging current monitor
1 = OTG output current monitor/battery discharging current monitor
2 Digital Reset Bit<2> reset all SMBus register value to POR default value.
0 = Idle
1 = Reset
1 Buck-Boost Switching Bit<1> configures switching period in Buck-Boost mode

Period 0 = x1
1 = x2 (half switching frequency)
0 OTG Start-Up Delay Bit<0> shorts OTG start-up time

0 = Idle
1 = Short OTG start-up time from 150ms to 1ms when Control2 register Bit<13> = 1 for 150ms
TABLE 16. CONTROL4 REGISTER 0x4EH

<15:8> Not used
7 OTGCURRENT PROCHOT# Bit<6> enables or disables trigger PROCHOT# with OTGCURRENT
0 = Disable
1 = Enable
6 BATGONE PROCHOT# Bit<6> enables or disables trigger PROCHOT# with BATGONE
0 = Disable
1 = Enable
5 ACOK PROCHOT# Bit<6> enables or disables trigger PROCHOT# with ACOK
0 = Disable
1 = Enable
4 Comparator PROCHOT# Bit<6> enables or disables trigger PROCHOT# with General Purpose Comparator rising.
0 = Disable
1 = Enable
<3:2> ACOK falling or BATGONE Bit<3:2> configures debounce time from ACOK falling or BATGONE rising to PROCHOT# trip.
Rising Debounce 00 = 2µs
01 = 25µs
10 = 125µs
11 = 250µs
1 PROCHOT# Clear Bit<1> clear PROCHOT#.
0 = Idle
1 = Clear PROCHOT#
0 PROCHOT# Latch Bit<0> manually reset PROCHOT#.
0 = PROCHOT# signal auto-clear
1 = Hold PROCHOT# low once tripped
FN8877 Rev.3.00 Page 29 of 45

Sep 7, 2017
ISL9238
OTG Voltage Register

.
TABLE 18. OTGCURRENT 0x4AH

The OTG voltage register contains SMBus readable and writable BIT DESCRIPTION
OTG mode output regulation voltage reference. The default is <6:0> Not used
5.004V. This register accepts any voltage command but only the
<7> 0 = Add 0mA of OTG current
valid register bits will be written to the register and the maximum 1 = Add 128mA of OTG current
value is clamped at 27.456V.
<8> 0 = Add 0mA of OTG current
1 = Add 256mA of OTG current
TABLE 17. OTGVOLTAGE REGISTER 0x49H
<9> 0 = Add 0mV of OTG current
BIT DESCRIPTION 1 = Add 512mA of OTG current
<2:0> Not used <10> 0 = Add 0mV of OTG current

1 = Add 1024mA of OTG current
<3> 0 = Add 0mV of OTG voltage
<11> 0 = Add 0mV of OTG current
1 = Add 12mV of OTG voltage 1 = Add 2048mA of OTG current
<4> 0 = Add 0mV of OTG voltage <12> 0 = Add 0mV of OTG current
1 = Add 24mV of OTG voltage 1 = Add 4096mA of OTG current
<5> 0 = Add 0mV of OTG voltage <15:13> Not used
1 = Add 48mV of OTG voltage
Maximum 4096mA
1 = Add 96mV of OTG voltage Input Voltage Register
<7> 0 = Add 0mV of OTG voltage The input voltage register contains SMBus readable and writable
1 = Add 192mV of OTG voltage input voltage limit. The default is 4.096V. This register accepts
any current command but only the valid register bits will be written
1 = Add 384mV of OTG voltage to the register and the maximum values is clamped at 18.432V.
<9> 0 = Add 0mV of OTG voltage TABLE 19. INPUT VOLTAGE REGISTER 0x4BH
BIT DESCRIPTION
<10> 0 = Add 0mV of OTG voltage <7:0> Not used
<8> 0 = Add 0mV of Input voltage
1 = Add 341.3mV of Input voltage
<9> 0 = Add 0mA of Input voltage
<13> 0 = Add 0mV of OTG voltage 1 = Add 1365.3mV of Input voltage
<15> Not used
Maximum 27456mV
OTG Current Register
<15:14> Not used
The OTG current register contains SMBus readable and writable
OTG current limit. The default is 512mA. This register accepts any Maximum 18432mV
current command but only the valid register bits will be written to
the register and the maximum values is clamped at 4096mA for
Rs1 = 20mΩ.
FN8877 Rev.3.00 Page 30 of 45

Sep 7, 2017
ISL9238
Information Register TABLE 21. INFORMATION2 REGISTER 0x4DH

The information register contains SMBus readable information BIT DESCRIPTION
about manufacturing and Operating modes. Table 21 identifies <4:0> Program Resister read out
the bit locations of the information available. # of battery cell
Switching Frequency
TABLE 20. INFORMATION1 REGISTER 0x3AH Adapter current Limit
BIT DESCRIPTION <7:5> Bit<7:5> indicates the ISL9238 is in operation mode.
001 = Boost Mode
<3:0> Not used
010 = Buck Mode
<4> Bit<4> indicates if the Trickle Charging mode is active 011 = Buck-Boost Mode
or not. 101 = OTG Boost Mode
0 = Trickle Charging mode is not active 110 = OTG Buck Mode
1 = Trickle Charging mode is active 111 = OTG Buck-Boost Mode
<9:5> Not used <11:8> Bit<11:8> indicates the ISL9238 state machine status
0000 = OFF
<10> Bit<10> indicates if the Low_VSYS_Prochot# is 0001 = BATTERY
tripped or not. 0010 = ADAPTER
0 = Low_VSYS Prochot# is not tripped 0011 = ACOK
1 = Low_VSYS Prochot# is tripped 0100 = VSYS
0101 = CHARGE
<11> Bit<11> indicates if DCProchot# is tripped or not.
0 = DCProchot# is not tripped 0110 = ENOTG
0111 = OTG
1 = DCProchot# is tripped
1000 = ENLDO5
<12> Bit<12> indicates if 1001 = Not Applicable
ACProchot#/OTGCURRENTProchot# is tripped or not. 1010 = TRIM/ENCHREF
0 = ACProchot#/OTGCURRENTProchot# is not tripped 1011 = ACHRG
1 = ACProchot#/OTGCURRENTProchot# is tripped 1100 = CAL
1101 = AGON/AGONTG
<14:13> Bit<14:13> indicates the active control loop. 1110 = WAIT/PSYS
00 = MaxSystemVoltage control loop is active
1111 = ADPPSYS
01 = Charging current loop is active
10 = Adapter current limit loop is active <12> Bit<10> indicates BATGONE pin status
11 = Input voltage loop is active 0 = Battery is present
1 = No battery
<15> Bit<15> indicates if the internal reference circuit is
<13> Bit<11> indicates if the general purpose comparator
active or not. Bit<15> = 0 indicates that ISL9238 is in
Low Power mode. output after debounce time
0 = Comparator output is low
0 = Reference is not active
1 = Comparator output is high
1 = Reference is active
<14> Bit<12> indicates the ACOK pin status
0 = No adapter
1 = Adapter is present
<15> Not used
FN8877 Rev.3.00 Page 31 of 45

Sep 7, 2017
ISL9238
Application Information CCM/DCM BOUNDARY

VW
R3 Modulator V CR
COMP +
CCM
-
VCR S IL
Q PWM
R L
VO LIGHT DCM
+ VW
PHASE V CR
VW - IL CO
+
GM
-
CR
IL
DEEP DCM
VW
FIGURE 25. R3 MODULATOR
V CR
PWM IL
VW FIGURE 29. PERIOD STRETCHING

The ISL9238 uses Intersil patented R3 (Robust Ripple Regulator)
HYSTERETIC
VCR WINDOW
modulation scheme. The R3 modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 25 conceptually
COMP
shows the R3 modulator circuit and Figure 26 shows the
FIGURE 26. R3 MODULATOR OPERATION PRINCIPLES IN STEADY operation principles in steady state.
STATE
There is a fixed voltage window between VW and COMP. This
voltage window is called the VW window in the following
discussion. The modulator charges the ripple capacitor CR with a
PWM
current source equal to gm(VIN-VO) during PWM on-time and
discharges the ripple capacitor CR with a current source equal to
gmVO, during PWM off-time, where gm is a gain factor. The Cr
VW
voltage VCR therefore emulates the inductor current waveform.
The modulator turns off the PWM pulse when VCR reaches VW
and turns on the PWM pulse when it reaches COMP.
COMP
Since the modulator works with Vcr, which is large amplitude and
VCR noise free synthesized signal, it achieves lower phase jitter than
conventional hysteretic mode modulator.
Figure 27 shows the operation principles during dynamic
FIGURE 27. R3 MODULATOR OPERATION PRINCIPLES IN DYNAMIC response. The COMP voltage rises during dynamic response,
RESPONSE turning on PWM pulses earlier and more frequently temporarily,
which allows for higher control loop bandwidth than conventional
fixed frequency PWM modulator at the same steady state
switching frequency.
PHASE The R3 modulator can operate in Diode Emulation (DE) mode to
increase light-load efficiency. In DE mode the low-side MOSFET
conducts when the current is flowing from source-to-drain and
UGATE
does not allow reverse current, emulating a diode. As shown in
Figure 28, when LGATE is on, the low-side MOSFET carries
LG ATE current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. The IC monitors the
current by monitoring the phase node voltage. It turns off LGATE
IL when the phase node voltage reaches zero to prevent the
inductor current from reversing the direction and creating
FIGURE 28. DIODE EMULATION unnecessary power loss.
FN8877 Rev.3.00 Page 32 of 45

Sep 7, 2017
ISL9238
If the load current is light enough, as Figure 28 on page 32 shows, TABLE 22. OPERATION MODE
the inductor current will reach and stay at zero before the next
MODE Q1 Q2 Q3 Q4
phase node pulse and the regulator is in Discontinuous
Conduction Mode (DCM). If the load current is heavy enough, the Buck Control FET Sync. FET OFF ON
inductor current will never reach 0A and the regulator is in CCM Boost ON OFF Control FET Sync. FET
although the controller is in DE mode.
Buck-Boost Control FET Sync. FET Control FET Sync. FET
Figure 29 on page 32 shows the operation principle in Diode
OTG Buck ON OFF Sync. FET Control FET
Emulation mode at light load. The load gets incrementally lighter
in the three cases from top to bottom. The PWM on-time is OTG Boost Sync. FET Control FET OFF ON
determined by the VW window size, therefore is the same, OTG Buck-Boost Sync. FET Control FET Sync. FET Control FET
making the inductor current triangle the same in the three cases.
The R3 modulator clamps the ripple capacitor voltage VCR in DE
mode to make it mimic the inductor current. It takes the COMP
RS1
voltage longer to hit VCR, naturally stretching the switching VADP VSYS
CSOP
period. The inductor current triangles move further apart from CSIP CSIN Q4 SYSTEM
Q1 RS2
each other, such that the inductor current average value is equal LOAD
L1
to the load current. The reduced switching frequency helps CSON
BGATE
increase light-load efficiency. FET
Q2 Q3
VBAT
ISL9238 Buck-Boost Charger with USB OTG BATTERY
The ISL9238 buck-boost charger drives an external N-channel
MOSFET bridge comprised of two transistor pairs as shown in
FIGURE 30. BUCK-BOOST CHARGER TOPOLOGY
Figure 30. The first pair, Q1 and Q2, is a buck arrangement with
the transistor center tap connected to an inductor “input” as is
the case with a buck converter. The second transistor pair, Q3 The ISL9238 optimizes the Operation mode transition algorithm
and Q4, is a boost arrangement with the transistor center tap by considering the input and output voltage ratio and the load
connected to the same inductor’s “output” as is the case with a condition. When adapter voltage VADP is rising and is higher than
boost converter. This arrangement supports bucking from a 94% of the system bus voltage VSYS, the ISL9238 will transit
voltage input higher than the battery and also boosting from a from Boost mode to Buck-Boost mode; if VADP is higher than
voltage input lower than the battery. 120% of VSYS, the ISL9238 will forcedly transit from Buck-Boost
mode to Buck mode at any circumstance. At heavier load, the
In Buck mode, Q1 and Q2 turn on and off alternatively, while Q3 mode transition point changes accordingly to accommodate the
remains off and Q4 remains on. duty cycle change due to the power loss on the charger circuit.
In Boost mode, Q3 and Q4 turn on and off alternatively, while Q1 When the adapter voltage VADP is falling and is lower than 106%
remains on and Q2 remains off. the system bus voltage VSYS, ISL9238 will transit from Buck
In Buck-Boost mode, Q1 and Q3 turn on at the same time, Q3 mode to Buck-Boost mode; if VADP is lower than 80% of VSYS,
turns off and Q4 turns on, Q1 turns off and Q2 turns on and after ISL9238 will transit from Buck-Boost mode to Boost mode.
Q2 and Q4 turn off at the same time and Q1 and Q3 turn on
again. VADP
BUCK BUCK
In OTG Buck mode, Q3 and Q4 turn on and off alternatively, while

Q2 remains off and Q1 remains on. 120%
B U C K -B O O S T
In OTG Boost mode, Q1 and Q2 turn on and off alternatively,
while Q4 remains on and Q3 remains off.
106%
B U C K -B O O S T
In OTG Buck-Boost mode, Q4 and Q2 turn on at the same time, VSYS
Q2 turns off and Q1 turns on, Q4 turns off and Q3 turns on and 94%
BOOST
after Q3 and Q1 turn off at the same time and Q4 and Q2 turn on
again. 80%
BOOST
In OTG mode the output sensing point is the CSIP pin.
VADP
FIGURE 31. OPERATION MODE
FN8877 Rev.3.00 Page 33 of 45

Sep 7, 2017
ISL9238
When the OTG function is enabled with SMBus command and default switching frequency, the default AdapterCurrentLimit1
OTGEN pin, and if battery voltage VBAT is higher than 5.2V, register value and autonomous charging function.
ISL9238 operates in the OTG mode, there is one digital bit to AdapterCurrentLimit2 register default value is 1.5A. Table 23
control ASGATE. OTG mode is not available for 1-cell battery shows the programming options.
systems.
TABLE 23. PROG PIN PROGRAMMING OPTIONS
The ISL9238 connects the system voltage rail to either the
PROG-GND
output of the buck-boost switcher or the battery. In Turbo event, RESISTANCE (kΩ)
the ISL9238 will turn on the BGATE FET to discharge the battery DEFAULT DEFAULT
so the battery works with the adapter together to supply the TYP SWITCHING AUTONOMOUS ACLimit1
system power. MIN 1% MAX CELL # FREQUENCY CHARGING Reg(A)
0 1 733kHz No 0.476
Soft-Start
8.3 8.45 8.6 733kHz No 1.5
The ISL9238 includes a low power LDO with nominal 5V output,
which input is OR-ed from VBAT and ADP pins. The ISL9238 also 14.5 14.7 14.9 1MHz No 1.5
includes a high power LDO with nominal 5V output, which input is 20.7 21.0 21.3 1MHz No 0.476
from DCIN pin connected to the adapter and the system bus
through an external OR-ing diode circuit. Both LDO outputs are tied 27.7 28.0 28.3 733kHz Yes 0.476
to the VDD pin to provide the bias power and gate drive power for 35.3 35.7 36.1 733kHz Yes 1.5
the ISL9238. VDDP pin is the ISL9238 gate drive power supply
input. Use an R-C filter to generate the VDDP pin voltage from the 42.7 43.2 43.7 2 733kHz Yes 1.5
VDD pin voltage. 51.7 52.3 52.9 733kHz Yes 0.476
When VDD >2.7V, the ISL9238 digital block is activated and the 61.2 61.9 62.6 1MHz No 0.476
SMBus register is ready to communicate with the master
70.6 71.5 72.4 1MHz No 1.5
controller.
81.5 82.5 83.5 733kHz No 1.5
When VADP >3.2V, after 1.3s or 150ms debounce time set by
Control2 register Bit<11> (after VDD POR, for the first time 92.0 93.1 94.2 733kHz No 0.476
adapter plugged in, the ASGATE turn on delay is always 150ms), 104 105 106 3 733kHz No 0.476
ASGATE starts turning on with 10µA sink current. During the 1.3s
or 150ms debounce time, ISL9238 uses Intersil’s patented 116 118 120 733kHz No 1.5
technique to check if the input bus is short or not; if CSIP <2V or 131 133 135 1MHz No 1.5
ACIN <0.8V, ASGATE will not turn on. The soft-start scheme will
carefully bias up the input capacitors and protect the back-to-back 145 147 149 1MHz No 0.476
ASGATE FETs against potential damage caused by the inrush 160 162 164 733kHz Yes 0.476
current.
176 178 180 733kHz Yes 1.5
Use a voltage divider from the adapter voltage to set the ACIN pin
194 196 198 4 733kHz Yes 1.5
voltage. The ISL9238 monitors the ACIN pin voltage to determine
the presence of the adapter. Once VDD >3.8V, the ACIN pin voltage 212 215 218 733kHz Yes 0.476
exceeds 0.8V and ASGATE is fully turned on, the ISL9238 will allow 234 237 240 1MHz No 0.476
the external circuit to pull up the ACOK pin. Once ACOK is asserted,
ISL9238 will start switching. 258 261 264 1MHz No 1.5
The ACOK is an open-drain output pin indicating the presence of 284 287 290 733kHz No 1.5
the adapter and readiness of the adapter to supply power to the 312 316 320 733kHz No 0.476
system bus. The ISL9238 actively pulls ACOK low in the absence of
the adapter. 344 348 352 1 733kHz No 0.476
Before ASGATE turns ON, the ISL9238 will source 10µA of current
The ISL9238 will use the default number of cells in series as
out of the PROG pin and read the pin voltage to determine the
Table 23 shows and set the default MaxSystemVoltage register
PROG resistor value. The PROG resistor programs the
value and default MinSystemVoltage register value accordingly.
configurations of the ISL9238.
The switching frequency can be changed through SMBus
In Battery Only mode, the ISL9238 enters Low Power mode if
Control1 register Bit<9:8> after POR. Refer to SMBus Control1
only battery is present. VDD is 5V from the low power LDO to
register programming table on page 26 for detailed description.
minimize the power consumption. VDD becomes 5V once it exits
the Low Power mode such as when PSYS is enabled. Before ASGATE turns on, ISL9238 will source 10µA current out of
the PROG pin and read the PROG pin voltage to determine the
Programming Charger Option resistor value. However, application environmental noise may
The resistor from the PROG pin to GND programs the configuration pollute the PROG pin voltage and cause incorrect reading. If noise
of the ISL9238 for the default number of battery cells in series, the is a concern, it is recommended to connect a capacitor from the
PROG pin to GND to provide filtering. The resistor and the capacitor
FN8877 Rev.3.00 Page 34 of 45

Sep 7, 2017
ISL9238
RC time constant should be less than 40µs so the PROG pin Battery Ship Mode
voltage can rise to steady state before the ISL9238 reads it.
ISL9238 supports Battery Ship mode. When Control3 register Bit
If ISL9238 is powered up from the battery, it will not read PROG <10> is 1, BGATE MOSFET stays off for Battery Ship mode.
resistor unless PSYS is enabled through SMBus Control1 register
Bit<3>. In Battery Only mode, whenever PSYS is enabled, the DE Operation
ISL9238 will read PROG pin resistor and reset the configuration In DE mode of operation, the ISL9238 employs a phase
to the default. comparator to monitor the PHASE node voltage during the
Whenever the adapter is plugged in, ISL9238 will reset the low-side switching FET on-time in order to detect the inductor
AdapterCurrentLimit1 register to the default by reading the current zero crossing. The phase comparator needs a minimum
PROG pin resistor if it is not read before or by loading the on-time of the low-side switching FET for it to recognize inductor
previous reading result. current zero crossing. If the low-side switching FET on-time is too
short for the phase comparator to successfully recognize the
If PSYS is not enabled, ISL9238 will reset MaxSystemVoltage inductor zero crossing, the ISL9238 may lose diode emulation
register and MinSystemVoltage register to their default values ability. To prevent such a scenario, the ISL9238 employs a
according to the PROG pin cell number setting. If PSYS is minimum low-side switching FET on-time. When the intended
enabled, ISL9238 will keep the values in these two registers. low-side switching FET on-time is shorter than the minimum
By default, the adapter current sensing resistor Rs1 is 20mΩ and value, the ISL9238 stretches the switching period in order to
battery current sensing resistor Rs2 is 10mΩ. Using this keep the low-side switching FET on-time at the minimum value,
Rs1 = 20mΩand Rs2 = 10mΩ option would result in 4mA/LSB which causes the CCM switching frequency to drop below the set
correlation in the SMBus current commands. point.
If Rs1 and Rs2 values are different from this Rs1 = 20mΩand Power Source Selection
Rs2 = 10mΩ option, the SMBus command needs to be scaled The ISL9238 automatically selects the adapter and/or the
accordingly to obtain the correct current. Smaller current sense battery as the source for system power.
resistor values reduce the power loss while larger current sense
resistor values give better accuracy. The BGATE pin drives a P-channel MOSFET gate that
connects/disconnects the battery from the system and the
If different current sensing resistors are used, the Rs1:Rs2 ratio switcher.
should be kept as 2:1, then PSYS output can be scaled
accordingly to reflect the total system power correctly. The ASGATE pin drives a pair of back-to-back common source
PFETs to connect/disconnect the adapter from the system and
The illustration in this datasheet is based on current sensing the battery.
resistors Rs1 = 20mΩ and Rs2 = 10mΩ unless specified
otherwise. Use of the ASGATE pin is optional.
When battery voltage VBAT is higher than 2.4V and the adapter
Autonomous Charging Mode
voltage VADP is less than 3.2V, ISL9238 operates in Battery Only
The ISL9238 supports Autonomous Charging mode. This mode mode. During Battery Only mode, the ISL9238 turns on the
can be enabled/disabled through programming charging option BGATE FET to connect the battery to the system. In Battery Only
resistor or SMBus Control3 register Bit<7>. When the mode, the ISL9238 consumes very low power, less than 20µA
Autonomous Charging mode is enabled, this mode can be also during this mode. The battery discharging current monitor BMON
disabled by writing SMBus ChargingCurrentLimit or can be turned on during this mode to monitor the battery
MaxSystemVoltage command. discharging current. If the battery voltage VBAT is higher than
The ISL9238 enters to the Autonomous Charging mode when the 5.2V, the system power monitor PSYS function also can be
battery voltage is lower than MaxSystemVoltage -200mV per cell for turned on during this mode to monitor system power.
1ms debounce time and BGATE MOSFET is on. In Battery Only mode, the USB OTG function can be enabled
In the Autonomous Charging mode, the ISL9238 starts to charge when the battery voltage VBAT is higher than 5.2V, see “USB OTG
the battery with 2A (with RS2 = 10mΩ), PROCHOT# pin (On the Go)” on page 38 for details.
(Autonomous Charging mode indication pin) is pulled down to When the adapter voltage VADP is more than 3.2V, ISL9238 turns
GND and 175s charging timeout timer is disabled. The ISL9238 on ASGATE. If VDD is higher than 3.8V, ISL9238 enters in the
exits from Autonomous Charging mode when the battery Forward Buck, Forward Boost, or Forward Buck-Boost mode
charging current is less than 200mA (with RS2 = 10mΩ) for depending upon the adapter and system voltage VSYS duty cycle
20ms or 200ms in CV loop. This autonomous charging ratio. The system bus voltage is regulated at the voltage set on
termination time can be set by Control3 register Bit<13>. The the MaxSystemVoltage register. If the charge current register is
ISL9238 re-enters Autonomous Charging mode when the battery programmed (non-zero), ISL9238 charges the battery either in
voltage is discharged below MaxSystemVoltage - 200mV per cell. Trickle Charging mode or Fast Charging mode, as long as
When ISL9238 stays in Autonomous Charging mode for 12hrs, BATGONE is low.
which means the battery charging current is higher than 200mA
and the battery can not be charged to MaxSystemVoltage for
12hrs, ISL9238 stops charging the battery and exits Autonomous
Charging mode.
FN8877 Rev.3.00 Page 35 of 45

Sep 7, 2017
ISL9238
Battery Learn Mode TABLE 24. BGATE ON/OFF TRUTH TABLE

The ISL9238 supports Battery Learn mode. The ISL9238 enters TURBO
Battery Learn mode when it receives the SMBus Control (CONTROL CHARGECURRENT
command. BIT) REGISTER BGATE ON/OFF
SYSTEM
This mode of operation is used when it is desired to supply the
SYSTEM LOAD NOT LOAD IN
system power from the battery even when the adapter is plugged
0 = ENABLE 0 = ZERO IN TURBO MODE TURBO MODE
in, such as calibration of the battery fuel gauge, hence the name 1 = DISABLE 1 = NONZERO RANGE RANGE
“Battery Learn mode”.
0 0 OFF ON
Upon entering Battery Learn mode the ISL9238 will turn on the
0 1 ON for fast charge; ON
BGATE FET.
Trickle charge is
In Battery Learn mode, the ISL9238 turns on BGATE, keeps enabled
ASGATE on but turns off the buck-boost switcher regardless of 1 0 OFF OFF
whether the adapter is present or not.
1 1 ON for fast charge; ON
There are three ways of exiting Battery Learn mode: Trickle charge is
enabled
1. Receive Battery Learn mode exit command through SMBus.
2. Battery voltage is less than MinSystemVoltage register setting Two-Level Adapter Current Limit
(according to Control1 register Bit<12> setting).
In a real system, Turbo event usually does not last very long. It is
3. BATGONE pin voltage goes from logic LOW to HIGH. often no longer than milliseconds, a time length during which the
In all these cases, the ISL9238 resumes switching immediately adapter can supply current higher than its DC rating. The
to supply power to the system bus from the adapter in order to ISL9238 employs a two-level adapter current limit in order to
prevent system voltage collapse. fully take advantage of adapter’s surge capability and minimize
the power drawn from the battery.
Turbo Mode Support Figure 32 shows the two SMBus programmable adapter current
Turbo mode refers to the scenario when the system draws more limit levels, AdapterCurrentLimit1 and AdapterCurrentLimit2, as
power than the adapter’s power rating. well as the durations t1 and t2. The two-level adapter current
If the adapter current reaches the AdapterCurrentLimit1 register limit function is initiated when the adapter current is less than
set value (or AdapterCurrentLimit2 register set value, if two-level 100mA lower than the AdapterCurrentLimit1 register setting and
adapter current limit function is enabled), or the adapter input it starts at AdapterCurrentLimit2 for t2 duration and then
voltage drops to the Input Voltage Regulation Reference set by changes to AdapterCurrentLimit1 for t1 duration before
Control0 register 0x39H Bit<2>, the ISL9238 will limit the input repeating the pattern. These parameters can set adapter current
power by regulating the adapter current at limit with an envelope that allows the adapter to temporarily
AdapterCurrentLimit1/2 register set value, or by regulating the output surge current without requiring the charger to enter Turbo
adapter voltage at the Input Voltage Regulation Reference point. mode. Such operation maximizes battery life.
In Turbo mode, the system bus voltage VSYS will drop AdapterCurrentLimit1 register value can be higher or lower than
automatically or the charging current will drop automatically to AdapterCurrentLimit2 value.
limit the adapter input power. If the VSYS pin voltage is 150mV The two-level adapter current limit function can be enabled and
lower than the VBAT pin voltage, BGATE FET will turn on, such disabled through SMBus Control2 register Bit<12>. When the
that the battery supplies the rest of the power required by the two-level adapter current limit function is disabled, only
system. AdapterCurrentLimit1 value is used as the adapter current limit
If the ISL9238 detects 150mA charging current or if the battery and AdapterCurrentLimit2 value is ignored.
discharging current is less than 200mA for longer than 40ms or
I
80ms, it will turn off BGATE to exit Turbo mode. Turbo mode exit t2 t1 t2 t1
timer can be configured through Control3 register 0x4C Bit<8>.
Refer to Table 24 for BGATE control logic. AdapterCurrentLimit2
AdapterCurrentLimit1
I_Adapter
I T
I_System
I_Battery
T
FIGURE 32. TWO-LEVEL ADAPTER CURRENT LIMIT
FN8877 Rev.3.00 Page 36 of 45

Sep 7, 2017
ISL9238
Current Monitor The PSYS function can be enabled or disabled through SMBus
Control1 register Bit<3> as shown in Table 13 on page 26.
The ISL9238 provides an adapter current monitor/OTG current
monitor or a battery charging current monitor/battery discharging In Battery Only mode, the PSYS function cannot work if the
current monitor through the AMON/BMON pin. The AMON output battery voltage is less than 5.2V.
voltage is 18x (CSIP-CSIN) and 18x (CSIN-CSIP) voltage and the
BMON output voltage is 18x (CSON-CSOP) and 36x (CSOP-CSON) Trickle Charging
voltage. The ISL9238 supports trickle charging to an overly discharged
AMON and BMON function can be enabled or disabled through battery. It can activate the trickle charging function when the
SMBus Control1 register Bit<5>, AMON or BMON can be selected battery voltage is lower than MinSystemVoltage setting. The
through SMBus Control1 register Bit<4> and AMON/BMON VBAT pin is the battery voltage sense point for Trickle Charge
direction can be configured through SMBus Control3 register mode.
Bit<3> as Table 13 on page 26 shows. To enable Trickle Charging, set ChargeCurrent register to a
non-zero value. To disable trickle charging, set ChargeCurrent
PSYS Monitor register to 0. Refer to Table 24 on page 36 for trickle charging
The ISL9238 PSYS pin provides a measure of the instantaneous control logic.
power consumption of the entire platform. The PSYS pin outputs a
The trickle charging current can be programmed to be 512mA,
current source described by Equation 1.
256mA, 128mA or 64mA through SMBus Control2 register
I PSYS = K PSYS   V ADP  I ADP + V BAT  I BAT  (EQ. 1) Bit<15:14> in Table 14 on page 27.
In Trickle Charging mode, the ISL9238 regulates the trickle
KPSYS is based on current sensing resistor Rs1 = 20mΩ and charging current through the buck-boost switcher. Another
Rs2 = 10mΩ. VADP is the adapter voltage in Volts, IADP is the independent control loop controls the BGATE FET such that the
adapter current in Amperes, VBAT is the battery voltage and IBAT system voltage is maintained at the voltage set in the
is the battery discharging current. When the battery is MinSystemVoltage register. The VSYS pin is the system voltage
discharging, IBAT is a positive value; when the battery is being sensing point in Trickle Charging mode.
charged, IBAT is a negative value. The battery voltage VBAT is
detected through CSON pin to maximize the power monitor Once the battery voltage is charged the MinSystemVoltage register
accuracy in NVDC configuration Trickle Charge mode. value, the ISL9238 enters Fast Charging mode by limiting the
charging current at the ChargeCurrentLimit register setting.
The Rs1 to Rs2 ratio must be 2:1 for a valid power calculation to
occur. If the resistance values are higher (or lower) than the System Voltage Regulation
suggested values mentioned previously, KPSYS will be
proportionally higher (or lower). As an example, if Rs1 = 10mΩ If the battery is absent, or if a battery is present but BGATE is
and Rs2 = 5mΩ, then the output current will be half that above turned off, the ISL9238 will regulate the system bus voltage at
for the same power. If the PSYS information is not needed then the MaxSystemVoltage register setting. The VSYS pin is used to
any Rs1:Rs2 ratio is acceptable. sense the system bus voltage.
The PSYS gain can be configured through SMBus Control3 Charger Timeout
register Bit<9>. The default PSYS gain is set to 1.44µA/W and The ISL9238 includes a timer to insure the SMBus master is active
0.723µA/W PSYS gain option is available. and to prevent overcharging the battery. The ISL9238 will
The PSYS information includes the power loss of the charger terminate charging by turning off BGATE FET if the charger has not
circuit and the actual power delivered to the system. Resistor received a write command to the MaxSystemVoltage or
RPSYS connected between the PSYS pin and GND converts the ChargeCurrent register within 175s (SMBus Control3 register
PSYS information from current to voltage. Bit<12:11> = 00). Charger timeout time can be configured
through SMBus Control3 register Bit<12:11>. When the charging
PSYS accuracy limits and a typical accuracy scan are shown in is terminated by the timeout, the ChargeCurrent register will retain
Figure 33. its value instead of resetting to zero. If a timeout occurs,
MaxSystemVoltage or ChargeCurrent register must be written to
re-enable charging.
The ISL9238 allows users to disable the charger timeout function
through SMBus Control0 register Bit<7> as Table 12 on page 25
shows.
FIGURE 33. PSYS ACCURACY AND LIMITS
FN8877 Rev.3.00 Page 37 of 45

Sep 7, 2017
ISL9238
USB OTG (On the Go) Once OV is detected, ISL9238 will stop switching and deassert
OTGPG. It will resume switching after 100µs once OTG voltage
When the OTG function is enabled with SMBus command and
drops below the OTG OV threshold.
OTGEN pin and if battery voltage VBAT is higher than 5.2V,
ISL9238 operates in the Reverse Buck, Reverse Boost, or BATGONE needs to be low to enable OTG mode. OTG mode is not
Reverse Buck-Boost mode. available for 1-cell battery systems.
Once ISL9238 receives the command to enable the OTG Stand-Alone Comparator
function, it will start switching after the 1.3s or 150ms debounce
time set by Control2 register Bit<13>. Once the OTG output The ISL9238 includes a general purpose stand-alone
voltage reaches to the OTG output voltage set by register 0x49 comparator. OTGEN/CMIN pin is the comparator input. The
Bit<14:3>, OTG power-good OTGPG will assert to High. Moreover, internal comparator reference is connected to the inverting input
Control2 register Bit<5> can be used to turn ASGATE FET off to of the comparator and can be configured as 1.2V or 2V through
cut off the OTG output. SMBus Control2 register Bit<4>. The comparator output is the
OTGPG/CMOUT pin and the output polarity when the comparator
Before OTG mode starts switching, the CSIP pin voltage needs to is tripped can be configured through SMBus register bit.
drop below the OTG output overvoltage protection threshold
(OTGVDAV + 100mV) first. When Control2 register Bit<2> = 0 for normal comparator output
polarity, if CMIN>Reference, CMOUT = High; if CMIN < Reference,
The default OTG output voltage is programmable up to 20V. The CMOUT = Low.
OTG Voltage register 0x49H can be used to configure the OTG
output voltage. When Control2 register Bit<2> = 1 for inversed comparator
output polarity, if CMIN > Reference, CMOUT = Low; if
The default OTG output current is limited at 512mA through Rs1. CMIN < Reference, CMOUT = High.
The OTGCurrent register 0x4AH can be used to adjust the OTG
output current limit. In Battery Only mode, the stand-alone comparator is disabled
unless PSYS is enabled through SMBus Control1 register Bit<3>
The ISL9238 includes the OTG output undervoltage and to enable the internal reference, which is indicated through
overvoltage protection functions. The UVP threshold is OTG Information1 register Bit<15>.
output voltage -1.2V and the OVP threshold is OTG output voltage
+1.2V. Table 25 shows the OTG mode and the stand-alone comparator
truth table.
Once UV is detected, ISL9238 will stop switching and turn off
ASGATE and deassert OTGPG after 32ms and after 1.3s or
150ms debounce time set by Control2 register Bit<13>, it will
resume switching.
TABLE 25. OTG AND COMPARATOR TRUTH TABLE
DESCRIPTION
Control1 Register Control2 PIN-2O PIN-26
0x3C Register 0x3D
Bit<11> Bit<3> OTGEN/CMIN OTGPG/CMOUT

OTG Function Comparator
Enable/Disable Enable/Disable
0 0 Comparator Comparator Output OTG function is disabled.

Input Pin CMIN Pin CMOUT Comparator is enabled.
0 1 X X Both OTG function and comparator are disabled.
1 0 Comparator Comparator Output Both OTG function and comparator are enabled.
Input Pin CMIN Pin CMOUT OTG function is enabled when VBAT > 5.2V and Control1 register
Bit<11> = 1 without OTG power-good pin indication. While the
Information1 register 0x3A Bit<6:5> = 11 indicates it is in OTG mode.
1 1 OTG Enable Input OTG Power-Good Comparator is disabled.
Pin OTGEN Indication Pin OTGPG OTG function is enabled when VBAT > 5.2V and ENOTG pin = High and
Control1 register Bit<11> = 1
FN8877 Rev.3.00 Page 38 of 45

Sep 7, 2017
ISL9238
Adapter Overvoltage Protection Over-Temperature Protection

If the ADP pin voltage exceeds 23.4V for more than 10µs, the The ISL9238 will stop switching for self protection when the
ISL9238 will consider an adapter overvoltage condition has junction temperature exceeds +140°C.
occurred. It will turn off the ASGATE MOSFETs to isolate the
Once the temperature falls below +120°C and after 100µs
adapter from the system, deassert the ACOK signal by pulling it
delay, the ISL9238 will start to switching.
low and stop switching. BGATE will turn on for the battery to
support the system load. Once ADP voltage drops below 23.04V
Switching Power MOSFET Gate Capacitance
from more than 100µs, it will start to turn on ASGATE and start
switching. The ISL9238 includes an internal 5V LDO output at VDD pin,
which can be used to provide the switching MOSFET gate driver
Battery Overvoltage Protection power through VDDP pin with an R-C filter. The 5V LDO output
overcurrent protection threshold is 100mA nominal. When
If the VBAT pin voltage is higher than battery overvoltage threshold
selecting the switching power MOSFET, the MOSFET gate
(Vbov) + MaxSystemVoltage for 1ms, it will declare the battery
capacitance should be considered carefully to avoid overloading
overvoltage and stop switching. Battery overvoltage threshold are
the 5V LDO, especially in Buck-Boost mode when four MOSFETs
4% of MaxSystemVoltage for 1-cell battery setting and 2% of
are switching at the same time. For one MOSFET, the gate drive
MaxSystemVoltage in 2-, 3- and 4-cells setting. It will resume
current can be estimated by Equation 2:
switching with 1ms debounce time when VBAT pin voltage drops
0.5xVbov + MaxSystemVoltage. The ISL9238 allows users to I driver = Q g  f (EQ. 2)
SW
disable the battery overvoltage protection function through
SMBus Control2 register Bit<0>. Where:
System Overvoltage Protection • Qg is the total gate charge, which can be found in the MOSFET
datasheet
The ISL9238 provides system rail overvoltage protection. If the
system voltage VSYS is 800mV higher than MaxSystemVoltage • fSW is switching frequency
register set value, it will declare the system overvoltage and stop
switching. It will resume switching without the 1.3s or 150ms Adapter Input Filter
debounce once VSYS drops 300mV below the system The adapter cable parasitic inductance and capacitance could
overvoltage threshold. cause some voltage ringing or an overshoot spike at the adapter
connector node when the adapter is hot plugged in. This voltage
Way Overcurrent Protection (WOCP) spike could damage the ASGATE MOSFET or the ISL9238 pins
In the case that the system bus is shorted, either a MOSFET short connecting to the adapter connector node. One low cost solution
or an inductor short, the input current could be high. The ISL9238 is to add an RC snubber circuit at the adapter connector node to
includes input overcurrent protection to turn off the ASGATE and clamp the voltage spike as shown in Figure 34. A practical value
stop switching. of the RC snubber is 2.2Ω to 2.2µF while the appropriate values
and power rating should be carefully characterized based on the
The ISL9238 provides adapter current and battery discharging actual design. Meanwhile it is not recommended to add a pure
current WOCP (Way Overcurrent Protection) function against the capacitor at the adapter connector node, which can cause an
MOSFET short, system bus short and inductor short scenarios. even bigger voltage spike due to the adapter cable or the adapter
The ISL9238 monitors the CSIP-CSIN voltage and CSON-CSOP current path parasitic inductance.
voltage, compares them with the WOCP threshold 12A for
adapter current and 20A for battery discharge current.
When the WOC comparator is tripped, ISL9238 counts one time ADAPTER
within each 10µs. Whenever ISL9238 counts WOC to 7 times in CONNECTOR
Ri
50ms, it turns off ASGATE, deasserts ACOK and stops switching 2 .2
immediately. After the 1.3s or 150ms debounce time set by ASGATE
Control2 register Bit<11>, it goes through the start-up sequence Ci A C IN
to retry. 2 .2µF
The WOCP function can be disabled through Control2 register

R C SN U B B ER IS L9 2 38
Bit<1>.
FIGURE 34. ADAPTER INPUT RC SNUBBER CIRCUIT
FN8877 Rev.3.00 Page 39 of 45

Sep 7, 2017
ISL9238
General Application Information Select the Input Capacitor

This design guide is intended to provide a high-level explanation of The important parameters for the input capacitance are the
the steps necessary to design a single-phase power converter. It is voltage rating and the RMS current rating. For reliable operation,
assumed that the reader is familiar with many of the basic skills select capacitors with voltage and current ratings above the
and techniques referenced in the following section. In addition to maximum input voltage and capable of supplying the RMS
this guide, Intersil provides complete reference designs that current required by the switching circuit. Their voltage rating
include schematics, bill of materials and example board layouts. should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Select the LC Output Filter Figure 35 is a graph of the input capacitor RMS ripple current,
The duty cycle of an ideal buck converter in CCM is a function of normalized relative to output load current, as a function of duty
the input and the output voltage. This relationship is written by cycle and is adjusted for converter efficiency. The normalized RMS
Equation 3: ripple current calculation is written as Equation 8:
V OUT 2
D = --------------- (EQ. 3) Dk
V IN I MAX  D   1 – D  + --------------
12
I C  RMS ,NORMALIZED  = ----------------------------------------------------------------------
-
IN I MAX (EQ. 8)
The output inductor peak-to-peak ripple current is written by
Equation 4: Where:
V OUT   1 – D 
I P-P = -------------------------------------- (EQ. 4) • IMAX is the maximum continuous ILOAD of the converter
f SW  L
• k is a multiplier (0 to 1) corresponding to the inductor
peak-to peak ripple amplitude expressed as a ratio of IMAX
A typical step-down DC/DC converter will have an IP-P of 20% to
(0 to 1)
40% of the maximum DC output load current for a practical
design. The value of IP-P is selected based upon several criteria • D is the duty cycle that is adjusted to take into account the
such as MOSFET switching loss, inductor core loss and the efficiency of the converter, which is written as Equation 9:
resistive loss of the inductor winding. V OUT
D = --------------------------
The DC copper loss of the inductor can be estimated by V IN  EFF (EQ. 9)
Equation 5:
2 In addition to the capacitance, some low ESL ceramic
P COPPER = I LOAD  DCR (EQ. 5) capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given to the 0.60
NORMALIZED INPUT RMS RIPPLE CURRENT
DCR selection. Another factor to consider when choosing the

inductor is its saturation characteristics at elevated temperatures. A
0.48 k = 0.25
saturated inductor could cause destruction of circuit components.
A DC/DC buck regulator must have output capacitance CO into k = 0.5
k=0
which ripple current IP-P can flow. Current IP-P develops a 0.36
corresponding ripple voltage VP-P across CO, which is the sum of k=1
the voltage drop across the capacitor ESR and of the voltage k = 0.75
0.24
change stemming from charge moved in and out of the
VS = ±2.5V
capacitor. These two voltages are written by Equations 6 and 7:
V ESR = I P-P  E SR (EQ. 6) 0.12
I P-P 0
V C = ----------------------------- (EQ. 7) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
8  CO  f
SW
DUTY CYCLE
If the output of the converter has to support a load with high FIGURE 35. NORMALIZED RMS INPUT CURRENT AT EFF = 1
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the load
transient has an extremely high slew rate. Low inductance
capacitors should be considered in this scenario. A capacitor
dissipates heat as a function of RMS current and frequency. Be sure
that IP-P is shared by a sufficient quantity of paralleled capacitors so
that they operate below the maximum rated RMS current at fSW.
Take into account that the rated value of a capacitor can fade as
much as 50% as the DC voltage across it increases.
FN8877 Rev.3.00 Page 40 of 45

Sep 7, 2017
ISL9238
Select the Switching Power MOSFET Select the Bootstrap Capacitor

Typically, a MOSFET cannot tolerate even brief excursions beyond The selection of the bootstrap capacitor is written by
their maximum drain-to-source voltage rating. The MOSFETs used Equation 13:
in the power stage of the converter should have a maximum VDS Qg
rating that exceeds the sum of the upper voltage tolerance of the C BOOT = ------------------------ (EQ. 13)
V BOOT
input power source and the voltage spike that occurs when the
MOSFET switches off. Where:
There are several power MOSFETs readily available that are • Qg is the total gate charge required to turn on the high-side
optimized for DC/DC converter applications. The preferred MOSFET
high-side MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear • VBOOT, is the maximum allowed voltage decay across the
region. Unlike the low-side MOSFET, which has the drain-to-source boot capacitor each time the high-side MOSFET is switched on.
voltage clamped by its body diode during turn off, the high-side As an example, suppose the high-side MOSFET has a total gate
MOSFET turns off with a VDS of approximately VIN - VOUT, plus the charge Qg, of 25nC at VGS = 5V and a VBOOT of 200mV. The
spike across it. The preferred low-side MOSFET emphasizes low calculated bootstrap capacitance is 0.125µF; for a comfortable
rDS(ON) when fully saturated to minimize conduction loss. It should margin, select a capacitor that is double the calculated
be noted that this is an optimal configuration of MOSFET selection capacitance. In this example, 0.22µF will suffice. Use an X7R or
for low duty cycle applications (D < 50%). For higher output, low X5R ceramic capacitor.
input voltage solutions, a more balanced MOSFET selection for
high- and low-side devices may be warranted.
For the Low-Side (LS) MOSFET, the power loss can be assumed to
be conductive only and is written as Equation 10:
2
P CON_LS  I LOAD  r DS  ON _LS   1 – D  (EQ. 10)
For the High-Side (HS) MOSFET, the conduction loss is written by

Equation 11:
2
P CON_HS = I LOAD  r DS  ON _HS  D (EQ. 11)
For the High-Side MOSFET, the switching loss is written as

Equation 12:
V IN  I VALLEY  t SWON  f V IN  I PEAK  t SWOFF  f

SW SW
P SW_HS = -------------------------------------------------------------------------- + -----------------------------------------------------------------------
2 2
(EQ. 12)
Where:
• IVALLEY is the difference of the DC component of the inductor
current minus 1/2 of the inductor ripple current
• IPEAK is the sum of the DC component of the inductor current
plus 1/2 of the inductor ripple current
• tSW(ON) is the time required to drive the device into saturation
• tSW(OFF) is the time required to drive the device into cut-off
FN8877 Rev.3.00 Page 41 of 45

Sep 7, 2017
ISL9238
Layout
PIN NUMBER PIN NAME LAYOUT GUIDELINES
BOTTOM PAD GND Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to
33 connect to ground planes in PCB to ensure there is sufficient thermal dissipation directly under the IC.
1 CSON Run two dedicated trace with decent width in parallel (close to each other to minimize the loop area) from the two
terminals of the battery current sensing resistor to the IC. Place the differential mode and common-mode RC filter
2 CSOP
components in general proximity of the controller.
Route the current sensing traces through vias to connect the center of the pads; or route the traces into the pads from
the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current
sensing traces.
VIAS
CURRENT SENSING TRACES CURRENT SENSING TRACES
3 VSYS Signal pin. Provides feedback for the system bus voltage. Place the optional RC filter in general proximity of the
controller. Run a dedicated trace from system bus to the pin and do not route near the switching traces. Do not share
the same trace with the signal routing to the DCIN pin OR diodes.
4 BOOT2 Switching pin. Place the bootstrap capacitor in general proximity of the controller. Use decent wide trace. Avoid any
sensitive analog signal trace from crossing over or getting close.
5 UGATE2 Run these two traces in parallel fashion with decent width. Avoid any sensitive analog signal trace from crossing over
or getting close. Recommend routing PHASE2 trace to high-side MOSFET source pin instead of general copper.
6 PHASE2
The IC should be placed close to the switching MOSFETs gate terminals and keep the gate drive signal traces short
for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs.
Place the output capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET
source; and use shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs
instead of on different layers and using vias to make the connection.
Place the inductor terminal to the switching high-side MOSFET drain and low-side MOSFET source terminal as close
as possible. Minimize this phase node area to lower the electrical and magnetic field radiation but make this phase
node area big enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of the
PCB.
7 LGATE2 Switching pin. Run LGATE2 trace in parallel with UGATE2 and PHASE2 traces on the same PCB layer. Use decent
width. Avoid any sensitive analog signal trace from crossing over or getting close.
8 VDDP Place the decoupling capacitor in general proximity of the controller. Run the trace connecting to VDD pin with decent
width.
9 LGATE1 Switching pin. Run LGATE1 trace in parallel with UGATE1 and PHASE1 traces on the same PCB layer. Use decent
width. Avoid any sensitive analog signal trace from crossing over or getting close.
10 PHASE1 Run these two traces in parallel fashion with decent width. Avoid any sensitive analog signal trace from crossing over
or getting close. Recommend routing PHASE1 trace to high-side MOSFET source pin instead of general copper.
11 UGATE1
The IC should be placed close to the switching MOSFETs gate terminals and keep the gate drive signal traces short
for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs.
Place the input capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET
source; and use shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs
instead of on different layers and using vias to make the connection.
Place the inductor terminal to the switching high-side MOSFET drain and low-side MOSFET source terminal as close
as possible. Minimize this phase node area to lower the electrical and magnetic field radiation but make this phase
node area big enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of the
PCB.
FN8877 Rev.3.00 Page 42 of 45

Sep 7, 2017
ISL9238
Layout (Continued)
PIN NUMBER PIN NAME LAYOUT GUIDELINES

12 BOOT1 Switching pin. Place the bootstrap capacitor in general proximity of the controller. Use decent wide trace. Avoid any
sensitive analog signal trace from crossing over or getting close.
13 ASGATE Run this trace with decent width in parallel fashion with the ADP pin trace.
14 CSIN Run two dedicated trace with decent width in parallel (close to each other to minimize the loop area) from the two
terminals of the adapter current sensing resistor to the IC. Place the Differential mode and common-mode RC filter
15 CSIP
components in general proximity of the controller.
Route the current sensing traces through vias to connect the center of the pads; or route the traces into the pads from
the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current
sensing traces.
VIAS
CURRENT SENSING TRACES CURRENT SENSING TRACES
16 ADP Run this trace with decent width in parallel fashion with the ASGATE pin trace.
17 DCIN Place the OR diodes and the RC filter in general proximity of the controller. Run the VADP trace and VSYS trace to the
OR diodes with decent width.
18 VDD Place the RC filter connecting with VDDP pin in general proximity of the controller. Run the trace connecting to VDDP
pin with decent width.
19 ACIN Place the voltage divider resistors and the optional decoupling capacitor in general proximity of the controller.
20 OTGEN/CMIN No special consideration.
21 SDA Digital pins. No special consideration. Run SDA and SCL traces in parallel.
22 SCL
23 PROCHOT# Digital pin, open-drain output. No special consideration.
24 ACOK Digital pin, open-drain output. No special consideration.
25 BATGONE Digital pin. Place the 100kΩ resistor series in the BATGONE signal trace and the optional decoupling capacitor in
general proximity of the controller.
26 OTGPG/CMOUT Digital pin, open-drain output. No special consideration.
27 PROG Signal pin. Place the PROG programming resistor in general proximity of the controller.
28 COMP Place the compensation components in general proximity of the controller. Avoid any switching signal from crossing
over or getting close.
29 AMON/BMON No special consideration. Place the optional RC filter in general proximity of the controller.
30 PSYS Signal pin, current source output. No special consideration.
31 VBAT Place the optional RC filter in general proximity of the controller. Run a dedicated trace from the battery positive
connection point to the IC.
32 BGATE Use decent width trace from the IC to the BGATE MOSFET gate. Place the capacitor from BGATE to ground close to the
MOSFET.
FN8877 Rev.3.00 Page 43 of 45

Sep 7, 2017
ISL9238
Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please visit our website to make sure that you have the latest revision.
DATE REVISION CHANGE
September 7, 2017 FN8877.3 Removed ISL9238A part due to non-applicable changes to this datasheet.
Updated Table 2 on page 20 added Revision ID.
Updated Table 12 on page 25.
Updated About Intersil section.
November 9, 2016 FN8877.2 Remove the ISL9238AIRTZ parts from Ordering Information table.
Updated POD L32.4x4D. Changes: Added 0.035 Nominal value to standoff height
September 7, 2016 FN8877.1 Increased HBM ESD from 1.5kV to 2kV.

Updated Applications and 1st paragraph to include more broad applications.
August 31, 2016 FN8877.0 Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2016-2017. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8877 Rev.3.00 Page 44 of 45

Sep 7, 2017
ISL9238
Package Outline Drawing For the most recent package outline drawing, see L32.4x4D.
L32.4x4D
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/16
2.80
4.00 A 6
28X 0.40 PIN #1
6 B
INDEX AREA
PIN 1
INDEX AREA
4.00
2.70 ±0.10
(4X) 0.10
32X 0.30 32X 0.20
b 0.10 M C A B
TOP VIEW BOTTOM VIEW 4
(3.90 TYP)
(2.80) 0.75
SEE DETAIL “X”
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 2.70)
(28X 0.40)
C 5
(32X 0.20)
0.00 MIN
(32X 0.50) 0.05 MAX
0.2 REF
0.035 NOMINAL
TYPICAL RECOMMENDED LAND PATTERN
DETAIL “X”
NOTES:
1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ±0.05.
4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.25mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8877 Rev.3.00 Page 45 of 45

Sep 7, 2017

Intersil ISL9238IRTZ Datasheet

Uploaded by

Copyright:

Available Formats

Intersil ISL9238IRTZ Datasheet

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Intersil ISL9238IRTZ Datasheet

Uploaded by

Copyright:

Available Formats

DATASHEET

The ISL9238 is a buck-boost Narrow Output Voltage DC (NVDC)

FIGURE 1. TYPICAL APPLICATION CIRCUIT

FN8877 Rev.3.00 Page 1 of 45

FN8877 Rev.3.00 Page 2 of 45

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

PART NUMBER I2C READ ADDRESS I2C WRITE ADDRESS

ISL9238 0b00010011 (0x13H) 0b00010010 (0x12H)

ISL9238A 0b00011011 (0x1BH) 0b00011010 (0x1AH)

FN8877 Rev.3.00 Page 3 of 45

BOOT2 4 GND 21 SDA

FN8877 Rev.3.00 Page 4 of 45

FN8877 Rev.3.00 Page 5 of 45

MODULATOR AND DRIVER

PROCHOT# DRV VDDP

FIGURE 2. BLOCK DIAGRAM

FN8877 Rev.3.00 Page 6 of 45

Simplified Application Circuit

ACOK ISL9238, ISL9238A

FIGURE 3. SIMPLIFIED APPLICATION DIAGRAM

FN8877 Rev.3.00 Page 7 of 45

Absolute Maximum Ratings Thermal Information

FN8877 Rev.3.00 Page 8 of 45

FN8877 Rev.3.00 Page 9 of 45

FN8877 Rev.3.00 Page 10 of 45

FN8877 Rev.3.00 Page 11 of 45

FN8877 Rev.3.00 Page 12 of 45

FN8877 Rev.3.00 Page 13 of 45

SMBUS Timing Specification (Note 9)

SMBus Frequency FSMB 10 400 kHz

Bus Free Time tBUF 4.7 µs

Start Condition Hold Time from SCL tHD:STA 4 µs

Start Condition Set-Up Time from SCL tSU:STA 4.7 µs

Stop Condition Set-Up Time from SCL tSU:STO 4 µs

SDA Hold Time from SCL tHD:DAT 300 ns

SDA Set-Up Time from SCL tSU:DAT 250 ns

SCL Low Period tLOW 4.7 µs

SCL High Period tHIGH 4 µs

SMBus Inactivity Timeout Maximum charging period without a SMBus 175 s

Gate Driver Timing Diagram

FIGURE 4. GATE DRIVER TIMING DIAGRAM

FN8877 Rev.3.00 Page 14 of 45

FIGURE 7. ADAPTER REMOVAL, VADP = 2OV, VBAT = 11V, CHARGECURRENT = 0A

FN8877 Rev.3.00 Page 15 of 45

Typical Performance (Continued)

FN8877 Rev.3.00 Page 16 of 45

Typical Performance (Continued)

FN8877 Rev.3.00 Page 17 of 45

Typical Performance (Continued)

General SMBus Architecture START and STOP Conditions

FIGURE 22. START AND STOP WAVEFORMS

FIGURE 20. GENERAL SMBus ARCHITECTURE Acknowledge

DATA LINE CHANGE

FIGURE 21. DATA VALIDITY

FN8877 Rev.3.00 Page 18 of 45

SMBus and I2C Compatibility

START ACKNOWLEDGE ISL9238 SMBus Commands

READ FROM A REGISTER

FIGURE 24. SMBus READ AND WRITE PROTOCOL