ADPLL
ADPLL
ADPLL
Under the guidance of: Dr. Syamal Kumar Dana Scientist F & Head Instrumentation Division Indian Institute of Chemical Biology Jadavpur, Kolkata.
Summer Project Evaluation
Phase Locked Loop is a circuit that synchronizes an output signal (generated by an oscillator) with a reference or input signal in frequency.
*
Summer Project Evaluation
1.Linear PLL
A linear PLL has all analog components.
2.Digital PLL
Digital PLL has digital as well as analog components such as the charge pump.
4.Software PLL
Algorithm based PLL where functions of a PLL are performed by a computer based program written using high level languages like C/C++ which finally are programmed into microcontrollers.
*
Summer Project Evaluation
*
x(t) Phase Detector Loop Filter Frequency Divider
Voltage Controlled Oscillator
y(t)
* There are 4 components of a PLL: 1.Phase Detector 2.Loop Filter 3.Voltage Controlled Oscillator 4.Frequency Divider
Summer Project Evaluation
Compulsory Components
Optional Component
4
5th Nov 2011
ANALOG PLL
*
* Inputs of the Phase Detector:
1. Reference input 2. Feedback from VCO
*
Counter u1 u2 J K Q Enable N Clock High Frequency Clock Reset
u1 u2 Q N
t t t t
*
Summer Project Evaluation
*
Modulus Control (K) K Clock UP/ DN UP Counter Down Counter Carry Borrow
*
*All PLLs employ an oscillator
element with variable capability.
2(t) = 0 + K0uf(t) of 0 = center angular frequency the VCO K0 = VCO Gain (rad.s-1V-1)
Summer Project Evaluation
10
*
ID CLK Carry Borrow CP INC DEC OUT ID OUT = (ID CLK) . (TOGGLE FF)
* ID Counter is sensitive to the positive edges of the clock. * ID Clock frequency is 2Nf0 where N is the modulus control for
the Modulo N counter.
11
*
1.No BORROW or CARRY pulses
ID CLK TOGGLE ID OUT
ID CLK
12
ID CLK
13
*
Summer Project Evaluation
14
*
* Parameters of the ADPLL:
o K Modulus control of the K counter loop filter o M The frequency of the clock signal of K counter is M times the center frequency of
the ADPLL. o N Modulus control of the modulo N counter and the IDCLK frequency 2Nf0. o For minimum phase jitter M=2K
o N > N(practical) = * Values of K, N and M considered for an ADPLL with center frequency of 10MHz are
f0 = 10MHz K=8 N=8 M = 16
= 0.4 usec
15
5th Nov 2011
16
Member, An FPGA-Based Linear All-Digital PhaseLocked Loop, IEEE Trans. on Circuits Syst-I, Regular paper, vol. 57, no. 9, Sept. 2010. pp.2487-2497.
*
Summer Project Evaluation
17