PDF Switch Router Architectures Systems With Crossbar Switch Fabrics 1St Edition James Aweya Author Ebook Full Chapter
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Switch/Router
Architectures
Switch/Router
Architectures
Systems with Crossbar Switch Fabrics
James Aweya
CRC Press
Taylor & Francis Group
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Contents
Preface���������������������������������������������������������������������������������������������������������������� xv
Author���������������������������������������������������������������������������������������������������������������xvii
v
vi Contents
Index����������������������������������������������������������������������������������������������������������������� 343
Preface
The continuous growth of the Internet is still creating increasing demands for
bandwidth and new services from service providers’ networks. The growing reli-
ance on the Internet has also created the demand for value-added services that
require faster connectivity, higher quality of service, and more advanced mobile
user services. There is little doubt that the rising demand for Internet connectivity
and new services will continue to task the performance of network infrastructures
and the individual network devices that make those networks. Networks are also
under pressure to deliver these advanced services cost-effectively and at reduced
operational costs.
Switches, switch/routers, routers, and network devices, in general, have tradi-
tionally been based on the following basic interconnect architectures: shared bus,
shared memory, ring fabric (using point-to-point interconnects), and the crossbar
switch. Shared-bus architectures are simple in design and are easy to implement.
They can be constructed from readily available standard commercial products.
However, despite these advantages, designers have discovered over the years that
shared-bus architectures have practical performance, scalability, and fault toler-
ance limitations. On the issue of signal integrity, the bus architecture has practical
limits on the operating frequency that can be supported, signal propagation delays
(or path lengths) that are tolerable, and electrical loading on the signal lines.
The shared bus has serious bus bandwidth utilization limitation because it
allows only one data transfer on the bus at a time. On the shared-bus fabric, only
one transmission (time-slot) can be carried/propagated on the bus at any given
time, which can result in limited throughput, scalability, and low number of net-
work interfaces supported. Although multiple buses can be used to increase the
throughput and improve the reliability of bus-based architectures, its inability to
scale cost-effectively with higher data rates, number of network interfaces, and
bus clock speeds is a serious limitation.
The main disadvantage of a shared-memory architecture is that bandwidth
scalability is limited by the memory access speed (bandwidth). The access speeds
of memories have a physical limit, and this limit prevents the shared-memory
switch architecture from scaling to very high bandwidths and port speeds.
Another factor is that the shared-memory bandwidth has to be at least two times
the aggregate system port speeds for all the ports to run at full line rate.
Ring architectures overcome the one-at-a-time data-transfer limitations of the
shared bus by allowing multiple concurrent data transfers on the ring in order to
achieve higher aggregate data throughput. However, high data transfer latencies
and ring reliability issues such as single points of failure are major concerns in
ring architectures. The ring is susceptible to single-point-of-failures because it
supports only one path between any two adjacent nodes. One malfunctioning node
or link on the ring can disrupt communication on the entire fabric. The capacity
of the ring architectures can be improved by implementing multiple parallel rings.
xv
xvi Preface
These rings are usually controlled in a distributed manner, but Medium Access
Control (MAC) implementation on the multiple rings can be difficult to realize.
Given the limitations of the other interconnect architectures, designers
have long considered the use of crossbar switch fabrics, especially for high-
performance, high-capacity systems. Crossbar switch fabrics offer several design
benefits over the traditional shared-media fabrics. High-performance crossbar
switches can support multiple data transfers over the fabric at the same time and
can easily be made nonblocking, avoiding the bandwidth limitations seen in the
shared-media fabrics with one-at-a-time data transfer type of operations.
Crossbar switch fabrics have the flexibility of connecting any input to any
output, allowing for multiple concurrent data transfers. They can be designed
to have relatively higher bandwidth, scalability, and fault tolerance. In addition
to its basic architectural advantages, the crossbar switch can be implemented in
ASICs and FPGAs. Bigger switches can be constructed from smaller crossbar
switch chips. There is an abundance of literature from the commercial sector and
academia on how to design crossbar switch fabrics of different types and capabili-
ties. For this reason, a comprehensive list of references will be nearly impossible
in this book. More so, crossbar switch fabric design has been a very well-studied
area, especially during the days of Asynchronous Transfer Mode (ATM) switch
development.
This book discusses the various switch/router architectures that use crossbar
switch fabric as their internal interconnects. The book also discusses the main
issues involved in the design of these switch/routers that use crossbar switch fab-
rics. The issues discussed include performance, implementation complexity, and
scalability to higher speeds. To enhance reader understanding of switch/routers,
the book begins by describing the basics of switch/routers and then the most com-
mon crossbar switch fabric-based architectures in today’s networks.
After presenting a detailed discussion of centralized versus distributed for-
warding architectures, the book discusses the processing considerations that led
to the design of distributed forwarding systems using crossbar-based switch fab-
rics. The discussion includes the hardware and software designs in select but dif-
ferent switch/router architectures, to allow the reader to appreciate the different
designs out there and how crossbar-based switch/routers have evolved over the
years. The book uses case studies to examine the inner workings of switch/router
design in a comprehensive manner with the goal of enhancing reader understand-
ing. The example architectures discussed are selected such that they cover the
majority of features found in switch/routers used in today’s networks. It is written
in a simple style and language to allow readers to easily understand and appreci-
ate the material presented.
Author
James Aweya, PhD, is a chief research scientist at Etisalat British Telecom
Innovation Center (EBTIC), Khalifa University, Abu Dhabi, UAE. He has been
granted 64 US patents and has published over 54 journal papers, 39 conference
papers, and 43 Nortel technical reports. He has authored one book and is a senior
member of the Institute of Electrical and Electronics Engineers (IEEE).
xvii
Part 1
Characteristics of Switch/Routers
with Crossbar Switch Fabrics
1 Integrated OSI Layers
The Switch/Router
2 and 3 Forwarding on
a Single Platform
1.1 INTRODUCTION
This chapter introduces switch/routers and the architectures and methods they
support to perform multilayer switching. An understanding of multilayer switch-
ing is necessary for the reader to better appreciate the various architectures dis-
cussed in this book. A switch/router, sometimes referred to as a multilayer switch,
is a device that supports the forwarding of packets at both Layers 2 and 3 of the
Open Systems Interconnection (OSI) model (Figure 1.1).
The switch/router also supports the relevant Layers 2 and 3 control plane proto-
cols needed to create the forwarding databases used in the forwarding of packets
[AWEYA1BK18]. In addition to features for system management and configura-
tion, the switch/router may support quality-of-service (QoS) and security filtering
and control mechanisms that use parameters within the Layers 4 to 7 fields of
packets being forwarded.
Network devices attached to different virtual local area networks (VLANs)
can only communicate with one another through a router (or Layer 3 forwarding
device) as illustrated in Figure 1.1. In a Layer 2 network, VLANs can be used to
define distinct and separate broadcast domains. Each defined broadcast domain
(or VLAN) is the set of devices attached to that domain that can receive Layer 2
broadcast packets (e.g., Ethernet frames) sent from any device within that domain.
Routers are typically used to bound the distinct broadcast domains (VLANs)
because routers do not forward broadcast frames—all broadcast traffic within a
VLAN is confined to that VLAN and cannot cross any attached router. VLANs
are designed to mimic the behavior of legacy shared-medium LAN segments
where broadcasts from any one device are seen by all other devices on that LAN
segment.
Layer 2 forwarding is relatively simple compared to Layer 3 forwarding
[AWEYA1BK18]. To perform Layer 3 forwarding, the switch/router needs a route
processor (also referred to as Layer 3 control engine) that runs the routing and
management protocols for the system. The routing protocols build and maintain
the routing tables required for Layer 3 forwarding. In addition to creating the rout-
ing and forwarding databases (tables), the route processor also performs all the
non-data transfer housekeeping functions for the system (system configuration,
3
4 Switch/Router Architectures
Switch/Router
A4 B1
VLAN A VLAN B
A1
A3 B3
A2 B2
Forwarding Forwarding
Table Table
Flow/Route
Cache
Network
Network Network Network Flow/ Interfaces
Interface Interface Interface Route Output
Cache Processing
First Packet Subsequent Packets
of a Flow of a Flow First Packet Subsequent Packets
of a Flow of a Flow
FIGURE 1.2 ayer 3 Forwarding Using Flow-Based Forwarding Table (or Flow/Route
L
Cache).
Master
Routing Adjacency
Forwarding
Table Table
Table
Routing Route
Protocols Processor
Adjacency Adjacency
Table Input Output Table Input Output
Processing Processing Processing Processing
Layer 3 Layer 3
Packets Packets
The topology-based forwarding model allows the separation (or decoupling) of the
control-plane functions (i.e., running routing and control protocols) from the data-
plane functions (i.e., forwarding table lookups and packet rewrites). Nevertheless,
the control-plane functions (running software in the route processor) are still
responsible for creating and maintaining the master forwarding and adjacency
tables and then downloading these to the data-plane functions (running in the
forwarding engine(s)).
A switch/router may support multiple route processors for redundancy pur-
poses (e.g., primary and secondary route processors running in active-active or
active-standby mode). A switch/router may also support multiple forwarding
engines running in a distributed manner each using a copy of the master forward-
ing table maintained by the route processor.
The forwarding engine may not be able to forward all packets it receives. These
special packets have to be forwarded to the route processor for further processing.
Examples of these special (or exemption) packets are:
Centralized
Forwarding
Centralized Processing Module Route Processor Module Engine Module
Master
Routing
Forwarding
Table
Table
Routing Route
Protocols Processor
Switch Fabric
Layer 3 Layer 3
Packets Packets
including more processing beyond pure data-path processing) adopt this central-
ized ARP processing approach.
High-capacity, high-performance routing systems are generally based on dis-
tributed forwarding architectures. The forwarding performance and throughput
with distributed forwarding is equal to the aggregate throughput of all the dis-
tributed forwarding engines as long as the switch fabric is not a bottleneck. The
distributed forwarding architecture also allows each line card to be specifically
designed to support its own unique set of local functions and interfaces (encryp-
tion, network address translation capabilities, tunneling protocols, different types
of Layer 2 protocols and encapsulations, mix of interface types and speeds, etc.).
Each line card can be tailor made to meet specific design objectives without being
unnecessarily constrained by issues in other system modules.
The Catalyst 6500 with a Supervisor Engine 720 (discussed in Chapter 8)
supports distributed forwarding using a built-in crossbar switch fabric module
and line cards that have an integrated Distributed Forwarding Card (DFC). This
Catalyst 6500 switch/router still maintains a centralized forwarding engine (in a
module called the Policy Feature Card (PFC)) even when using line cards with
DFCs for backward-compatibility with older line cards that do not support the
DFC feature.
645
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in thermic fever,
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636
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1176
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).
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709
Treatment,
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external pachymeningitis,
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706
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705
Treatment,
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internal pachymeningitis,
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747
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of acute myelitis,
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718
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of catalepsy,
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of chorea,
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of chronic hydrocephalus,
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of delirium tremens,
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of ecstasy,
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of hysteria,
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of hystero-epilepsy,
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of spina bifida,
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of symmetrical gangrene,
1261
of tabes dorsalis,
839
840
of tubercular meningitis,
729
1045
of vertigo,
418
of writers' cramp,
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47
Dyslalia,
569
572
601
607
Dysphagia, hysterical,
239
245
E.
249
influence on causation of acute pachymeningitis,
716
of external pachymeningitis,
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474
of epilepsy,
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of vertigo,
421
698
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464
464
CSTASY
339
Definition,
339
343
Etiology,
341
339
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Symptoms,
342
Treatment,
344
444
Education, improper, as a cause of hysteria,
218
220
979
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868
in Bell's palsy,
1205
1206
in diffuse sclerosis,
890
in infantile paralysis,
1125
864
1184
1188
1207
in catalepsy,
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in chronic lead-poisoning,
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in hysteria,
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286
in hystero-epilepsy,
311-313
1156
in labio-glosso-laryngeal paralysis,
1175
in migraine,
415
1232
in multiple neuritis,
1198
in myelitis, acute,
824
in myxœdema,
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in nerve injuries,
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in neuralgia,
1225