Genesys Logic GL823K HCY04 - C284879
Genesys Logic GL823K HCY04 - C284879
Genesys Logic GL823K HCY04 - C284879
GL823K
USB 2.0 SD/MSPRO Card Reader
Controller
Datasheet
Revision 1.05
May 24, 2016
GL823K Datasheet
Copyright
Copyright © 2016 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any
form or by any means without prior written consent of Genesys Logic, Inc.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise,
regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual
property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any
direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys
Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.
Revision History
Table of Contents
CHAPTER 2 FEATURES...................................................................................................... 7
List of Figures
List of Tables
The GL823K integrates a high speed 8051 microprocessor and a high efficiency hardware engine for the best
data transfer performance between USB and flash card interfaces. Its pin assignment design fits to card sockets
to provide easier PCB layout. Inside the chip, it integrates 5V to 3.3V regulator, 3.3V to 1.8V regulator and
power MOSFETs and it enables the function of on-chip clock source (OCCS) which means no external 12MHz
XTAL is needed and that effectively reduces the total BOM cost.
The GL823K implements USB disconnect function; it can be used for Mobile cable/ OTG reader/ PC card reader
application.
CHAPTER 2 FEATURES
USB specification compliance
- Comply with 480Mbps Universal Serial Bus specification rev. 2.0
- Comply with USB Storage Class specification rev. 1.0
- Support one device address and up to four endpoints: Control (0)/Bulk Read (1)/Bulk Write (2)/Interrupt (3)
Integrated USB building blocks
- USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and
low-voltage detector (LVD)
Embedded 8051 micro-controller
- Operate @ 60 MHz clock, 12 clocks per instruction cycle
- Embedded mask ROM and internal SRAM
TM TM
Secure Digital (SD) and MultiMediaCard (MMC)
- Supports SD specification v1.0 / v1.1 / v2.0 / SDHC (Up to 32GB)
- Compatible with SDXC (Up to 2TB)
- Supports MMC specification v3.x / v4.0 / v4.1 / v4.2
- Supports 1 / 4 bit data bus
- Compliant with Secure DigitalTM v5.0
Memory Stick PRO / Memory Stick PRO Duo / Memory Stick PRO-HG / MS Micro (M2)
- Compliant with Memory Stick Series Specification: MS PRO v1.05, MS PRO-HG Duo 1.03, MS
Micro (M2) v1.06
- Support 4bit data bus
Support boost mode for SD3.0 for better performance
Support non-SD Card Detect pin, non-MS Insertion/Removal pin design to save BOM cost
Support non-SD Write Protection pin design to save BOM cost
Support LED function to indicate power and access status
On chip clock source and no need of 12MHz Crystal Clock input
On-Chip 5V to 3.3V and 3.3V to 1.8V regulators
On-Chip power MOSFET for supplying flash media card power
Support USB disconnection by memory card unplug or manual switch for Mobile cable/ OTG reader/ PC
card reader application
Available in SSOP16 package (150 mil)
13 VDDA
11 GPIO
9 VDD
12 LED
14 VSS
16 DM
10 5V
15 DP
GL823K
SSOP-16 (150mil)
CMD 5
D3 6
PMOS 8
VSS 1
D0 3
D2 7
D1 2
CLK 4
Notation:
Type O Output
I Input
B Bi-directional
pu internal pull-up when input
pd internal pull-down when input
P Power / Ground
A Analog
Regulator
MHE EPFIFO
5 to 3.3V
3.3 to 1.8V
EP0/EP3 FIFO
MSPRO 4bit
I/F RAM
Control 8051
Register CORE
ROM
4.2 SIE
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing
and state machine logic to handle USB packets and transactions.
4.3 EPFIFO
Endpoint FIFO includes Control FIFO (FIFO0) and Bulk In/Out FIFO
EP0 FIFO FIFO of control endpoint 0. It is 64-byte FIFO and used for endpoint 0 data transfer.
Interrupt FIFO 64-byte depth FIFO of endpoint 3 for status interrupt
Bulk FIFO It can be in the TX mode or RX mode:
1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.
2. It can be directly accessed by micro-controller
4.4 MCU
8051 micro-controller inside.
8051 Core Compliant with Intel 8051 high speed micro-controller
ROM FW code on ROM
SRAM Internal RAM area for MCU access
4.5 MHE
MIF Media Interface: SD/MMC
MCFIFO It can access by MCU for memory card short data packet.
4.6 Regulator
5V to 3.3V Band Gap Regulator for stable voltage supply for USB PHY, PMOS
3.3V to 1.8V For core logic and internal memory.
4.7 PMOS
On-Chip power MOSFETs for memory card power
Parameter Value
Storage Temperature -65C to +150 C
Operating Temperature 0C to +70 C
Parameter Value
Supply Voltage +4.75V to +5.25V
Ground Voltage 0V
5.3 DC Characteristics
Table 5.3 – DC Characteristics
Internal Version
No. GL823K No.
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Date
Lot Code
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