8th International Conference on Power Electronics - ECCE Asia

[WeP1-050] May 30-June 3, 2011, The Shilla Jeju, Korea

Single-Stage Bridgeless Three-Level AC/DC Converter with

Current Doubler Rectifier

Woo-Young Choi*, Jae-Yeon Choi, Ju-Seung Yoo,

Division of Electronic Engineering
Chonbuk National University, Jeonju, South-Korea
*
[email protected]

[5], [6]. Similar efforts have been put in optimizing and

Abstract — This paper proposes a new bridgeless single-stage improving the performance of the converter by using active-
three-level ac-dc converter. The proposed converter integrates clamping techniques [7], [8]. The majority of these
the operation of the bridgeless power factor correction (PFC) development efforts have been focused on reducing switching
boost rectifier and the zero-voltage switching (ZVS) three-level power losses on the power conversion efficiency. However, so
dc-dc converter. The proposed converter provides high power far no single-stage ac-dc converter without using the full-
factor and direct power conversion from the line voltage to an
bridge diode rectifier has been reported. The single-stage ac-
isolated dc output voltage without using the full-bridge diode
rectifier. Conduction losses are lowered with a simple circuit dc converters still use the full-bridge diode rectifier, which
structure. Voltage stresses of the power switches are reduced by causes high conduction losses. The full-bridge diode rectifier
the use of three-level topology. Switching losses are also reduced suffers from significant conduction losses especially at low
by achieving ZVS of the power switches. The effectiveness of the line voltage. Thus, a bridgeless single-stage ac-dc converter
proposed converter is verified on a 400 W (48 V/8.33 A) should be studied to reduce conduction losses and component
experimental prototype at 90 Vrms line voltage. counts.
This paper proposes a new bridgeless single-stage three-
level ac-dc converter. The proposed converter integrates the
Index Terms—Bridgeless, single-stage, three-level, AC/DC
converter, current doubler rectifier.

I. INTRODUCTION
The research for single-stage ac-dc converters has been an
active research topic for power factor correction (PFC)
circuits in the power electronics. A number of single-stage
PFC ac-dc converters have been introduced in the literature.
Among them, discontinuous-conduction-mode (DCM) single-
stage PFC ac-dc converters are widely used for their simple
and efficient structures [1]-[8]. Generally, two power stages of
the PFC circuit and dc-dc converter are simplified by sharing
a common switch [1]-[4] or a pair of switches [5]-[8]. Most
single-stage PFC ac-dc converters use single-switch dc-dc
converter topologies such as flyback [1], [2] and forward
converters [3], [4]. However, the single-stage single-switch
ac-dc converters operate under hard-switching condition. The
voltage stresses of switching devices and power conversion Fig. 1. Circuit diagram of the proposed converter.
efficiency have not been optimized yet. The practical use of
the single-stage single-switch ac-dc converters has been
operation of the bridgeless PFC boost rectifier [9]-[12] and
limited for low-power applications with power levels lower
zero-voltage switching (ZVS) three-level dc-dc converter
than 80 W.
[13]-[15]. The proposed converter provides high power factor
Single-stage soft-switching ac-dc converters have been
and direct power conversion from the line voltage to an
developed to improve the performance of single-stage PFC ac-
isolated dc output voltage without using the full-bridge diode
dc converters [5]-[8]. Single-stage soft-switching ac-dc
rectifier. By allowing the boost inductor to operate in DCM,
converters based on the half-bridge converter topology are
PFC and fast output voltage regulation are performed
attractive because they provide low component count and
simultaneously by the asymmetrical pulse-width modulation
zero-voltage switching (ZVS) operation of the power switches
(APWM) control of power switches.

978-1-61284-957-7/11/$26.00 ©2011 IEEE

Fig. 2. Operating modes of the proposed converter in a positive half-line cycle.
Conduction losses are lowered by essentially eliminating the
full-bridge diode rectifier. Voltage stresses of the power
switches are reduced by the use of three-level topology.
Switching losses are also reduced by achieving zero-voltage
switching (ZVS) of the power switches. The proposed
approach not only reduces the number of circuit components,
but also makes it possible to increase power efficiency of
single-stage PFC ac-dc converter. The performance of the
proposed converter is evaluated by the experimental results
based on a 400 W (48 V/8.33 A) converter prototype. The
proposed converter achieves a high-efficiency of 93 % with
almost unity power factor at 90 Vrms line voltage.

II. OPERATION PRINCIPLE

Fig. 1 shows a circuit diagram of the proposed converter.
The bridgeless PFC boost rectifier consists of the boost
inductor Lb, dc-link capacitors Cd1 and Cd2, and switching
devices D1 ~ D4, and S1 ~ S4. S1 ~ S4 are MOSFETs with
output capacitors CS1 ~ CS4. DS1 ~ DS4 are body diodes of S1 ~ Fig. 3. Circuit diagram of the simulation circuit.
S4. The three-level dc-dc converter has the blocking capacitor
Cb, transformer T, output diodes Do1 and Do2, output filter
released to the dc-link capacitors. The transformer T transfers
inductor Lo, and output capacitor Co.
energy to the output through the output diode Do2.
By sharing dc-link capacitors and power switches, the
Mode 5 [t4, t5]: At t = t4, the boost inductor current iLb is
proposed converter integrates the operation of the bridgeless
zero. The transformer T still transfers energy to the output
PFC boost rectifier and the ZVS three-level dc-dc converter.
through the output diode Do2.
By allowing the boost inductor to operate in DCM, PFC and
Mode 6 [t5, t6]: At t = t5, S4 is turned off. The clamping
fast output voltage regulation are performed simultaneously
diode D4 serves to clamp the switch voltage VS4 to half the dc-
by the APWM control of power switches. For both positive
bus voltage. The primary current ip charges CS4 and discharges
and negative half-line cycle of vi, the proposed converter has
CS1 and CS2.
symmetric operation. In the positive half-line cycle, S1 and S2
Mode 7 [t6, t5]: At t = t6, S3 is turned off. The primary
are controlled with duty ratio D. When the conduction times
current ip begins flowing through the body diodes DS1 and DS2.
of the switches S1 and S2 are DTs, the conduction times of the
ZVS of S1 and S2 can be achieved because the voltages across
switches S3 and S4 are (1–D)Ts. The transformer T has the
the switches are zero when S1 and S2 are turned on again.
magnetizing inductor Lm and leakage inductor Llk with the
turns ratio of 1 : n.
III. EXPERIMENTAL RESULTS
Fig. 2 shows the operating modes of the proposed converter
during Ts for the positive half-line cycle. Only the operation A 400 W converter prototype was built and tested. The
principle for the positive half-line cycle is described in this proposed converter has the following parameters as line
section. Due to the symmetric operation, the operation voltage vi = 90 Vrms, output voltage Vo = 48 V, switching
principle for the negative half-line cycle is not described here. frequency fs = 100 kHz, boost inductor Lb = 100 ȝH, blocking
The capacitors Cd1, Cd2, and Co are large enough so that the capacitor Cb = 1 ȝF, dc-link capacitor Cd1 = Cd2 = 440 ȝF,
voltages Vd1, Vd2, and Vo are assumed to be constant. |vi| is
considered constant during one switching period Ts (= fs). output capacitor Co = 680 ȝF, magnetizing inductor Lm = 100
Mode 1 [t0, t1]: At t = t0, S1 and S2 are turned on. The input ȝH, output filter inductor Lo = 30 ȝH. The circuit design was
current ii flows through Lb, D1, S1, and S2. The boost inductor simulated using PSIM 6.0; the schematic circuit is shown in
Lb stores energy from the line voltage. The transformer T Fig. 3. Fig. 4 shows the simulation results when the proposed
transfers energy to the output through the output diode Do1. converter supplies 400 W output power. Fig. 4(a) shows the
Mode 2 [t1, t2]: At t = t1, S1 is turned off. The clamping line voltage vi, boost inductor current iLb, and dc-link voltage
diode D3 serves to clamp the switch voltage VS1 to half the dc- Vd at vi = 90 Vrms, respectively. Fig. 4(b) shows the voltage
bus voltage. The primary current ip charges CS1 and discharges and current waveforms of power switches S1 and S2, and the
CS3 and CS4. output voltage Vo. Fig. 4(c) shows the voltage and current
Mode 3 [t2, t3]: At t = t2, S2 is turned off. The primary waveforms of power switches S3 and S4, and the output
current ip begins flowing through the body diodes DS3 and DS4. voltage Vo.
Mode 4 [t3, t4]: At t = t3, S3 and S4 are turned on. ZVS of S3 Fig. 5 shows the experimental results when the proposed
and S4 is achieved because the voltages across the switches are converter supplies 400 W output power. It shows the line
zero. The input current ii flows through Lb, D1, Cd1, Cd2, S4, current ii at vi = 90 Vrms. The proposed converter achieves a
DS4, S3, and DS3. The energy stored in the boost inductor Lb is high-efficiency of 93 % with almost unity power factor at vi =
90 Vrms. Compared to the previous approaches (single-stage
 (a) Fig. 5. Experimental results.

converter has the following features for the single-stage PFC

ac-dc converter as
1. Low conduction losses by essentially eliminating the full-
bridge diode rectifier;
2. Reduced component counts by integrating two power
conversion stages;
3. Low switching losses by the ZVS operation of power
switches.

(b) V. ACKNOWLEDGEMENT
This works was supported by National Research
Foundation of Korea (NRF) grant funded by the Korea
government (MEST) (2010-0029431).

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