J Link Microchip Adapter Schematic-3

Download as pdf or txt
Download as pdf or txt
You are on page 1of 1

1 2 3 4

A A

Socket 20 Pin
MIPS Debug Header 14 Pin (Debug Probe)
(Debug Target) VTREF VTREF
J1 4150
J2
1 2
Specification: TRST TRST
2 1 3 4
Compare MIPS® EJTAG Specification, Rev. 5.04, TDI TDI
4 3 5 6
chpt. 10.4 "Mechanical Connector" TDO TMS
B 6 5 7 8 B
TMS TCK
8 7 9 10
Explorer Board: TCK RTCK
GND 10 9 11 12
Pin 1, Pin 13: Not connected RTCK RST #RESET TDO
12 11 13 14
Pin 12: Not connected + keyed VDD DINT Pin17 #RESET
VTREF 14 13 15 16
Pin17
17 18
DNP VSUPPLY
TP2 19 20
TP1
Socket 2x10
GND
GND

Microchip RJ12 Microchip PICkit


Debug Connector Debug Connector
(Debug Target) (Debug Target)
J3 4113 J4
NC
C 1 1 C
CLK/PGC/RB6
2 2
RJ12

DIO/PGD/RB7
3 3
GND
4 4
VDD
5 VTREF VTREF 5
#MCLR
6 6
5555165-1 DNP
GND GND

History / Changes
Initial Version

SEG G ER
J-Link TM
Technology
www.segger.com
Title
D D
J-Link Microchip Adapter
Size Number Revision
A4 - -
L W R U
Date: 31.07.2013 Sheet 1 / 1
File: J_Link_Microchip_Adapter.SchDoc Drawn: VK
1 2 3 4

You might also like