Ver2.

A1 PROs Ai325CA
1/3 inch CCD Image Sensor for NTSC Camera

GENERAL DESCRIPTION
16 Pin Plastic - DIP
The Ai325CA is a 250K pixels CCD area ( Top View )
sensor for NTSC 1/3 inch video cameras.
Buried photodiodes and micro lenses are
adopted for low noise, low smear and high Vφ4 1 16 Hφ2

sensitivity. A chrominance signal is achieved by Vφ3 2 15 Hφ1

the adoption of Yellow, Magenta, Cyan and Vφ2 3 14 NC

Green complementary color mosaic filters. This Vφ1 4 13 V RG

RG

product also has the features of strong anti- GND 5 12 VP

VNC
GG 6 11 VSUB
blooming and electronic shutter with variable
VNC
SS 7 10 GND
charge-storage time.
VOUT 8 9 VDD

FEATURES
• Micro lens arrays for high sensitivity
• Ye, Mg, Cy and G complementary color mosaic filters
• Excellent blooming suppression
• TTL level(5V) operation on HCCD & RG electrodes
• 16 pin plastic DIP type package
• Variable electronic shutter of 1/60 to 1/100,000 sec
• High sensitivity and low smear
• Low image lag

STRUCTURE
Optical black position ( Top View )
• Architecture : IT - CCD
• Optical size : 1/3 inch format
• Chip size : 6.0(H) x 5.2(V) ㎟ Unit : Pixels Pin1
• Number of effective pixels : 1

510 (H) x 492 (V) about 250K pixels

• Number of total pixels :
537 (H) x 505 (V) about 270K pixels 492

• Pixel size : 9.65 (H) x 7.5 (V) ㎛2

• Optical black area
Horizontal direction : Front 2 pixels Rear 25 pixels
12
Vertical direction : Front 12 pixels Rear 1 pixels
• Number of dummy bits 2 510 25
Horizontal : 16 Pin9
Vertical : 1 ( Even field only )

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 Ai325CA
BLOCK DIAGRAM
VOUT NC NC GND Vφ1 Vφ2 Vφ3 Vφ4
8 7 6 5 4 3 2 1

PD

VCCD
HCCD

9 10 11 12 13 14 15 16

VDD GND VSUB VP VRG NC Hφ1 Hφ2

PIN DESCRIPTION
Pin Symbol Description Pin Symbol Description
1 VΦ4 Vertical register transfer clock 4 9 VDD Output amplifier drain bias

2 VΦ3 Vertical register transfer clock 3 10 GND Ground

3 VΦ2 Vertical register transfer clock 2 11 VSUB Substrate (Overflow drain) bias

4 VΦ1 Vertical register transfer clock 1 12 VP Protection bias

5 GND Ground 13 VRG Reset gate clock

6 NC No connection 14 NC No connection

7 NC No connection 15 HΦ1 Horizontal register transfer clock 1

8 VOUT CCD output signal 16 HΦ2 Horizontal register transfer clock 2

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit
Substrate voltage VSUB – GND –0.3 to +55 V

VDD, VOUT – GND –0.3 to +18 V

Supply voltage
VDD, VOUT – VSUB –55 to +10 V

VΦ1, 2, 3, 4 – GND –10 to +20 V

Vertical clock input voltage VΦ1, 2, 3, 4 – VP –0.3 to +27 V
VΦ1, 2, 3, 4 – VSUB –55 to +10 V

Horizontal clock input voltage HΦ1, HΦ2 – GND –10 to +15 V

Between vertical clock input pins VΦX – VΦY –10 to +15 V

Between horizontal clock

HΦ1, HΦ2 – VΦ4 –17 to +17 V
and vertical clock input pins

ΦRG – GND –10 to +15 V

Output pin voltage
ΦRG – VSUB –55 to +10 V

Protective circuit voltage VP – VSUB –65 to 0.3 V

Storage temperature TSTG –30 to 80 °C

Operation temperature TOPR –10 to 60 °C

* Protective circuit voltage(VP) is induced to the image sensor before VDD supplied power voltage.

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 Ai325CA

BIAS CONDITION
Parameter Symbol Min Typ Max Unit Remark

Output amplifier drain voltage VDD 14.5 15.0 15.5 V

Substrate voltage adjustment range VSUB 5 15 V

Fluctuation range after substrate voltage adjustment △VSUB –1 1 V

Reset gate clock voltage adjustment range VRG 0 4 V *

Fluctuation range after reset gate voltage adjustment △VRG –3 3 %

Set to low level

Protection bias VP
of vertical transfer clock

* No adjustment of reset gate clock voltage is necessary when reset gate clock is driven as indicated below.

Parameter Symbol Min Typ Max Unit Remarks

VRGL –0.2 0.0 0.2 V
Reset gate clock voltage
VRG 8.5 9.0 9.5 V

DC CHARACTERISTICS
Parameter Symbol Min Typ Max Unit

Output amplifier drain current IDD – 3 – ㎃

DRIVING CONDITION
Parameter Symbol Min Typ Max Unit
Vertical clock high voltage VH1, VH3 14.5 15.0 15.5 V

Vertical clock middle voltage VM1, 2, 3, 4 –0.2 0.0 0.2 V

Vertical clock low voltage VL1, 2, 3, 4 –9.0 –8.5 –8.0 V

Horizontal clock high voltage HH1, 2 4.5 5.0 5.5 V

Horizontal clock low voltage HL1, 2 –0.5 0.0 0.5 V

RG clock voltage difference RGHL 4.7 5.0 5.3 V

Substrate clock voltage VSUB 23 24 25 V

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 Ai325CA

ELECTRO-OPTICAL PERFORMANCE ( Ta = 25°C )

Item Symbol Min Typ Max Unit Measurement Method Remark

Sensitivity SENS 65 80 mV/Lux 1

Saturation signal VSAT 900 mV 2 Temp=60 °C

Smear SMR 0.015 % 3

Blooming BL 1 % 4

Video signal shading OSNU 25 % 7

Uniformity between △Sr 10 % 9

video signal channels △Sb 10 % 9

Dark signal level VDARK 2 mV 6 Temp=60 °C

Dark signal shading DSNU 2 mV 8 Temp=60 °C

Flicker Y FY 2 % 5

Flicker B-Y, R-Y FCr, FCb 5 % 10

LCr, LCb,
Line crawl R, G, B, W 20 % 11
LCg, LCw

Image lagging Lag 0.5 % 12

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 Ai325CA

MESUREMENT METHOD

1. Sensitivity
① Set to SILC ( Standard Illumination Conditions* )
② Measure the average value of signal output ( VOUT )
③ Calculate the efficiency of VOUT to light intensity

2. VSAT
① Adjust light intensity to 200 times of SILC
② Measure the average value of signal output

3. Smear
① Adjust light intensity to 200 times of SILC & readout clock
② Measure the signal output at horizontal optical black ( VHOPB )
③ Measure the signal output at vertical blanking dummy ( VVBD )
④ Smear = { (VVBD - VHOPB) / VSAT } × 100 ( % )

4. Blooming
① Adjust light intensity to 200 times of SILC & readout clock
② Measure the signal output at horizontal optical black (VHOPB )
③ Measure the signal output at blooming dummy area ( VBD )
④ Blooming = { ( VBD - VHOPB ) / VSAT } × 100 ( % )

5. OSNU
① Set to SILC
② Measure the average value of signal output ( VOUT )
③ Measure the maximum value and the minimum value of signal output
④ OSNU = ( VMAX - VMIN ) / VOUT ×100 (%)

6. ΔSr,ΔSb
① Set to SILC
② Measure the average value of signal output ( VOUT )
③ Measure the maximum value and minimum value of chroma output
ΔSr = │( CrMAX - CrMIN ) / VOUT │×100 (%)
ΔSb= │( CbMAX - CbMIN ) / VOUT │×100 (%)

7. VDARK
① Measure the average value of signal output at dark condition

8. DSNU
① Measure the voltage difference between minimum and maximum of dark signal

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 Ai325CA

9. FY
① Set to SILC
② Measure the average value of signal output ( VOUT )
③ Measure the difference of signal output between even field and odd field
④ FLK = ( VOUT/ VOUT ) ×100 (%)

10. FCr, FCb

① Set to SILC using the R,B optical filter respectively
② Measure the average value of chroma signal output
③ Measure the difference of chroma signal output between even field and odd field
④ FCi = ( ΔVCiOUT / VCiOUT ) ×100 (%) ( i = r,b )

11. LCr, LCb, LCg, LCw

① Set to SILC using the W,R,B,G optical filter respectively
② Measure the average value of signal output
③ Measure the difference of signal output between signal lines of the same field
(ΔVlw,ΔVlr,ΔVlg,ΔVlb)
④ Lci = (ΔVliOUT / ViOUT ) ×100 (%) ( i = w,r,g,b )

12. Lag
① Light a strobe lamp as follow

TG
V1 V2 V3 V4
odd even odd even

Str

② Lag = { V2(out)+V3(out)+V4(out) } / V1(out)

* Standard Illumination Conditions

① Measure the average value of output of linear region
② At this time, measure the light intensity of illumination at CCD face plate
③ Define SILC with above
④ Light source: Tungsten lamp(3100K)
⑤ Use a standard test lens at F8

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Ai325CA

+15V
100 VR
10K
KDS226
C2223 1M 3.3K
CCD 100
output 0.1
9 VDD VOUT 8
3.9K
10 GND NC 7
V-DRIVER
VSUB

7
11 NC 6
Ai1002(3)
-9V 12 VP GND 5 VSUB
13 VRG
Ai325CA 4 VΦ1
RG VΦ1
33
14 NC VΦ2 3 VΦ2
APPLICATION CIRCUIT

HΦ1 15 HΦ1 VΦ3 2 VΦ3

33
HΦ2 16 HΦ2 VΦ4 1 VΦ4
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 Ai325CA

PACKAGE DIMENSION (16 PIN PLASTIC-DIP)

B UNIT = mm
6.1

1.The center of the effective image

area relative to “ B ” and “ B’ ”is
(H, V) = (6.1, 5.7)±0.15mm.
0.4

2. The rotation angle of the effective

H=
DE .5

image area relative to H and V is

PT
R0
2.5

V ±1.5。
5.7

0.3

H
: GLASS LID
R

B
0.32±0.10

1.40±0.3

12.20±0.1 11.40±0.1

8.9±0.10
3。 9.70±0.10
3.08±0.3
1.57

5。
0.64 5。
R0.3
3.55±0.25
1.27±0.10

10.73±0.05

0.30±0.10 0.25
0.46±0.10
1.27±0.05 11.43±0.3
1.27X7=8.89±0.10
11.80±0.05