Bharath N E-Mail: Contact Number: +919666652634: Dorstar

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Bharath N

E-mail: [email protected]
Contact Number: +919666652634

 Experience summary:

 3 years of Experience in Physical Design Implementation.


 PnR Implementation of block level design in 12nm(SMIC) and 6nm(TSMC)
technologies.
 Supported to IREM to check Grid resistance violations to the instances and summar-
ize the block level IREM runs data.

 Technical Skills:

 Comprehensive knowledge of physical design implementation, Physical Design


Strategies-sanity checks, Floor planning, Power planning, Placement, CTS, Routing
and timing closure.
 Flow of Netlist to GDS-II
 Understand different issues during flow like Congestion, timing issues and DRC
violations.
 Applying different methodologies and optimization techniques to meet design
constraints.
 Good knowledge on STA.
 Expertise in using Innovus and Prime-Time tools and familiar with RedHawk-SC
tool.
 Highly adaptable to all kinds of environment.
 Always on the look to improve skills and grow with the organization

 Work Experience

 May 2021 to till now: Physical Design Engineer in FOLIK TECHNOLOGIES


(ENFLAME - ODC)

 PROJECT DETAILS

 Project 1: Dorstar

 Responsibility: Responsible to run all aspects of physical design like P&R, STA, and
ECO Timing Closure
 Inst Count: 750k with 22 macros
 Role: Implementing Block from Floor-Plan to PnR STA
 Tools: Innovus, RedHawk-SC and Prime Time.
 Frequency: 1.4 GHZ
 Challenges during PNR:
o Worked on the block level PNR
o Feedback to RTL team for Half cycle paths
o Floorplan experiments to meet timing and congestion requirements at place
stage.
o Path grouping for critical modules.
 ECO:
o • Implemented ECOs for timing closure of block.
o Skewing the clock path to fixed setup timing critical paths.
o Timing fixes by swapping, size cell and adding buffer on long net length.
o Fixed Dynamic IR violations and DRC spacing issues.
 IREM:
o Check the resistance issues from bump power grid to cell power pin. If any
cells have larger Short path resistance will report to block owner to fix the vi-
olations early at place stage.
o Gather the block level StaticIR/DynamicIR/PowerEM/SignalEM violations and
publish it to team.

 Project 2: Scorpio

 Responsibility: Responsible to run all aspects of physical design like P&R, STA, and
ECO Timing Closure
 Inst Count: 460k with 32 macros and 170k with 4 macros
 Role: Implementing Block from floor plan to PnR. STA
 Tools: Innovus, RedHawk-SC and Prime Time
 Frequency: 1.4 GHZ
 Challenges during PNR:
o Worked on the block level PNR
o Multiple Floorplan experiments to better congestion and timing at place stage
o Path grouping for high timing paths
 ECO:
o Timing fixes by swapping, size cell and adding buffer on long net length.
o Swapping SVT to LVT for setup hold conflict paths.
o IR violations and DRC spacing issues.

 Project 3: Venus
 Responsibility: Responsible to one block pnr implementation and closure the timing.
 Inst Count: 600k with 16 macros.
 Role: Implementing Block from floor plan to PnR. STA
 Tools: Innovus, and Prime Time
 Frequency: 1.5 GHZ
 Challenges during PNR:
o Worked on the block level PNR.
o Tried different floorplans to achieved lower congestion and best timing.
 ECO:
o Timing fixes by swapping, size cell and adding buffer on long net length.
o Skewing the start point of the flop to fixed critical setup timing violations.
o Fixed IR drop violations and signalEM violations.
DECLARATION:

I hereby declare that the above information furnished is correct to the best of my
knowledge.

Place: Hyderabad. Bharath N

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