ES9069 Datasheet v0.1.3

ES9069
32-bit High performance 2 Channel DAC with MQA

Analog Reinvented Product Datasheet
The ESS Sabre® ES9069 is a high performance 32-bit, 2-channel audio D/A converter. It has been designed for professional applications (mixer
consoles, digital audio workstations), audiophile-grade portable applications (headphones, network streamers and digital music players), and
consumer applications (DACs and A/V receivers). The ES9069 uses the newest ESS patented HyperStream® IV Dual DAC™ technology, and
advanced SABRE HiFi® architecture.
The ES9069 delivers a performance level that will satisfy the most demanding audiophile and pro-audio enthusiast.
The ES9069 SABRE® DAC improves on previous designs to include:

• MQA Hardware renderer to reveal the original master resolution
• TDM & SPI support for more options in connectively
• Lower power consumption than previous generations which includes the Hyperstream IV DAC modulator
• New hardware mode (HW) programmability alleviates I2C/SPI programming for ease of use.
The versatile audio input port accepts PCM (TDM/LJ/RJ/I2S), DSD, DoP, S/PDIF and MQA renderer formats. The integrated SABRE DAC supports
up to 32-bit 768kHz PCM & DSD1024 audio data via master/slave interface in synchronous and asynchronous sampling modes.
ES9069 is a licensed and standard-compliant MQA native hardware renderer reducing the decoding demand on the application processor.
The integrated digital regulator reduces PCB area and BOM cost.
FEATURE DESCRIPTION
Patented 32-bit HyperStream® IV Architecture

32-bit audio DAC with very high dynamic range & ultra-low distortion
and Dual DAC™Technology
+130dB Dynamic Range (DNR)
High performance 32-bit audio DAC with unprecedented dynamic range and ultra-low
-126dB Total Harmonic Distortion (THD)
distortion.
-120dB Total Harmonic Distortion + Noise
Supports synchronous and asynchronous sampling modes
(THD+N)
s
Automatic ‘stream lock’ to unfold decoded MQA stream
Hardware MQA Renderer Easily paired with software MQA core decoder
Eliminates the need for complicated DAC filter tuning
Integrated low noise digital regulator Reduced BOM cost and improved DNR
32-bit processing Distortion free signal processing
Supports master/slave PCM (TDM, I2S, LJ, RJ), DSD, DoP, S/PDIF and MQA renderer
Versatile digital audio input port
formats.
Customizable digital filter characteristics 8 preset filters and a programmable filter for custom sound signature
FIR & IIR filter bypass To allow full customer ability to add custom filters
APPLICATIONS
• Professional digital audio workstations and mixer consoles
• Digital music players, Portable multimedia players
• Consumer and Audiophile DAC headphone amplifiers and A/V receivers
• Bluetooth stereo devices & Networked Audio
• DJ Equipment
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM 1
VERSION 0.1.3
ES9069 Datasheet
Table of Contents
Table of Contents ............................................................................................................................................................................................................. 2
List of Figures ................................................................................................................................................................................................................... 4
List of Tables .................................................................................................................................................................................................................... 5
Functional Block Diagram ................................................................................................................................................................................................. 6
ES9069 Pinout .................................................................................................................................................................................................................. 7
32 QFN Pin Descriptions .................................................................................................................................................................................................. 8
Feature List ....................................................................................................................................................................................................................... 9
Configuration Modes......................................................................................................................................................................................................... 9
Software Mode ............................................................................................................................................................................................................. 9
I2C ............................................................................................................................................................................................................................ 9
SPI ........................................................................................................................................................................................................................... 9
Hardware Mode .......................................................................................................................................................................................................... 10
Design Information ................................................................................................................................................................................................. 11
Muting .................................................................................................................................................................................................................... 11
Hardware Mode Pin Configurations ....................................................................................................................................................................... 12
Recommended Hardware Mode Setup Sequence ................................................................................................................................................ 14
Digital Features............................................................................................................................................................................................................... 15
Digital Signal Path ...................................................................................................................................................................................................... 15
Volume Control ...................................................................................................................................................................................................... 15
Automute................................................................................................................................................................................................................ 16
8x FIR Interpolation Oversampling Filter ............................................................................................................................................................... 16
THD Compensation ............................................................................................................................................................................................... 17
IIR Filter ................................................................................................................................................................................................................. 17
GPIO Software Configuration ..................................................................................................................................................................................... 18
GPIO Configuration Descriptions ............................................................................................................................................................................... 18
GPIO Pin Descriptions ............................................................................................................................................................................................... 20
Audio Input Formats ................................................................................................................................................................................................... 21
PCM (I2S, LJ, RJ) .................................................................................................................................................................................................. 22
TDM (Time-division multiplexing)........................................................................................................................................................................... 23
DSD ....................................................................................................................................................................................................................... 26
S/PDIF ................................................................................................................................................................................................................... 26
Digital Filters............................................................................................................................................................................................................... 29
Customizable programmable FIR filters................................................................................................................................................................. 30
PCM Filter Properties (44.1kHz Sampling) ............................................................................................................................................................ 31
PCM Filter Latency ................................................................................................................................................................................................ 32
PCM Filter Frequency Response ........................................................................................................................................................................... 33
PCM Filter Impulse Response ............................................................................................................................................................................... 37
MQA Renderer ........................................................................................................................................................................................................... 41
VERSION 0.1.3
ES9069 Datasheet
Analog Features ............................................................................................................................................................................................................. 41

Calibration Resistor .................................................................................................................................................................................................... 41
Absolute Maximum Ratings ............................................................................................................................................................................................ 42
I/O Electrical Characteristics ........................................................................................................................................................................................... 42
Recommended Operating Conditions............................................................................................................................................................................. 43
Power Consumption ................................................................................................................................................................................................... 44
Performance ............................................................................................................................................................................................................... 46
Timing Requirements...................................................................................................................................................................................................... 47
I2C Slave Interface Timing .......................................................................................................................................................................................... 47
SPI Slave Interface ..................................................................................................................................................................................................... 48
Audio Interface Timing ............................................................................................................................................................................................... 49
Register Overview .......................................................................................................................................................................................................... 50
Read/Write Register Addresses ............................................................................................................................................................................. 50
Read-only Register Addresses .............................................................................................................................................................................. 50
Multi-Byte Registers ............................................................................................................................................................................................... 50
Register Map .................................................................................................................................................................................................................. 51
Register Listings ............................................................................................................................................................................................................. 53
System Registers ....................................................................................................................................................................................................... 53
GPIO Registers .......................................................................................................................................................................................................... 60
DAC Registers............................................................................................................................................................................................................ 70
Readback Registers ................................................................................................................................................................................................... 82
ES9069 Reference Schematics ...................................................................................................................................................................................... 86
Typical Application Schematic .................................................................................................................................................................................... 86
Hardware (HW) mode ................................................................................................................................................................................................ 87
Software (SW) mode .................................................................................................................................................................................................. 88
Recommended Output Stage ..................................................................................................................................................................................... 89
Internal Pad Circuitry ...................................................................................................................................................................................................... 90
32 QFN Package Dimensions ........................................................................................................................................................................................ 92
32 QFN Top View Marking ............................................................................................................................................................................................. 93
Reflow Process Considerations ...................................................................................................................................................................................... 94
Temperature Controlled ............................................................................................................................................................................................. 94
Manual........................................................................................................................................................................................................................ 94
RPC-1 Classification reflow profile ............................................................................................................................................................................. 95
RPC-2 Pb-Free Process – Classification Temperatures (Tc)..................................................................................................................................... 95
Ordering Information ....................................................................................................................................................................................................... 96
Revision History .............................................................................................................................................................................................................. 96
3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
VERSION 0.1.3
ES9069 Datasheet
List of Figures
Figure 1 - ES9069 Block Diagram .................................................................................................................................................................................... 6
Figure 2 - Hardware mode pin configurations................................................................................................................................................................. 11
Figure 3 - Hardware mode startup sequence ................................................................................................................................................................. 14
Figure 4 – THD Compensation Block Diagram............................................................................................................................................................... 17
Figure 5 – LJ & I2S Input for 16bit and 32bit word depths.............................................................................................................................................. 22
Figure 6 – TDM128 mode ............................................................................................................................................................................................... 23
Figure 7 – TDM256 mode ............................................................................................................................................................................................... 23
Figure 8 – TDM512 mode ............................................................................................................................................................................................... 23
Figure 9 – TDM1024 mode ............................................................................................................................................................................................. 23
Figure 10 – TDM connection of several ES9069 devices in parallel .............................................................................................................................. 24
Figure 11 – TDM connection of several ES9069 devices in daisy chain mode .............................................................................................................. 25
Figure 12 – DSD format, 1bit stream .............................................................................................................................................................................. 26
Figure 13 – GPIO8 Digital I/O with Calibration Resistor ................................................................................................................................................. 41
Figure 14 – I2C Slave Control Interface Timing .............................................................................................................................................................. 47
Figure 15 – I2C single byte examples of read and write instructions with I2C ................................................................................................................. 47
Figure 16 – SPI single byte write .................................................................................................................................................................................... 48
Figure 17 – SPI single byte read .................................................................................................................................................................................... 48
Figure 18 – SPI multi-byte read ...................................................................................................................................................................................... 48
Figure 19 – Audio interface timing .................................................................................................................................................................................. 49
Figure 20. Typical ES9069 Software Mode Application Diagram ................................................................................................................................... 86
Figure 21 – Hardware (HW) mode reference schematic for ES9069Q .......................................................................................................................... 87
Figure 22 – Software mode reference schematic for ES9069Q ..................................................................................................................................... 88
Figure 23 – ES9069Q 32 QFN package dimensions ...................................................................................................................................................... 92
Figure 24 – ES9069Q Marking ....................................................................................................................................................................................... 93
Figure 25 – IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)......................................................................................................................... 94
VERSION 0.1.3
ES9069 Datasheet
List of Tables
Table 1 - Mode pin configuration options.......................................................................................................................................................................... 9
Table 2 – I2C addresses .................................................................................................................................................................................................. 9
Table 3 - SPI commands .................................................................................................................................................................................................. 9
Table 4 – GPIO function in Hardware mode ................................................................................................................................................................... 10
Table 5 – Mute Control for HW mode configuration ....................................................................................................................................................... 11
Table 6 - Hardware mode pin configurations table ......................................................................................................................................................... 13
Table 7 – Automute Configuration .................................................................................................................................................................................. 16
Table 8 - GPIO Configuration function............................................................................................................................................................................ 18
Table 9 - GPIO Hardware & Software mode pin descriptions ........................................................................................................................................ 20
Table 10 - PCM pin connections..................................................................................................................................................................................... 22
Table 11 - TDM pin connections ..................................................................................................................................................................................... 23
Table 12 - DSD pin connections ..................................................................................................................................................................................... 26
Table 13 - S/PDIF pin connections ................................................................................................................................................................................. 26
Table 14 – S/PDIF Channel Status – Consumer Configuration ...................................................................................................................................... 27
Table 15 – S/PDIF Channel Status – Professional Configuration .................................................................................................................................. 28
Table 16 – FIR digital filter properties ............................................................................................................................................................................. 29
Table 17 – PCM Filter Properties ................................................................................................................................................................................... 32
Table 18 - Latency of Pre-Programmed Digital Filters .................................................................................................................................................... 32
Table 19 – PCM Filter Frequency Response.................................................................................................................................................................. 36
Table 20 – PCM Filter Impulse Response ...................................................................................................................................................................... 40
Table 21 – Absolute Maximum Ratings .......................................................................................................................................................................... 42
Table 22 – I/O Electrical Characteristics......................................................................................................................................................................... 42
Table 23 – Recommended Operating Conditions ........................................................................................................................................................... 43
Table 24 – Power Consumption with test conditions 1 ................................................................................................................................................... 44
Table 25 – Power Consumption with test conditions 2 ................................................................................................................................................... 45
Table 26 – Performance Data......................................................................................................................................................................................... 46
Table 27 – I2C slave interface timing definitions ............................................................................................................................................................ 47
Table 28 – Internal Pad Circuitry .................................................................................................................................................................................... 91
Table 29 – RPC-1 Classification reflow profile ............................................................................................................................................................... 95
Table 30 – RPC-2 Pb free classification temperatures ................................................................................................................................................... 95
VERSION 0.1.3
ES9069 Datasheet
Functional Block Diagram
VCCA DVDD AVDD
DVDD LDO
MCLK CLOCK
NETWORK
CHIP_EN CLK DETECT / POR
MISO/ADDR0/MUTE_CTRL
I2C/SPI
SS/ADDR1/HW2
SLAVE
DIGITAL
SCLK/SCL/HW1
MOSI/SDA/HW0 CORE
MODE Hardware
RT1 Interface AVCC_DAC1
GPIO1
GPIO2
GPIO3 Hyperstream® IV DAC1
HiFi Sabre® DAC DAC1B
GPIO4
VOLUME CONTROL
DIGITAL FILTERS,
GPIO5
MODULATORS
GPIO6 AGND_DAC1
GPIO7 S/PDIF
GPIO8 DIGITAL AGND_DAC2
AUDIO
DATA_CLK PORT
DATA1 (I2S, DSD,
Hyperstream® IV DAC2
DoP,TDM) HiFi Sabre® DAC DAC2B
DATA2
MQA Renderer
AVDD_DAC2
DGND GND
Figure 1 - ES9069 Block Diagram
VERSION 0.1.3
ES9069 Datasheet
ES9069 Pinout
32 QFN Pinout
Figure 2. ES9069Q Pinout*

(Top View)
*Note: ES9069Q has an exposed pad (pin 33) that should be connected to ground.
VERSION 0.1.3
ES9069 Datasheet
32 QFN Pin Descriptions

Pin Name Pin Type Reset State Pin Description
1 AVCC_DAC1 Power Power 3.3V DAC analog output stage reference supply for the Channel 1
2 DAC1B AO Ground Differential Negative Output for Channel 1
3 DAC1 AO Ground Differential Positive Output for Channel 1
4 AGND_DAC1 Ground Ground DAC analog output stage ground for Channel 1
5 AGND_DAC2 Ground Ground DAC analog output stage ground for Channel 2
6 DAC2B AO Ground Differential Negative Output for Channel 2
7 DAC2 AO Ground Differential Positive Output for Channel 2
8 AVCC_DAC2 Power Power 3.3V DAC analog output stage reference supply for the Channel 2
9 DVDD Power Power Digital Supply, 1.2V (Internally Supplied)
10 AVDD Power Power 3.3V digital regulator supply
11 GND Ground Ground Device Ground
12 DATA_CLK I/O HiZ Serial Data Clock pin
13 DATA1 I/O HiZ Serial DATA1 pin
14 DATA2 I HiZ Serial DATA2 pin
15 SCLK/SCL/HW1 I HiZ Serial Clock for SCLK (SPI), SCL (I2C), also HW1 controlled by MODE pin
16 MOSI/SDA/HW0 I HiZ Serial communication for SPI/I2C & HW0 interface pin, controlled by MODE
17 RT1 I HiZ Reserved. Must be connected to GND for normal operation.
18 CHIP_EN I HiZ Active-high Chip Enable
19 SS/ADDR1/HW2 I HiZ Serial communication for SPI/I2C & HW2 interface pin, controlled by MODE
pin
20 MISO/ADDR0/ I HiZ Serial communication for SPI/I2C & MUTE_CTRL interface pin, controlled by
MUTE_CTRL MODE pin
21 GPIO1 I/O Ground Automute Output, General I/O w/extended functions
22 GPIO2 I/O Ground Lock Status Output, General I/O w/extended functions
23 GPIO3 I/O HiZ General I/O w/extended functions
28 GPIO8 I/O Res. to Ground** Calibration Resistor & General I/O w/extended functions
29 MODE I HiZ I2C/SPI Control selection or HW mode
30 GND Ground Ground Device Ground
31 VCCA Power Power Analog Supply, 3.3V
32 MCLK I HiZ Oscillator input
33 External PAD - - External pad, connect to GND
* Note: AO = Analog Output, I = Digital Input, I/O = Digital Input/Output,
**Note: Res. to Ground = Resistor to ground, see calibration resistor section for more information.
VERSION 0.1.3
ES9069 Datasheet
Feature List
The ES9069 is a SABRE® 2 channel high performance digital to analog converter (DAC) with features and performance including the new
Hyperstream IV modulator that produces a very high-performance device that is well suited for a variety of applications.
In addition to improved performance, the new ES9069 SABRE DAC now supports the TDM audio interface, SPI (or I2C) control interface and
hardware modes for simplifying device configuration.
TDM, I2S including LJ & RJ, DSD & DoP audio interfaces are supported.
Sample rates up to 768kHz (@ 64 FS) with PCM data with 8 selectable digital filters to choose from and a programmable filter for custom sound
signatures. DSD rates up to DSD1024 (512 x 44.1kHz) are also supported.
ES9069 is a licensed and standard-compliant MQA native hardware renderer reducing the decoding demand on the application processor to help
recreate the natural sound of the recording.
Configuration Modes
The ES9069 has 4 control programming modes. They are controlled by the state of the MODE (pin 29):
MODE PIN Configuration

0 I2C interface
Pull Low HW control mode (see Hardware Mode Table)
Pull High HW control mode (see Hardware Mode Table)
1 SPI interface
Table 1 - Mode pin configuration options
Software Mode
ES9069 supports I2C or SPI serial communication to configure registers. There are two types of registers, read/write and read-only registers.
I2C
o MODE (Pin 29) – GND
o Connect per I2C standard I2C Address ADDR1 ADDR0
0x90 GND GND
▪ SDA (Pin 16)
▪ SCL (Pin 15) 0x92 GND AVDD
▪ ADDR0 (Pin 20) 0x94 AVDD GND
▪ ADDR1 (Pin 19) 0x96 AVDD AVDD
Table 2 – I2C addresses
SPI
o Mode (Pin 29) – AVDD
o Connect per SPI standard
▪ MOSI (Pin 16) SPI command First byte
▪ SCLK (Pin 15) Write 3
▪ SS (Pin 19) Read 1
▪ MISO (Pin 20) Table 3 - SPI commands
VERSION 0.1.3
ES9069 Datasheet
Hardware Mode
The ES9069 has 31 pre-configured modes that can be set with external pin configuration. These modes configure the DAC for different input serial
data rates and set the DAC muting. All Synchronous hardware modes have Automatic FS (sample rate) detection enabled.
These modes are set with pins:
• MODE (Pin 29)
• HW0 (Pin 16)
• HW1 (Pin 15)
• HW2 (Pin 19)
• MUTE_CTRL (Pin 20)
Each hardware mode pin has 4 states:

• 0 – Pin directly connected to GND
• 1 – Pin directly connected to AVDD
• Pull 0 – Pin pulled to GND through 47kΩ resistor
• Pull 1 – Pin pulled to AVDD through 47kΩ resistor
In Hardware mode, most GPIOs have specific functions:
GPIO # Input/Output HW mode function

GPIO1 Output Automute Status (AND of both channels)
GPIO2 Output SRC Lock (Reg 249[2] register for readback)
GPIO3 Output Daisy chain mode data output
GPIO4 Input S/PDIF input in HW mode (HW modes 16-18)
DoP HW enable
• 1’b0: DoP disabled
GPIO5 Input • 1’b1: DoP enabled
Note: Requires a PCM (I2S/LJ/TDM) HW mode to be selected
FIR filter selection
• 1’b0: minimum phase (register default)
GPIO6 Input • 1’b1: Linear phase fast roll-off
Note: See section on Digital filter for more information
GPIO7 Ground Must be connected to Ground in HW mode (Pin 27)
GPIO8 Input CAL_RES input (Calibration Resistor) See calibration section for more information.
Table 4 – GPIO function in Hardware mode
VERSION 0.1.3
ES9069 Datasheet
Design Information
Each hardware mode pin can be configured with either a pull-up or pull-down resistor. Therefore, it is important that the pin is configured to allow for
the desired hardware modes. Some guidelines include the following:
• The HW0 and HW1 pins never require a pull up or pull-down resistor.
Pull-up Pull-down
AVDD or GPIO
47k
HW2/ HW2/
MODE MODE
47k
GND or GPIO
Figure 2 - Hardware mode pin configurations
Muting
MUTE_CTRL (Pin 20) is used to control the muting of the output and enabling of the Automute feature while in Hardware Mode:
HW MUTE Control (Pin 20) Condition

0 Output Muted, No Automute
1 Output Unmuted, No Automute
Pull 0 Output Muted, Automute Enabled
Pull 1 Output Unmuted, Automute Enabled
Table 5 – Mute Control for HW mode configuration
VERSION 0.1.3
ES9069 Datasheet
Hardware Mode Pin Configurations

The following table shows the available hardware modes for the ES9069. All Synchronous Hardware (HW) modes have Automatic FS detection
enabled with FS & BCK being detected. See Register 3[7] for more details.
BCK/
FS (kHz) BCK (MHz) MCLK (MHz) MODE HW2 HW1 HW0
HW Mode Channel
I2S Master Mode
(MCLK=128*FS) ≤
0 MCLK / 128 MCLK / 2 32 Pull 0 0 0 0
49.152
(MCLK=256*FS) ≤
1 MCLK / 256 MCLK / 4 32 Pull 0 0 0 1
49.152
(MCLK=512*FS) ≤
2 MCLK / 512 MCLK / 8 32 Pull 0 0 1 0
49.152
(MCLK=1024*FS) ≤
3 MCLK / 1024 MCLK / 16 32 Pull 0 0 1 1
49.152
LJ Master Mode
(MCLK=128*FS) ≤
4 MCLK / 128 MCLK / 2 32 Pull 0 Pull 0 0 0
49.152
(MCLK=256*FS) ≤
49.152
(MCLK=512*FS) ≤
49.152
(MCLK=1024*FS) ≤
49.152
I2S Slave SYNC, MCLK/1, Auto FS detection enabled
64*FS ≤ MCLK ≤
8 Auto (8 < FS < 768) 64FS 32 Pull 0 Pull 1 0 0
49.152
128*FS ≤ MCLK ≤
49.152
256*FS ≤ MCLK ≤
49.152
I2S Slave SYNC, Auto Clock Gear (128FS), Auto FS detection enabled
64*FS ≤ MCLK ≤
49.152
LJ Slave SYNC, MCLK/1, Auto FS detection enabled
64*FS ≤ MCLK ≤
12 Auto (8 < FS < 384) 64FS 32 Pull 0 1 0 0
49.152
128*FS ≤ MCLK ≤
13 Auto (8 < FS < 192) 64FS 32 Pull 0 1 0 1
49.152
256*FS ≤ MCLK ≤
14 Auto (8 < FS < 96) 64FS 32 Pull 0 1 1 0
49.152
LJ Slave SYNC, Auto Clock Gear (128FS), Auto FS detection enabled
64*FS ≤ MCLK ≤
15 Auto (8 < FS < 384) 64FS 32 Pull 0 1 1 1
49.152
S/PDIF, DoP, or I2S Slave ASYNC, Auto Detect Input Format, MCLK/1
VERSION 0.1.3
ES9069 Datasheet
16 Auto (8 < FS < 384) 64FS 130FS < MCLK < 50 32 Pull 1 0 0 0
S/PDIF, DoP, or I2S Slave ASYNC, Auto Detect Input Format*, MCLK/2
S/PDIF, DoP, or I2S Slave ASYNC, Auto Detect Input Format*, MCLK/4
I2S Slave ASYNC, Auto Clock Gear (>130FS), Auto Detect Input Format*
LJ Slave ASYNC, MCLK/1, Auto Detect Input Format*
20 Auto (8 < FS < 384) 64FS 130FS < MCLK < 50 32 Pull 1 Pull 0 0 0
LJ Slave ASYNC, Auto Clock Gear (>130FS), Auto Detect Input Stream*
DSD Slave SYNC, MCLK/1
4*FS ≤ MCLK ≤
24 DSD64 - DSD512 2FS -- Pull 1 Pull 1 0 0
45.1584
DSD Slave SYNC, Auto Clock Gear (4FS)
4*FS ≤ MCLK ≤
25 DSD64 - DSD512 2FS -- Pull 1 Pull 1 0 1
45.1584
DSD Slave ASYNC, MCLK/1
26 DSD64 - DSD512 2FS 6*FS ≤ MCLK ≤ 50 -- Pull 1 Pull 1 1 0
DSD Slave ASYNC, Auto Clock Gear (>6FS)
27 DSD64 - DSD512 2FS 6*FS ≤ MCLK ≤ 50 -- Pull 1 Pull 1 1 1
TDM LJ Slave SYNC, Auto Detect CH num.
Auto (64FS, 128FS,
64FS ≤ MCLK ≤
28* Auto (8 < FS < 768) 256FS, 512FS, 32 Pull 1 1 0 0
49.152
1024FS)
Auto (128FS, 256FS, 128FS ≤ MCLK ≤
29* Auto (8 < FS < 384) 32 Pull 1 1 0 1
512FS, 1024FS) 49.152
30* Auto (8 < FS < 192) 32 Pull 1 1 1 0
1024FS) 49.152
31* Auto (8 < FS < 192) 32 Pull 1 1 1 1
1024FS) 49.152
Table 6 - Hardware mode pin configurations table
Note:
* Mode 28 = Channel Slots 1,2, Mode 29 = Channel slots 3,4, Mode 30 = Channel slots 5,6, Mode 31 = Channel slots 7,8
* ACG is auto clock gearing is enabled, it will normally gear the clock down to 128*FS, unless 64*FS is required, or 2*DSDCLK in DSD modes.
* To enable DoP in HW mode, GPIO5 pin must be high
* The MQA renderer is not available in HW mode.
VERSION 0.1.3
ES9069 Datasheet
Recommended Hardware Mode Setup Sequence

The hardware mode setup sequence is shown below with all hardware pins being defined after CHIP_EN is asserted.
Note: It is recommended that MUTE_CTRL is set low until the HW mode is finalized and after CHIP_EN is asserted, then asserted last.
CHIP_EN
HW0
HW1
HW2
1ms
MUTE_CTRL
OUT
Figure 3 - Hardware mode startup sequence
VERSION 0.1.3
ES9069 Datasheet
Digital Features
See Recommended Operating Conditions for additional information.
Digital Signal Path
SABRE DAC DIGITAL PATH

DSD FIR with
DSD/DoP
VOL
8x interpolation Noise Shaped

IIR
Oversampling Filter THD SRC Modulators
TDM/I2S Filter
Comp (NSMOD)
MQA
PCM Volume Bypass
Control & 2x FIR 4x FIR
Automute
SPDIF
Bypass Bypass
(ASYNC)
Volume Control
This volume control is intended for use during audio playback. Each channel can be digitally attenuated from 0dB to –127.5dB in 0.5dB steps. When
a new volume level is set, the attenuation circuit will ramp softly to the new level at a rate specified in the DAC VOL UP RATE, DAC VOL DOWN
RATE and DAC VOL DOWN RATE FAST registers.
Muting the DAC output can be accomplished by DAC_MUTE_CHx from Register 86.
Channel volumes, by default, are updated as soon as the volume registers are written. However, the volume control can be updated for both
channels together by using VOLUME_HOLD.
Volume Control Registers

• Register 74: VOLUME CH1
• Register 75: VOLUME CH2
• Register 82: DAC VOL UP RATE
• Register 83: DAC VOL DOWN RATE
• Register 84: DAC VOL DOWN RATE FAST
• Register 89[4]: VOLUME_HOLD
Volume control is available for PCM (I2S, LJ, RJ, TDM), DoP (DSD over PCM), and DSD. There is separate control for each channel.
VERSION 0.1.3
ES9069 Datasheet
Automute
In HW mode automute is controlled by the state of the MUTE_CTRL pin (pin 20), the pin must be “pull 0” or “pull 1” to enable automute.
In SW mode automute is enabled by default and can be disabled on each channel individually through Register 123 AUTOMUTE ENABLE.
The thresholds that engage and disengage automute can be configured through the AUTOMUTE LEVEL and AUTOMUTE OFF LEVEL registers.
If automute is enabled, it will be triggered when any one of the following conditions are met:
Mode Detection Condition Time

Data is lower than automute_level for longer than the 2^18
PCM automute_time.
Date is at a constant DC level for longer than automute_time. (𝑎𝑢𝑡𝑜𝑚𝑢𝑡𝑒_𝑡𝑖𝑚𝑒 ∗ 𝐹𝑆)
DSD data contains a DSD mute pattern (equal number of 1’s and
0’s in 8 consecutive bits of data), for longer than automute_time. 2^18
DoP/DSD
DSD data contains all 1’s or 0’s in 8 consecutive bits of data, for (𝑎𝑢𝑡𝑜𝑚𝑢𝑡𝑒_𝑡𝑖𝑚𝑒 ∗ 𝐹𝑆)
longer than automute_time.
Table 7 – Automute Configuration

Automute Configuration Registers
• Register 123: AUTOMUTE ENABLE
• Register 124-125: AUTOMUTE TIME
• Register 126-127: AUTOMUTE LEVEL
• Register 128-129: AUTOMUTE OFF LEVEL
• Register 62[7]: DISABLE_DSD_DC – Disables the DSD automute condition for 8 consecutive bits of 1'b1 or 1'b0.
• Register 62[6]: DISABLE_DSD_MUTE – Disables the DSD automute condition for the DSD Mute pattern.
• Register 62[0]: DISABLE_PCM_DC – Disables the PCM automute condition for a constant DC level.
8x FIR Interpolation Oversampling Filter

Selection of the 8x interpolation filter is chosen from 8 pre-programmed filter shapes (Register 88[2:0] FILTER_SHAPE) or custom sound signatures
can be programmed.
For more information on filters see Digital filters section
VERSION 0.1.3
ES9069 Datasheet
THD Compensation
The ES9069 has built-in THD compensation to help compensate for system second and third harmonics that may be present on the output signal.
The compensation is controlled through 4 individual signed 16-bit coefficients in the THD Compensation Coefficient Registers.
The following equation displays how the second and third harmonics are affected by the C2 and C3 values:
Figure 4 – THD Compensation Block Diagram
THD Compensation is always enabled but if register values are zero, it will be bypassed. For best results, the chosen compensation coefficients
should be tuned for each system/device in-situ.
THD Compensation Coefficient Registers

• Registers 94-93: THD_C2_CH2, THD Compensation for C2 for Channel 2
• Registers 92-91: THD_C2_CH1, THD Compensation for C2 for Channel 1
• Registers 110-109: THD_C3_CH2, THD Compensation C3 for Channel 2
• Registers 108-107: THD_C3_CH2, THD Compensation C3 for Channel 1
Note: Coefficients are 16-bit signed values
IIR Filter
The IIR filter in the ES9069 can be bypassed by using Register 90: DAC PATH CONFIG bit [2] IIR_bypass.
The bandwidth of the filter is controlled Register 89[2:0] IIR_BW.
VERSION 0.1.3
ES9069 Datasheet
GPIO Software Configuration

Each GPIO from 1 to 8 has 14 configurable modes (mode 8 is reserved). The table below shows the available configurations. See GPIO pin
descriptions for Hardware and Software mode setups.
GPIO#_CFG Function Input / Output GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
4’d0 Analog Shutdown Output Shutdown
4’d1 Output 0 Output Output 0
4’d2 Output 1 Output Output 1
4’d3 Clocks Output CLKEN_1FS CLK_BCK CLK_DAC CLK_IDAC CLKEN_1FS CLK_BCK CLK_DAC CLK_IDAC
4’d4 Interrupt Output OR of all interrupts
4’d5 Mute Input Mute all channels
4’d6 System Mode Control Input See System mode control section
4’d7 SRC lock status Output src_locked flag
4’d8 -- -- Reserved
4’d9 PWM1 signal Output PWM1 signal
4’d12 Minimum volume1 Output vol_min flag
4’d13 Automute status1 Output dac_automute flag
4’d14 Soft ramp done1 Output dac_ss_ramp flag
4’d15 MQA authentication Output mqa_auth_true flag
Table 8 - GPIO Configuration function
1 Can be bitwise ANDed, ORed, or a specific channel output; based on the values of registers 46-47[6:0]. See corresponding registers.
GPIO Configuration Descriptions

Analog shutdown
Output shutdown
Output 0
Outputs a constant 1’b0.
Output 1
Outputs a constant 1’b1.
Clocks
• GPIO1: CLKEN_1FS (1*FS pulse clock)
• GPIO2: CLK_BCK
• GPIO3: CLK_DAC (SYS_CLK)
• GPIO4: CLK_IDAC (128*FS clock)
• GPIO5: CLKEN_1FS
• GPIO6: CLK_BCK
• GPIO7: CLK_DAC
• GPIO8: CLK_IDAC
Interrupt
Bitwise OR of all masked interrupts. See registers 10-21 for interrupt descriptions.
VERSION 0.1.3
ES9069 Datasheet
Mute
Mute all DAC channels.
System mode control

Works with register 46-47[15] GPIO_DAC_MODE.
When any GPIOx_CFG = 4’d6 (system mode control):
• 1’b0: Disable datapath when GPIOx input is 1’b1

• 1’b1: Enable datapath when GPIO input is 1'b1
When GPIOx input is 1’b0, system mode is determined by register 0[1] DAC_MODE_REG.
SRC Lock status

SRC (Sample rate converter) lock status output. If the device is in a synchronous mode, output will be 1’b0.
PWM Signals
Outputs 1 of 3 PWM signals. Frequency and duty cycle on the PWM signals can be calculated with the following equations:
𝑆𝑌𝑆_𝐶𝐿𝐾
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 [𝐻𝑧] =
𝑃𝑊𝑀#_𝐹𝑅𝐸𝑄 + 1
𝑃𝑊𝑀#_𝐶𝑂𝑈𝑁𝑇
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 [%] = ( ) × 100
𝑃𝑊𝑀#_𝐹𝑅𝐸𝑄 + 1
Each PWM signal can be controlled by the following registers:
• PWM1: register 48 PWM1_COUNT, register 49-50 PWM1_FREQ

Minimum Volume
vol_min flag output. Is high during normal and abnormal mute conditions.
Normal mute conditions: register mute, gpio mute, override mute, and automute.
Abnormal mute conditions: lock of SRC lock, and bck_ws_fail.
Register 46-47[1] GPIO_AND_VOL_MIN sets the GPIO output to be the logical AND of all channel vol_min flags. Overrides GPIO_OR_VOL_MIN.
Register 46-47[4] GPIO_OR_VOL_MIN sets the GPIO output to be the logical OR of all channel vol_min flags.
Register 46-47[6] GPIO_SEL will output the flag of a specific channel if GPIO_OR_VOL_MIN and GPIO_AND_VOL_MIN are both 1’b0.
Automute status
dac_automute flag output. High when automute is active.
Register 46-47[0] GPIO_AND_AUTOMUTE sets the GPIO output to be the logical AND of all channel dac_automute flags.
Overrides GPIO_OR_AUTOMUTE.
Register 46-47[3] GPIO_OR_AUTOMUTE sets the GPIO output to be the logical OR of all channel dac_automute flags.
VERSION 0.1.3
ES9069 Datasheet
Register 46-47[6] GPIO_SEL will output the flag of a specific channel if GPIO_OR_ AUTOMUTE and GPIO_AND_ AUTOMUTE are both 1’b0.
Soft ramp done

dac_ss_ramp flag output. Is high when the ES9069 is not in the process of ramping either up or down.
Register 46-47[2] GPIO_AND_SS_RAMP sets the GPIO output to be the logical AND of all channel dac_ss_ramp flags.
Overrides GPIO_OR_SS_RAMP.
Register 46-47[5] GPIO_OR_SS_RAMP sets the GPIO output to be the logical OR of all channel dac_ss_ramp flags.
Register 46-47[6] GPIO_SEL will output the flag of a specific channel if GPIO_OR_ SS_RAMP and GPIO_AND_SS_RAMP are both 1’b0.
MQA authentication
MQA_Auth_True flag output. Will be 1’b1 when the MQA decoder detects an authorized MQA stream.
GPIO Pin Descriptions
GPIOx Hardware Mode Software mode

GPIO1 Automute status. Regular GPIO
GPIO2 Lock Status Regular GPIO
GPIO3 is connected to the Reg60[5] TDM_DAISY_CHAIN logic. When
TDM_DAISY_CHAIN = 1'b1, GPIO3 can ONLY be used as an output for daisy
chain delayed data line.
GPIO3 No hardware mode connection If TDM_DAISY_CHAIN = 1'b0, GPIO3 can then be used as a GPIO.
GPIO4 S/PDIF input pin, requires HW modes 16-18. Regular GPIO.
GPIO5 DoP input enable, requires HW modes 0-23, 28-31 Regular GPIO.
FIR filter selection,
1’b0: Filter 0, Minimum phase (register default),
1’b1: Filter 2, Linear phase fast roll-off.
GPIO6 Requires HW modes 0-23, 28-31. Regular GPIO.
GPIO7 Connect to Ground* Regular GPIO.
GPIO8 CAL_RES (calibration resistor) CAL_RES, disable to use as regular GPIO.
Table 9 - GPIO Hardware & Software mode pin descriptions
Note*: In Hardware mode GPIO7 needs to be connected to Ground.
VERSION 0.1.3
ES9069 Datasheet
Audio Input Formats

The ES9069 supports multiple serial input data formats. Input format is selected either through Hardware mode or software mode (Register 1: SYS
MODE CONFIG).
The ES9069 can automatically determine the input data format by enabling Register 57[0] AUTO_INPUT_SEL. When using AUTO_INPUT_SEL data
must be provided on the DATA2 pin, to properly decode the input format. The input data format can also be selected using Reg[2:1] INPUT_SEL.
For Hardware mode see hardware mode for inputs.
This formats include:
• PCM
o Slave and master mode in 16, 24, and 32 bit widths
o I2S, Left Justified (LJ) and Right Justified (RJ)
o TDM up to TDM1024 mode with 32 slots including daisy chain mode
o Sample rates up to 768kHz (64fs mode)
o Channel Remapping & Invert
• DoP (DSD Over PCM)
o Slave and master mode
o Sample rates up to DoP512 (24bit, 1.4112MHz PCM)
• Native DSD
o Slave and master mode
o Sample rates from DSD64 (2.8224Mbits/sec, 64 x 44.1kHz) to DSD1024
• S/PDIF
o Selectable input pin and payload information
o S/PDIF input in HW mode (HW modes 16-18) using GPIO4.
VERSION 0.1.3
ES9069 Datasheet
PCM (I2S, LJ, RJ)

Data is organized as 2 channels per data line. Any channel on any data line can be mapped to any DAC through the TDM_CHx_CONFIG
channel mapping Registers 64-65. Data is latched on the positive edge of BCLK.
PCM Pin Connections (default configuration)

Pin Name Function Description
DATA_CLK I2S BCLK I2S clock (Bit Clock), Master or Slave
DATA1 I2S WS I2S WS (Word Select/Frame Select), Master or Slave
DATA2 I2S DATA I2S DATA
Table 10 - PCM pin connections
Figure 5 – LJ & I2S Input for 16bit and 32bit word depths
Note: RJ is supported but only in software mode.
VERSION 0.1.3
ES9069 Datasheet
TDM (Time-division multiplexing)

The ES9069 supports time-division multiplexing (TDM) format, allowing more than 2 channels (or slots) to be transmitted on each data line,
up to a maximum of 32 channels per data line. Typical formats are TDM128 (4chx32bit), TDM256 (8chx32bit), TDM512 (16chx32bit) and
TDM1024 (32chx32bit). In this mode, Registers 64[4:0] & 65[4:0] PCM_CH#_SLOT_SEL can be used to internally map any TDM slot
(channel) to either DAC. Data is latched on the positive edge of BCLK.
TDM Pin Connections (default configuration)

DATA_CLK TDM BCLK TDM clock, Master or Slave
DATA1 TDM WS TDM WS (Word Select/Frame Select), Master or Slave
DATA2 TDM DATA TDM DATA
Table 11 - TDM pin connections
Figure 6 – TDM128 mode
VERSION 0.1.3
ES9069 Datasheet
Multiple ES9069 devices in parallel in TDM mode
In TDM modes, several ES9069 can be used in parallel to increase the number of channels. Each ES9069 can be configured in HW or SW mode to
output its data to different slots on the TDM DATA line.
Note: In hardware modes, only Left Justified TDM formats are supported. In software mode, the user can configure it to be I2S TDM format.
Figure 10 – TDM connection of several ES9069 devices in parallel
Applicable Registers
• Register 60[7] TDM_LJ_MODE set to 1'b1.

• Register 60[6] TDM_VALID_EDGE set to 1'b1.
• Register 59[4:0] TDM_CH_NUM or using Register 57[7] AUTO_CH_DETECT: Sets the # of TDM slots / frame.
• Register 64[4:0] & Register 65[4:0] PCM_CH#_SLOT_SEL: Sets the TDM slots for each device.
VERSION 0.1.3
ES9069 Datasheet
Daisy Chain multiple ES9069 devices in TDM mode
Figure 11 – TDM connection of several ES9069 devices in daisy chain mode
Applicable Registers (Daisy chain mode is only available in software mode)
• Register 60[7] TDM_LJ_MODE set to 1’b1

• Register 60[6] TDM_VALID_EDGE set to 1’b1
• Register 60[5] TDM_DAISY_CHAIN: Enables Daisy Chain mode
o GPIO3 will output data pass-through on DATA2 line delayed by 1 BCLK
• Register 59[4:0] TDM_CH_NUM or using Register 57[7] AUTO_CH_DETECT: Sets the # of TDM slots / frame.
• Register 61[4:0] TDM_DATA_LATCH_ADJ: Sets the position of the start bit within each TDM slot.
o Value corresponds to the position of the device in the chain (zero-indexed).
• Register 64[4:0] & Register 65[4:0] PCM_CH#_SLOT_SEL: Sets the TDM slots for each device.
o Note: the first chip in the chain is required to be in the final 2 slots.
Note: An application note for Daisy chain mode and TDM in general will be available shortly from ESS FAEs or your local distributor.
VERSION 0.1.3
ES9069 Datasheet
DSD
In DSD mode, there is a single DSD clock line, and each channel of data is an additional DSD data line. There is no internal channel
mapping for DSD input, DSD data input to DATA1 is sent to Ch1, DSD data input to DATA2 is sent to Ch2.
DSD Pin Connections (default configuration)

DATA_CLK DSD Clock DSD clock input
DATA1 DSD CH1 DSD DATA channel 1
DATA2 DSD CH2 DSD DATA channel 2
Table 12 - DSD pin connections
Automute is available for DSD once a constant DC level (8 1’s or 8 0’s in a row) is detected. The ES9069 will then automute to the proper
DSD mute pattern.
DCLK
DSD1 D1D2D3D4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
1bit DSD2 D1D2D3D4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
DSD FORMAT
Figure 12 – DSD format, 1bit stream
The ES9069 can accept DS data line for multiple pins. The pins can be chosen using:
• Register 64[7:5] DSD_CH1_SOURCE, DATA1 (default)
• Register 65[7:5] DSD_CH2_SOURCE, DATA2 (default)
S/PDIF
S/PDIF input
Pin Name Description
GPIO4 HW modes 16-18 S/PDIF stream input
GPIOx or DATA1/2 Input selection from SPDIF_SEL for software mode
Table 13 - S/PDIF pin connections
S/PDIF is transmitted over a single signal line using dual phase encoded data, which allows for clock extraction from the data signal line.
The ES9069 has an integrated S/PDIF decoder that can be accessed in either Asynchronous Hardware or Software modes.
• For Hardware mode, the S/PDIF input is on GPIO4 using HW modes 16-18.
o S/PDIF input stream must be disconnected in order to use other input formats.
• For Software mode, the applicable registers are:
o Register 89[7:4] SPDIF_SEL
▪ Selects the S/PDIF input pin
▪ If a GPIO is selected, GPIO pins also require the GPIOx_SDB input to be enabled.
o Register 136[4:0] SPDIF_DATA_SEL
▪ Selects the byte of the S/PDIF payload in register 251[7:0] SPDIF_DATA_READ
o Register 251 SPDIF_DATA_READ
▪ Readback the payload, 24 bytes total
VERSION 0.1.3
ES9069 Datasheet
For decoding the S/PDIF payload see Channel Status Table below:
SPDIF CHANNEL STATUS – Consumer configuration

Address
Offset [7] [6] [5] [4] [3] [2] [1] [0]
(Bytes)
0 Reserved Reserved 0:2Channel Reserved 0: No-Preemph 0: CopyRight 0: Audio 0: Consumer
1:4Channel 1: Preemph 1: Non-CopyRight 1: Data 1: Professional
1 Category Code
0x00: General
0x01: Laser-Optical
0x02: D/D Converter
0x03: Magnetic
0x04: Digital Broadcast
0x05: Musical Instrument
0x06: Present A/D Converter
0x08: Solid State Memory
0x16: Future A/D Converter
0x19: DVD
0x40: Experimental
2 Channel Number Source Number
0x0: Don’t Care 0x0: Don’t Care
0x1: A (Left) 0x1: 1
0x2: B (Right) 0x2: 2
0x3: C 0x3: 3
0x4: D 0x4: 4
0x5: E 0x5: 5
0x6: F 0x6: 6
0x7: G 0x7: G
0x8: H 0x8: 8
0x9: I 0x9: 9
0xA: J 0xA: 10
0xB: K 0xB: 11
0xC: L 0xC: 12
0xD: M 0xD: 13
0xE: N 0xE: 14
0xF: O 0xF: 15
3 Reserved Reserved Clock Accuracy Sample Frequency
0x0: Level 2 1000ppm 0x0: 44.1k
0x1: Level 1 50ppm 0x2: 48k
0x2: Level 3 variable pitch shifted 0x3: 32k
0x4: 22.05k
0x6: 24k
0x8: 88.2k
0xA: 96k
0xC: 176.4k
0xE: 192k
4 Reserved Reserved Reserved Reserved Word Length: Word Field Size
If Word Field Size=0 |If Word Field Size = 1 0: Max 20bits
000=Not indicated |000=Not indicated 1: Max 24bits
100 = 23bits |100 = 19bits
010 = 22bits |010 = 18bits
110 = 21bits |110 = 17bits
001 = 20bits |001 = 16bits
101 = 24bits |101 = 20bits
5-23 Reserved
Table 14 – S/PDIF Channel Status – Consumer Configuration
VERSION 0.1.3
ES9069 Datasheet
SPDIF CHANNEL STATUS – Professional configuration

Address
Offset [7] [6] [5] [4] [3] [2] [1] [0]
(Bytes)
0 sampling frequency: lock: emphasis: 0: Audio 0: Consumer
00: not indicated (or see byte 4) 0: locked 000: Emphasis not indicated 1: Non-audio 1: Professional
10: 48 kHz 1: unlocked 001: No emphasis
01: 44.1 kHz 011: CD-type emphasis
11: 32 kHz 111: J-17 emphasis
1 User bit management: Channel mode:
0000: no indication 0000: not indicated (default to 2 ch)
1000: 192-bit block as channel status 1000: 2 channel
0100: As defined in AES18 0100: 1 channel (monophonic)
1100: user-defined 1100: primary / secondary
0010: As in IEC60958-3 (consumer) 0010: stereo
1010: reserved for user applications
0110: reserved for user applications
1110: SCDSR (see byte 3 for ID)
0001: SCDSR (stereo left)
1001: SCDSR (stereo right)
1111: Multichannel (see byte 3 for ID)
2 alignment level: Source Word Length: Use of aux sample word:
00: not indicated If max = 20bits |If max = 24bits 000: not defined, audio max 20 bits
10: –20dB FS 000=Not indicated |000=Not indicated 100: used for main audio, max 24 bits
01: –18.06dB FS 100 = 23bits |100 = 19bits 010: used for coord, audio max 20 bits
010 = 22bits |010 = 18bits 110: reserved
110 = 21bits |110 = 17bits
001 = 20bits |001 = 16bits
101 = 24bits |101 = 20bits
3 Channel identification:
if bit 7 = 0 then channel number is 1 plus the numeric value of bits 0-6 (bit reversed).
if bit 7 = 1 then bits 4–6 define a multichannel mode and bits 0–3 (bit reversed) give the channel number within that mode.
4 fs scaling: Sample frequency (fs): Reserved DARS (Digital audio reference signal):
0: no scaling 0000: not indicated 00: not a DARS
1: apply factor of 0001: 24kHz 01: DARS grade 2 (10ppm)
1 / 1.001 to value 0010: 96kHz 10: DARS grade 1 (1ppm)
1001: 22.05kHz 11: Reserved
1010: 88.2kHz
1011: 176.4kHz
0011: 192kHz
1111: User defined
5 Reserved
6-9 alphanumerical channel origin: four-character label using 7-bit ASCII with no parity. Bits 55, 63, 71, 79 = 0.
10-13 alphanumerical channel destination: four-character label using 7-bit ASCII with no parity. Bits 87, 95, 103, 111 = 0.
14-17 local sample address code: 32-bit binary number representing the sample count of the first sample of the channel status block.
18-21 time of day code: 32-bit binary number representing time of source encoding in samples since midnight
22 reliability flags
0: data in byte range is reliable
1: data in byte range is unreliable
23 CRCC
00000000: not implemented
X: error check code for bits 0–183
Table 15 – S/PDIF Channel Status – Professional Configuration
VERSION 0.1.3
ES9069 Datasheet
Digital Filters
The ES9069 has 8 pre-programmed digital filters and a programmable filter to allow for custom filter responses. The latency for each filter reduces
(scales) with increasing sample rates. (See Register 88[2:0] FILTER_SHAPE for configuration).
The pre-programmed filters are:

• Minimum phase (default)
• Linear phase apodizing fast roll-off
• Linear phase fast roll-off
• Linear phase slow roll-off low-ripple
• Linear phase slow roll-off
• Minimum phase fast roll-off
• Minimum phase slow roll-off
• Minimum phase slow roll-off low dispersion
# Filter Description
1 Minimum phase (default) Version 2 of minimum phase fast roll-off (#6) with less ripple and more image rejection
2 Linear phase apodizing fast roll-off Full image rejection by fs/2 to avoid any aliasing, with smooth roll-off starting before 20k.
3 Linear phase fast roll-off Sabre legacy filter, optimized for image rejection @ 0.55 fs
4 Linear phase fast roll-off low-ripple Sabre legacy filter, optimized for in-band ripple
5 Linear phase slow roll-off Sabre legacy filter, optimized for lower latency, but symmetric impulse response
6 Minimum phase fast roll-off Low latency, minimal pre ringing and low passband ripple, image rejection @ 0.55fs
7 Minimum phase slow roll-off Lowest latency at the cost of image rejection
Provides a nice balance of the low latency of minimum phase filters and the low dispersion
Minimum phase fast roll-off low
8 of linear phase filters. Minimal pre-ringing is added to achieve the low dispersion in the
dispersion
audio band.
Table 16 – FIR digital filter properties
Note on Minimum phase filters:
Minimum phase filters are asymmetric filters that work to minimize the pre-echo of the filter, while still maintaining an excellent frequency response
and they peak earlier that linear phase filters, resulting in a lower group delay. Minimum phase filters usually feature zero cycles of pre-echo, which
can result in improved audio quality.
VERSION 0.1.3
ES9069 Datasheet
Customizable programmable FIR filters
The ES9069 has an 8x interpolation oversampling FIR filter in the ES9069 data path that is programmable. It is a combination of 2 filters, a 4x FIR
filter and a 2x FIR filter.
These filters can be bypassed using Register 90[1] BYPASS_FIR4X & 90[0] BYPASS_FIR2X, which will source data to the IIR filter. It is
recommended to use an 8xFS input if the bypass is used. For example, an external signal at 44.1kHz can be oversampled externally to 8 x 44.1kHz
= 352.8kHz and then applied to the serial decoder in either I2S, LJ or RJ format.
The addresses for the two filters are:

• 2X FIR, Address 0x00 – 0x7F(0 – 127), 128 coefficients
• 4X FIR, Address 0x80 – 0x9F(128 – 159), 32 coefficients
To program the filters, the following registers are required:
• Register 135: PROGRAM RAM CONTROL

o [1] PROG_COEFF_WE
▪ Enables writing to the programmable coefficient RAM
o [0] PROG_COEFF_EN
▪ Use the built-in filters or custom filter
• Register 137: PROGRAM RAM ADDRESS
o [7] PROG_COEFF_STAGE
▪ Choose which FIR stage to write to, either 4x or 2x
o [6:0] PROG_COEFF_ADDR
▪ Selects the coefficient address when writing custom coefficients for the interpolation oversampling filter.
• Register 140-138: PROGRAM RAM DATA
o 24-bit signed filter coefficient to the address defined by PROG_COEFF_ADDR
• Register 248-246: PROG COEFF OUT READ
o Used to readback the programmed coefficients
An example sequence of programming a coefficient into RAM:
Write Reg 137 0 // RAM Address = 0, 2x stage

Write Reg 138 32 // Set data bits [7:0] of 24 bit coefficient
Write Reg 139 255 // Set data bits [15:8]
Write Reg 140 255 // Set data bits [23:16]
Write Reg 135 0x02 // Write 24 bit coefficient to RAM
Write Reg 135 0x00 // Reset write enable
Repeat for all 4x and 2x coefficient addresses.
An application note the programming sequence and sample code will be available shortly from your ESS distributor or field application engineer
(FAE).
VERSION 0.1.3
ES9069 Datasheet
PCM Filter Properties (44.1kHz Sampling)
Minimum phase
Parameter Conditions MIN TYP MAX UNIT
Pass band –3dB 0.49 x fs Hz
Stop band -96dB 0.55 x fs Hz
Group Delay 3.30/fs 9.38/fs s
Flatness (ripple) 0.0004 dB
Linear phase apodizing fast roll-off

Group Delay 33.18/fs s
Linear phase fast roll-off

Linear phase fast roll-off low ripple

Linear phase slow roll-off

Minimum phase fast roll-off

VERSION 0.1.3
ES9069 Datasheet
Minimum phase slow roll-off

Minimum phase slow roll-off low dispersion

Table 17 – PCM Filter Properties
PCM Filter Latency
The following table shows the simulated latency of each filter at 44.1kHz sampling rate. Measurements were taken from the external impulse
response. The extra sample delay for encoding the data accounts for external processing time to serialize the data stream. Latency delay will reduce
(scale) with sampling rate.
Delay(us) @
Digital Filter
fs=44.1kHz
Minimum phase (default) 174us
Linear phase apodizing fast roll-off 840us
Linear phase fast roll-off 854us
Linear phase fast roll-off low ripple 808us
Linear phase slow roll-off 229us
Minimum phase fast roll-off 174us
Minimum phase slow roll-off 152us
Minimum phase slow roll-off low dispersion 310us
Table 18 - Latency of Pre-Programmed Digital Filters
VERSION 0.1.3
ES9069 Datasheet
PCM Filter Frequency Response

The following frequency responses were obtained from software simulations of these filters. Simulation sample rate is 44.1kHz.
Filter Frequency Response
Minimum phase
Linear phase apodizing fast

roll-off
VERSION 0.1.3
ES9069 Datasheet
Linear phase fast roll-off low

ripple
VERSION 0.1.3
ES9069 Datasheet
VERSION 0.1.3
ES9069 Datasheet

low dispersion
Table 19 – PCM Filter Frequency Response
VERSION 0.1.3
ES9069 Datasheet
PCM Filter Impulse Response

The following impulse responses were obtained from software simulations of these filters. Measurements were taken from the external impulse
response. The extra sample delay for encoding the data accounts for external processing time to serialize the data stream.
Simulation sample rate is 44.1kHz.
Filter Impulse Response
Minimum phase
Linear phase apodizing fast

roll-off
VERSION 0.1.3
ES9069 Datasheet
Linear phase fast roll-off low

ripple
VERSION 0.1.3
ES9069 Datasheet
VERSION 0.1.3
ES9069 Datasheet

low dispersion
Table 20 – PCM Filter Impulse Response
VERSION 0.1.3
ES9069 Datasheet
MQA Renderer
The ES9069 is a licensed MQA hardware renderer.
The MQA renderer is only available in software configuration mode and is accessible with Register 141: MQA Config.
Analog Features
Calibration Resistor
The ES9069 features an integrated resistor that is used for calibration of DAC voltage supplies AVCC_DAC1 and AVCC_DAC2. This calibration is
required to maintain output level from device to device with the process varying DAC output impedance. This calibration resistor is accessible
through GPIO8, it is enabled by default. The ~47.5kΩ calibration resistor can be disabled with Register 34[6], CAL_RES_ENB, removing the
pulldown from interacting with the GPIO8 functionality.
To calibrate the AVCC_DAC1 and AVCC_DAC2 voltage supplies, a circuit is required to generate the voltage supply based on the resistor value.
This can be done by generating a constant current and using that current through the internal calibration resistor to generate the reference voltage.
This voltage is then buffered for the AVCC_DACx supply.
By default, the switch is closed (CAL_RES_ENB = 1’b0) , Register 42[7] = 1’b0 (input disabled), and Register 41[7] GPIO8_OE = 1’b0 (tristated).
Figure 13 – GPIO8 Digital I/O with Calibration Resistor
VERSION 0.1.3
ES9069 Datasheet
Absolute Maximum Ratings

PARAMETER RATING
Positive Supply Voltage
• AVCC_DAC1 • +3.7V with respect to Ground
• AVCC_DAC2 • +3.7V with respect to Ground
• AVDD • +3.7V with respect to Ground
• VCCA • +3.7V with respect to Ground
• DVDD • +1.4V with respect to Ground
Storage temperature –65C to +150C

Operating Junction Temperature +125C
Voltage range for digital input pins –0.3V to AVDD(nom)+0.3V
ESD Protection
Human Body Model (HBM) 2kV
Charge Device Model (CDM) 500V
Table 21 – Absolute Maximum Ratings

WARNING: Stresses beyond those listed under here may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any
other conditions beyond those indicated under Recommended Operating Conditions is not implied.
WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.
I/O Electrical Characteristics

PARAMETER SYMBOL MINIMUM MAXIMUM UNIT
High-level input voltage VIH (AVDD / 2) + 0.4 V
Low-level input voltage VIL 0.4 V
High-level output voltage VOH AVDD – 0.2 V
Low-level output voltage VOL 0.2 V
Table 22 – I/O Electrical Characteristics
VERSION 0.1.3
ES9069 Datasheet
Recommended Operating Conditions

There are the recommended operating conditions for the ES9069
PARAMETER SYMBOL CONDITIONS
Operating temperature TA –20C to +85C
AVCC_DAC1 3.3V
AVCC_DAC2 3.3V
AVDD 3.3V
VCCA 3.3V
DVDD Internal 1.2V
Table 23 – Recommended Operating Conditions
Note: Supplied power is required to be within +/- 5% of the recommended condition.
VERSION 0.1.3
ES9069 Datasheet
Power Consumption
Power numbers are given when the device is in slave mode.
Test Conditions 1 (unless otherwise noted)

TA = 25oC, AVCC_R = AVCC_L = VCCA = AVDD = +3.3V, DVDD= +1.2V, fs = 48kHz, DAC enabled, 1kHz sine full scale
Parameter Min Typ Max Unit
Hardware Mode: 11 (Slave mode with ACG (128*FS), MCLK = 49.152MHz)

AVCC_DAC1 5.9 mA
AVCC_DAC2 5.9 mA
VCCA 0.4 mA
AVDD 4.0 mA
Power Consumption 54 mW
Hardware Mode: 2 (Master mode with MCLK = 24.576MHz, FS=MCLK/512)

AVCC_DAC1 6.8 mA
AVCC_DAC2 6.8 mA
VCCA 0.5 mA
AVDD 9.4 mA
Hardware Mode: 1 (Master mode with MCLK = 12.288MHz, FS=MCLK/256)

AVCC_DAC1 6.2 mA
AVCC_DAC2 6.2 mA
VCCA 0.22 mA
AVDD 6.9 mA
Table 24 – Power Consumption with test conditions 1
VERSION 0.1.3
ES9069 Datasheet

TA = 25oC, AVCC_R = AVCC_L = VCCA = AVDD = +3.3V, DVDD= +1.2V, fs = 48kHz, DAC enabled, streaming zeros, automute enabled
Hardware Mode: 11 (Slave mode with ACG (128*FS), MCLK = 49.152MHz)

AVCC_DAC1 0.8 mA
AVCC_DAC2 0.8 mA
VCCA 0.4 mA
AVDD 2.4 mA
Hardware Mode: 2 (MCLK = 24.576MHz)

AVCC_DAC1 1.5 mA
AVCC_DAC2 1.5 mA
VCCA 0.44 mA
AVDD 6.9 mA
Hardware Mode: 1 (MCLK = 12.288MHz)

AVCC_DAC1 1.0 mA
AVCC_DAC2 1.0 mA
VCCA 0.2 mA
AVDD 5.0 mA
Table 25 – Power Consumption with test conditions 2
VERSION 0.1.3
ES9069 Datasheet
Performance
TA = 25oC, AVCC_DAC1 = AVCC_DAC2 = VCCA = AVDD = +3.3V, DVDD= +1.2V, fs = 48kHz, HW mode (I2S Master Mode)
Note: Performance numbers were measured using the ESS ES9069 evaluation board v1.0, 10Vrms = 0dBFS input.

Resolution 32 Bit
Max MCLK frequency 50 MHz
THD+N Ratio / THD Ratio

@ fs=48kHz 0dBFS, BW=20Hz-20kHz -120/-126 dB
(differential)
(differential)
(differential)
(differential)
DNR (A-weighted)
130 dB
(2 Channel mode – Single Channel diff)
-60dBFS
DNR (A-weighted)
133 dB
(Mono mode – 2 channel sum diff)
Voltage output amplitude Full-scale out 0.886*AVCC_DACx Vpp
Voltage output offset Bipolar zero out AVCC/2 V
Current output amplitude Full-scale out 1000 x 0.886*AVCC_DAC / RDAC mApp
Current output offsets Bipolar zero out 1000 x (AVCC/2 – Vg) / RDAC mA
Output impedance
RDAC 390 ±15% Ω
(Per + or – pin of each DAC output)
Table 26 – Performance Data
VERSION 0.1.3
ES9069 Datasheet
Timing Requirements
I2C Slave Interface Timing
Start Start Stop Start

Figure 14 – I2C Slave Control Interface Timing
Parameter Symbol CLK Standard-Mode Fast-Mode Unit

Constraint
MIN MAX MIN MAX
SCL Clock Frequency fSCL < CLK/20 0 100 0 400 kHz
START condition hold time tHD;STA 4.0 - 0.6 - s
LOW period of SCL tLOW >10/CLK 4.7 - 1.3 - s
HIGH period of SCL (>10/CLK) tHIGH >10/CLK 4.0 - 0.6 - s
START condition setup time (repeat) tSU;STA 4.7 - 0.6 - s
SDA hold time from SCL falling
All except NACK read 0 0 s
- tHD;DAT - -
2/CLK 2/CLK s
- NACK read only
SDA setup time from SCL rising tSU;DAT 250 - 100 - ns

Rise time of SDA and SCL tr - 1000 300 ns
Fall time of SDA and SCL tf - 300 300 ns
STOP condition setup time tSU;STO 4 - 0.6 - s
Bus free time between transmissions tBUF 4.7 - 1.3 - s
Capacitive load for each bus line Cb - 400 - 400 pF
Table 27 – I2C slave interface timing definitions
Figure 15 – I2C single byte examples of read and write instructions with I2C
VERSION 0.1.3
ES9069 Datasheet
SPI Slave Interface

The 4-wire SPI data format is: Command (1 byte) + Address (1 byte) + Data
Figure 16 – SPI single byte write
Figure 17 – SPI single byte read
Figure 18 – SPI multi-byte read
VERSION 0.1.3
ES9069 Datasheet
Audio Interface Timing

Audio data on DATA1-2 are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time requirements relative to the rising
edge of DATA_CLK.
Figure 19 – Audio interface timing
Parameter Symbol Min Max Unit

DATA_CLK pulse width high tDCH 9.0 ns
DATA_CLK pulse width low tDCL 9.0 ns
DATA_CLK cycle time tDCY 20 ns
DATA_CLK duty cycle 45:55 55:45
DATAx set-up time to DATA_CLK rising edge tDS 4.1 ns
DATAx hold time to DATA_CLK rising edge tDH 2.0 ns
Table 9 - Audio interface timing definitions
VERSION 0.1.3
ES9069 Datasheet
Register Overview
The ES9069 contains read/write and read-only registers. A system clock must be present to access registers.
Multi-byte registers must be written from LSB to MSB. Data is latched when MSB is written.
Multi-byte registers must be read from LSB to MSB. Data is latched when LSB is read.
MSB is always stored in the highest register address.
Read/Write Register Addresses

Registers 0-142 (0x00 – 0x8E) are read/write registers
Read-only Register Addresses

Registers 224 – 251 (0xE0 – 0xFB) are read only registers.
Multi-Byte Registers
Multi-byte registers must be written from LSB to MSB. Data is latched when MSB is written.
MSB is always stored in the highest register address.
VERSION 0.1.3
ES9069 Datasheet
Register Map
Addr Addr
Register 7 6 5 4 3 2 1 0
(Hex) (Dec)
ENABLE_
0x00 0 SYSTEM CONFIG SOFT_RESET RESERVED DAC_MODE RESERVED
64FS_MODE
ENABLE_ ENABLE_SPDIF_ ENABLE_DOP_ ENABLE_DSD_ ENABLE_TDM_
0x01 1 SYS MODE CONFIG SYNC_MODE RESERVED
DAC_CLK DECODE DECODE DECODE DECODE
0x02 2 RESERVED RESERVED
AUTO_FS_ SELECT_
0x03 3 DAC CLOCK CONFIG SELECT_IDAC_NUM
DETECT IDAC_HALF
0x04 4 CLOCK CONFIG MASTER_BCK_DIV
AUTO_FS_
AUTO_
0x05 5 CLK GEAR SELECT RESERVED SEL_CLK_GEAR RESERVED RESERVED DETECT_BLOCK
CLK_GEAR
_64FS
0x06 - 6-
RESERVED RESERVED
0x09 9
AUTOMUTE_ AUTOMUTE_
BCK_WS_FAIL_ DOP_VALID_ SS_FULL_RAMP SS_FULL_RAMP VOL_MIN_ VOL_MIN_
0x0A 10 INTERUPT MASKP FLAG_CH2_ FLAG_CH1_
MASKP MASKP _CH2_MASKP _CH1_MASKP CH2_MASKP CH1_MASKP
MASKP MASKP
TDM_VALID_
0x0B 11 INTERUPT MASKP RESERVED INPUT_SELECT_OVERRIDE_MASKP RESERVED
EDGE_MASKP
0x0C - 12 -
RESERVED RESERVED
0x0E 14
AUTOMUTE_ AUTOMUTE_
0x0F 15 INTERUPT MASKN FLAG_CH2_ FLAG_CH1_
MASKN MASKN _CH2_MASKN _CH1_MASKN CH2_MASKN CH1_MASKN
MASKN MASKN
TDM_VALID_
0x10 16 INTERUPT MASKN RESERVED INPUT_SELECT_OVERRIDE_MASKN RESERVED
EDGE_MASKN
0x11 - 17 -
RESERVED RESERVED
0x13 19
AUTOMUTE_ AUTOMUTE_
0x14 20 INTERRUPT CLEAR FLAG_CH2_ FLAG_CH1_
CLEAR CLEAR _CH2_CLEAR _CH1_CLEAR CH2_CLEAR CH1_CLEAR
CLEAR CLEAR
TDM_VALID_
0x15 21 INTERRUPT CLEAR RESERVED INPUT_SELECT_OVERRIDE_CLEAR RESERVED
EDGE_CLEAR
0x16 - 22 -
RESERVED RESERVED
0x1C 28
0x1D 29 DPLL BW DPLL_BW RESERVED
0x1E - 30 -
RESERVED RESERVED
0x21 33
CH2_NSMOD_
0x22 34 DATA PATH CONFIG CAL_RES_ENB RESERVED
IN_SEL
CH2_PCM_ CH1_PCM_
0x23 35 PCM 4X GAIN RESERVED
4X_GAIN 4X_GAIN
0x25 37 GPIO1/2 CONFIG GPIO2_CFG GPIO1_CFG
0x29 41 GPIO OUTPUT ENABLE GPIO8_OE GPIO7_OE GPIO6_OE GPIO5_OE GPIO4_OE GPIO3_OE GPIO2_OE GPIO1_OE
0x2A 42 GPIO INPUT GPIO8_SDB GPIO7_SDB GPIO6_SDB GPIO5_SDB GPIO4_SDB GPIO3_SDB GPIO2_SDB GPIO1_SDB
0x2B 43 GPIO WK EN GPIO8_WK_EN GPIO7_WK_EN GPIO6_WK_EN GPIO5_WK_EN GPIO4_WK_EN GPIO3_WK_EN GPIO2_WK_EN GPIO1_WK_EN
0x2C 44 INVERT GPIO INVERT_GPIO8 INVERT_GPIO7 INVERT_GPIO6 INVERT_GPIO5 INVERT_GPIO4 INVERT_GPIO3 INVERT_GPIO2 INVERT_GPIO1
0x2D 45 GPIO READ GPIO8_READ GPIO7_READ GPIO6_READ GPIO5_READ GPIO4_READ GPIO3_READ GPIO2_READ GPIO1_READ
GPIO_OR_ GPIO_OR_ GPIO_OR_ GPIO_AND_ GPIO_AND_ GPIO_AND_
0x2E 46 GPIO OUTPUT LOGIC RESERVED GPIO_SEL
SS_RAMP VOL_MIN AUTOMUTE SS_RAMP VOL_MIN AUTOMUTE
GPIO_DAC_
0x2F 47 GPIO OUTPUT LOGIC RESERVED
MODE
0x30 48 PWM1 COUNT PWM1_COUNT
0x31 49 PWM1_FREQ
PWM1 FREQUENCY
0x32 50 PWM1_FREQ
0x34 52 PWM2_FREQ
PWM2 FREQUENCY
0x35 53 PWM2_FREQ
0x37 55 PWM3_FREQ
PWM3 FREQUENCY
0x38 56 PWM3_FREQ
ENABLE_
AUTO_ DSD_MASTER_ PCM_MASTER_ AUTO_
0x39 57 INPUT SELECTION DSD_FAULT_ RESERVED INPUT_SEL
CH_DETECT MODE MODE INPUT_SEL
DETECTION
MASTER_WS_ MASTER_ MASTER_
0x3A 58 MASTER ENCODER CONFIG TDM_RESYNC BCK_INV RESERVED MASTER_FRAME_LENGTH
PULSE_MODE WS_INVERT BCK_INVERT
0x3B 59 TDM CONFIG RESERVED TDM_CH_NUM
TDM_VALID_
0x3C 60 TDM CONFIG1 TDM_LJ_MODE RESERVED
EDGE
0x3D 61 TDM CONFIG2 RESERVED TDM_BIT_WIDTH TDM_DATA_LATCH_ADJ
DISABLE_ DISABLE_ ENABLE_WS_ ENABLE_BCK_ DISABLE_
0x3E 62 BCK/WS MONITOR CONFIG RESERVED
DSD_DC DSD_MUTE MONITOR MONITOR PCM_DC
0x3F 63 RESERVED RESERVED
0x40 64 CH1 SLOT CONFIG DSD_CH1_SOURCE PCM_CH1_SLOT_SEL
0x41 65 CH2 SLOT CONFIG DSD_CH2_SOURCE PCM_CH2_SLOT_SEL
0x42 - 66 -
RESERVED RESERVED
0x49 73
0x4A 74 VOLUME CH1 VOLUME_CH1
0x4B 75 VOLUME CH2 VOLUME_CH2
0x4C - 76 -
RESERVED RESERVED
0x51 81
0x52 82 DAC VOL UP RATE DAC_VOL_RATE_UP
VERSION 0.1.3
ES9069 Datasheet
0x53 83 DAC VOL DOWN RATE DAC_VOL_RATE_DOWN

0x54 84 DAC VOL DOWN RATE FAST DAC_VOL_RATE_FAST
0x56 86 DAC MUTE RESERVED DAC_MUTE_CH2 DAC_MUTE_CH1
DAC_INVERT_ DAC_INVERT_
0x57 87 DAC INVERT RESERVED
CH2 CH1
0x58 88 FILTER SHAPE RESERVED FILTER_SHAPE
0x59 89 IIR BANDWIDTH & S/PDIF SEL SPDIF_SEL VOLUME_HOLD IIR_BW
0x5A 90 DAC PATH CONFIG RESERVED BYPASS_IIR BYPASS_FIR4X BYPASS_FIR2X
0x5B 91 THD_C2_CH1
0x5C 92 THD_C2_CH1
THD C2
0x5D 93 THD_C2_CH2
0x5E 94 THD_C2_CH2
0x5F - 95 -
RESERVED RESERVED
0x6A 106
0x6B 107 THD_C3_CH1
0x6C 108 THD_C3_CH1
THD C3
0x6D 109 THD_C3_CH2
0x6E 110 THD_C3_CH2
0x6F - 111 -
RESERVED RESERVED
0x7A 122
AUTOMUTE_ AUTOMUTE_
0x7B 123 AUTOMUTE ENABLE RESERVED
EN_CH2 EN_CH1
0x7C 124 AUTOMUTE_TIME
AUTOMUTE TIME MUTE_RAMP_
0x7D 125 RESERVED AUTOMUTE_TIME
TO_GROUND
0x7E 126 AUTOMUTE_LEVEL
AUTOMUTE LEVEL
0x7F 127 AUTOMUTE_LEVEL
0x80 128 AUTOMUTE_OFF_LEVEL
AUTOMUTE OFF LEVEL
0x81 129 AUTOMUTE_OFF_LEVEL
0x82 130 SOFT RAMP CONFIG RESERVED SOFT_RAMP_TIME
0x83 - 131 -
RESERVED RESERVED
0x86 134
PROG_ PROG_
0x87 135 PROGRAM RAM CONTROL RESERVED
COEFF_WE COEFF_EN
0x88 136 S/PDIF READ CONTROL RESERVED SPDIF_DATA_SEL
PROG_COEFF_
0x89 137 PROGRAM RAM ADDRESS PROG_COEFF_ADDR
STAGE
0x8A 138 PROG_COEFF_IN
0x8B 139 PROGRAM RAM DATA PROG_COEFF_IN
0x8C 140 PROG_COEFF_IN
MQA_
0x8D 141 MQA CONFIG RESERVED RENDERING_
ENABLE
0x8E - 142 -
RESERVED RESERVED
0x91 145
0xE0 224 RESERVED RESERVED
0xE1 225 CHIP ID READ CHIP_ID
0xE2 - 226 -
RESERVED RESERVED
0xE4 228
BCK_WS_FAIL_ DOP_VALID_
0xE5 229 INTERRUPT STATES SS_FULL_RAMP_STATE AUTOMUTE_STATE VOL_MIN_STATE
STATE STATE
TDM_DATA_
0xE6 230 INTERRUPT STATES RESERVED INPUT_SELECT_OVERRIDE_STATE RESERVED
VALID_STATE
0xE7 - 231 -
RESERVED RESERVED
0xE9 233
BCK_WS_FAIL_ DOP_VALID_
0xEA 234 INTERRUPT SOURCES SS_FULL_RAMP_SOURCE AUTOMUTE_SOURCE VOL_MIN_SOURCE
SOURCE SOURCE
TDM_DATA_
0xEB 235 INTERRUPT SOURCES RESERVED INPUT_SELECT_OVERRIDE_SOURCE RESERVED
VALID_SOURCE
0xEC 236 -
RESERVED RESERVED
- 0xEE 238
0xEF 239 RATIO VALID READ RATIO_VALID RESERVED
0xF0 240 GPIO READ GPIO8_I_READ GPIO7_I_READ GPIO6_I_READ GPIO5_I_READ GPIO4_I_READ GPIO3_I_READ GPIO2_I_READ GPIO1_I_READ
0xF1 241 VOL MIN READ RESERVED VOL_MIN_CH2 VOL_MIN_CH1
AUTOMUTE_ AUTOMUTE_
0xF2 242 AUTOMUTE READ RESERVED
CH2 CH1
SS_RAMP_ SS_RAMP_
0xF3 243 SOFT RAMP UP READ RESERVED
UP_CH2 UP_CH1
SS_RAMP_ SS_RAMP_
0xF4 244 SOFT RAMP DOWN READ RESERVED
DOWN_CH2 DOWN_CH1
TDM_DATA_
0xF5 245 INPUT STREAM READBACK RESERVED SPDIF_VALID DOP_VALID INPUT_SELECT_OVERRIDE
VALID
0xF6 246 PROG_COEFF_OUT
0xF7 247 PROG COEFF OUT READ PROG_COEFF_OUT
0xF8 248 PROG_COEFF_OUT
0xF9 - 249 -
RESERVED RESERVED
0xFA 250
0xFB 251 S/PDIF DATA READ SPDIF_DATA_READ
VERSION 0.1.3
ES9069 Datasheet
Register Listings
Some reserved registers values might be asserted in default mode. This is normal and does not need to be changed.
System Registers
Register 0: SYSTEM CONFIG
Bits [7] [6] [5:2] [1] [0]
Default 1'b0 1'b0 4'd0 1'b0 1'b0
Bits Mnemonic Description

[7] SOFT_RESET Performs soft reset to digital core.
• 1'b0: Normal operation
• 1'b1: Reset digital core (all settings are set to default)
[6] ENABLE_64FS_MODE Enables 64FS mode to run the DAC interpolation path at 64FS.
• 1'b0: 64FS mode disabled (default)
• 1'b1: 64FS mode enabled
Note: This mode is used only for PCM high sample rates such as 768kHz
with a 49.152MHz or 384kHz with 24.576MHz clock
[5:2] RESERVED NA
[1] DAC_MODE Enables the analog section of the DAC.
• 1'b0: DAC disabled (default)
• 1'b1: DAC enabled
[0] RESERVED NA
Register 1: SYS MODE CONFIG

Bits [7] [6] [5:4] [3] [2] [1] [0]
Default 1'b1 1'b0 2'b11 1'b0 1'b0 1'b0 1'b1

[7] ENABLE_DAC_CLK Enables DAC interpolation path clock.
• 1'b0: Clock disabled
• 1'b1: Clock enabled (default)
[6] SYNC_MODE Enables SYNC mode.
• 1'b0: ASYNC mode enabled (default)
• 1'b1: SYNC mode enabled
[5:4] RESERVED NA
[3] ENABLE_SPDIF_DECODE Enables S/PDIF decoding.
• 1'b0: Disabled (default)
• 1'b1: Enabled
[2] ENABLE_DOP_DECODE Enables DoP decoding.
• 1'b1: Enabled
[1] ENABLE_DSD_DECODE Enables DSD decoding.
• 1'b1: Enabled
[0] ENABLE_TDM_DECODE Enables TDM decoding.
• 1'b0: Disabled
• 1'b1: Enabled (default)
VERSION 0.1.3
ES9069 Datasheet
Register 2: RESERVED
Register 3: DAC CLOCK CONFIG

Bits [7] [6] [5:0]
Default 1'b1 1'b0 6'd0

[7] AUTO_FS_DETECT Automatically determine optimal (MCLK/CLK_IDAC ratio) according to
detected FS.
• 1'b0: Disabled, use reg 3[5:0] SELECT_IDAC_NUM to set ratio.
• 1'b1: Enabled, overrides reg 3[5:0] SELECT_IDAC_NUM (default)
Note: Cannot be used in ASYNC mode.
[6] SELECT_IDAC_HALF • 1'b0: Divide by SELECT_IDAC_NUM + 1 (default)
• 1'b1: Divide by half of SELECT_IDAC_NUM + 1
Note: Can only produce half of an odd number divide
[5:0] SELECT_IDAC_NUM CLK_IDAC divider. Whole number divide value + 1 for CLK_IDAC
(SYS_CLK/divide_value).
• 6'd0: Whole number divide value + 1 = 1
Register 4: CLOCK CONFIG

Bits [7:0]
Default 8'd7

[7:0] MASTER_BCK_DIV Master mode clock divider. Whole number divide value + 1 for CLK_Master
(SYS_CLK/divide_value).
VERSION 0.1.3
ES9069 Datasheet
Register 5: CLK GEAR SELECT

Bits [7:6] [5:4] [3] [2] [1] [0]
Default 2'b00 2'd0 1'b0 1'b0 1'b0 1'b0

[7:6] RESERVED NA
[5:4] SEL_CLK_GEAR Clock Gearing
• 2'd0: SYS_CLK/1
• 2'd1: SYS_CLK/2
• 2'd2: SYS_CLK/4
• 2'd3: SYS_CLK/8
[3] RESERVED NA
[2] AUTO_CLK_GEAR • 1'b0: Disable automatic clock gearing. SYS_CLK = SEL_CLK_GEAR
• 1'b0: Disabled, SYS_CLK = SEL_CLK_GEAR. (default)
• 1'b1: Enabled, SYS_CLK will decrease by up to SEL_CLK_GEAR.
[1] RESERVED NA
[0] AUTO_FS_DETECT_BLOCK_64FS Block AUTO_FS_DETECT from transitioning to 64FS mode when the
detected CLK_DAC/CLK_IDAC ratio is 64.
• 1'b1: Enabled
Register 9-7: RESERVED
VERSION 0.1.3
ES9069 Datasheet
Register 11-10: INTERUPT MASKP

Bits [15:14] [13:12] [11] [10:8] [7] [6] [5] [4] [3] [2] [1] [0]
Default 2'b00 2'b00 1'b0 3'b000 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0

[15:14] RESERVED NA
[13:12] INPUT_SELECT_OVERRIDE_MASKP Masks negative to positive interrupt transitions.
• 2'b00: Ignore interrupt (default)
• 2'b11: Service interrupt if flag transitions from negative to positive
[11] TDM_VALID_EDGE_MASKP Masks negative to positive interrupt transitions.
[10:8] RESERVED NA
[7] BCK_WS_FAIL_MASKP Masks negative to positive interrupt transitions.
[6] DOP_VALID_MASKP Masks negative to positive interrupt transitions.
[5] SS_FULL_RAMP_CH2_MASKP Masks negative to positive interrupt transitions.
[4] SS_FULL_RAMP_CH1_MASKP Masks negative to positive interrupt transitions.
[3] AUTOMUTE_FLAG_CH2_MASKP Masks negative to positive interrupt transitions.
[2] AUTOMUTE_FLAG_CH1_MASKP Masks negative to positive interrupt transitions.
[1] VOL_MIN_CH2_MASKP Masks negative to positive interrupt transitions.
[0] VOL_MIN_CH1_MASKP Masks negative to positive interrupt transitions.
VERSION 0.1.3
ES9069 Datasheet
Register 16-15: INTERUPT MASKN

Bits [15:14] [13:12] [11] [10:8] [7] [6] [5] [4] [3] [2] [1] [0]

[15:14] RESERVED NA
[13:12] INPUT_SELECT_OVERRIDE_MASKN Masks positive to negative interrupt transitions.
• 2'b11: Service interrupt if flag transitions from positive to negative
[11] TDM_VALID_EDGE_MASKN Masks positive to negative interrupt transitions.
[10:8] RESERVED NA
[7] BCK_WS_FAIL_MASKN Masks positive to negative interrupt transitions.
[6] DOP_VALID_MASKN Masks positive to negative interrupt transitions.
• 1'b1: Service interrupt if toggled from positive to negative
[5] SS_FULL_RAMP_CH2_MASKN Masks positive to negative interrupt transitions.
[4] SS_FULL_RAMP_CH1_MASKN Masks positive to negative interrupt transitions.
[3] AUTOMUTE_FLAG_CH2_MASKN Masks positive to negative interrupt transitions.
[2] AUTOMUTE_FLAG_CH1_MASKN Masks positive to negative interrupt transitions.
[1] VOL_MIN_CH2_MASKN Masks positive to negative interrupt transitions.
[0] VOL_MIN_CH1_MASKN Masks positive to negative interrupt transitions.
VERSION 0.1.3
ES9069 Datasheet
Register 21-20: INTERRUPT CLEAR

Bits [15:14] [13:12] [11] [10:8] [7] [6] [5] [4] [3] [2] [1] [0]

[15:14] RESERVED NA
[13:12] INPUT_SELECT_OVERRIDE_CLEAR Toggle high-low to clear and re-arm interrupt.
[11] TDM_VALID_EDGE_CLEAR Toggle high-low to clear and re-arm interrupt.
[10:8] RESERVED NA
[7] BCK_WS_FAIL_CLEAR Toggle high-low to clear and re-arm interrupt.
[6] DOP_VALID_CLEAR Toggle high-low to clear and re-arm interrupt.
[5] SS_FULL_RAMP_CH2_CLEAR Toggle high-low to clear and re-arm interrupt.
[4] SS_FULL_RAMP_CH1_CLEAR Toggle high-low to clear and re-arm interrupt.
[3] AUTOMUTE_FLAG_CH2_CLEAR Toggle high-low to clear and re-arm interrupt.
[2] AUTOMUTE_FLAG_CH1_CLEAR Toggle high-low to clear and re-arm interrupt.
[1] VOL_MIN_CH2_CLEAR Toggle high-low to clear and re-arm interrupt.
[0] VOL_MIN_CH1_CLEAR Toggle high-low to clear and re-arm interrupt.
Register 29: DPLL BW

Bits [7:4] [3:0]
Default 4'd4 4'd0

[7:4] DPLL_BW Sets the bandwidth of the DPLL.
• 4'd0: Reserved
• 4'd1: Lowest Bandwidth
• 4'd15: Highest Bandwidth
[3:0] RESERVED NA
VERSION 0.1.3
ES9069 Datasheet
Register 34: DATA PATH CONFIG

Bits [7] [6] [5:0]
Default 1'b0 1'b0 6'b000000

[7] CH2_NSMOD_IN_SEL Selects ch2 nsmod input.
• 1'b0: Input from ch2 interpolation path (default)
• 1'b1: Input from ch1 interpolation path
[6] CAL_RES_ENB Selects the calibration resistor connection on GPIO8.
• 1'b0: DAC calibration resistor enabled (default)
• 1'b1: DAC calibration resistor disabled, normal GPIO
[5:0] RESERVED NA
Register 35: PCM 4X GAIN

Bits [7:2] [1] [0]
Default 6'd0 1'b0 1'b0

[7:2] RESERVED NA
[1] CH2_PCM_4X_GAIN Changes the gain on the CH2 interpolation path after the IIR.
• 1'b0: 1x gain
• 1'b1: 4x gain
Note: Not Available in DSD mode
[0] CH1_PCM_4X_GAIN Changes the gain on the CH1 interpolation path after the IIR.
• 1'b0: 1x gain
• 1'b1: 4x gain
Note: Not Available in DSD mode
VERSION 0.1.3
ES9069 Datasheet
GPIO Registers
Register 37: GPIO1/2 CONFIG
Bits [7:4] [3:0]
Default 4'd7 4'd13

[7:4] GPIO2_CFG Configures GPIO2
• 4'd0: Analog shutdown - shutdown
• 4'd1: Output 0 – output
• 4'd3: CLK_BCK – output
• 4'd4: Interrupt – output
• 4'd5: Mute all channels – input
• 4'd6: System mode control – input
• 4'd7: Lock status – output (default)
• 4'd8: Reserved
• 4'd9: PWM1 signal – output
• 4'd12: Minimum volume – output
• 4'd13: Automute status – output
• 4'd14: Soft ramp done – output
• 4'd15: MQA authentication – input
• 4'd0: Analog shutdown - shutdown
• 4'd3: CLKEN_1FS – output
• 4'd7: Lock status – output
• 4'd8: Reserved
• 4'd13: Automute status – output (default)
VERSION 0.1.3
ES9069 Datasheet

Bits [7:4] [3:0]
Default 4'd0 4'd0

• 4'd0: Analog shutdown - shutdown (default)
• 4'd3: CLK_IDAC – output
• 4'd8: Reserved
• 4'd3: CLK_DAC – output
• 4'd8: Reserved
VERSION 0.1.3
ES9069 Datasheet

Bits [7:4] [3:0]
Default 4'd0 4'd0

• 4'd3: CLK_BCK – output
• 4'd8: Reserved
• 4'd3: CLKEN_1FS – output
• 4'd8: Reserved
VERSION 0.1.3
ES9069 Datasheet

Bits [7:4] [3:0]
Default 4'd0 4'd0

• 4'd3: CLK_IDAC – output
• 4'd8: Reserved
• 4'd3: CLK_DAC – output
• 4'd8: Reserved
VERSION 0.1.3
ES9069 Datasheet
Register 41: GPIO OUTPUT ENABLE

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b1 1'b1

[7] GPIO8_OE • 1'b0: Tristate GPIO8 (default)
• 1'b1: GPIO8 Output enabled
[1] GPIO2_OE • 1'b0: Tristate GPIO2
• 1'b1: GPIO2 Output enabled (default)
[0] GPIO1_OE • 1'b0: Tristate GPIO1
• 1'b1: GPIO1 Output enabled (default)
Register 42: GPIO INPUT

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_SDB • 1'b0: Disables GPIO8 input (default)
• 1'b1: Enables GPIO8 input
[6] GPIO7_SDB • 1'b0: Disables GPIO7 input
• 1'b1: Enables GPIO7 input (default)
VERSION 0.1.3
ES9069 Datasheet
Register 43: GPIO WK EN

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_WK_EN • 1'b0: GPIO8 weak keeper disabled (default)
• 1'b1: GPIO8 weak keeper enabled
Register 44: INVERT GPIO

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] INVERT_GPIO8 • 1'b1: Inverts GPIO8 output.
VERSION 0.1.3
ES9069 Datasheet
Register 45: GPIO READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]

[7] GPIO8_READ • 1'b0: GPIO8 Readback disabled (default)
• 1'b1: Allow readback of GPIO8_I
Note: Requires corresponding GPIOx_SDB to be set.
VERSION 0.1.3
ES9069 Datasheet
Register 47-46: GPIO OUTPUT LOGIC

Bits [15] [14:7] [6] [5] [4] [3] [2] [1] [0]
Default 1'b0 8'd0 1'b0 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1

[15] GPIO_DAC_MODE When any GPIO_CFG is "System mode control":
• 1'b0: Disable datapath when GPIO input is 1'b1
• 1'b1: Enable datapath when GPIO input is 1
When GPIOx input is 1'b0, system mode is determined by register 0[1]
DAC_MODE.
[14:7] RESERVED NA
[6] GPIO_SEL Outputs a specific channel's flag if the corresponding GPIO_AND and
GPIO_OR are not set.
• 1'b0: Outputs status/flag from CH1
• 1'b1: Outputs status/flag from CH2
[5] GPIO_OR_SS_RAMP Sets the GPIO_CFG "Soft Ramp Done" flag output as the bitwise OR of both
channel's flags.
• 1'b1: Enabled, GPIO_CFG output is |(ss_full_ramp[CHx])
[4] GPIO_OR_VOL_MIN Sets the GPIO_CFG "Automute Status" output as the bitwise OR of both
channel's statuses.
• 1'b1: Enabled, GPIO_CFG output is |(automute[CHx])
[3] GPIO_OR_AUTOMUTE Sets the GPIO_CFG "Minimum Volume" flag output as the bitwise OR of
both channel's flags.
• 1'b1: Enabled, GPIO_CFG output is |(vol_min[CHx])
[2] GPIO_AND_SS_RAMP Sets the GPIO_CFG "Soft Ramp Done" flag output as the bitwise AND of
• 1'b0: Disabled
• 1'b1: Enabled, GPIO_CFG output is &(ss_full_ramp[CHx]) (default)
Note: Overriden by GPIO_OR_SS_RAMP.
[1] GPIO_AND_VOL_MIN Sets the GPIO_CFG "Automute Status" output as the bitwise AND of both
channel's statuses.
• 1'b0: Disabled
• 1'b1: Enabled, GPIO_CFG output is &(automute[CHx]) (default)
Note: Overriden by GPIO_OR_AUTOMUTE.
[0] GPIO_AND_AUTOMUTE Sets the GPIO_CFG "Minimum Volume" flag output as the bitwise AND of
• 1'b0: Disabled
• 1'b1: Enabled, GPIO_CFG output is &(vol_min[CHx]) (default)
Note: Overriden by GPIO_OR_VOL_MIN.
VERSION 0.1.3
ES9069 Datasheet
Register 48: PWM1 COUNT

Bits [7:0]
Default 8'd0

[7:0] PWM1_COUNT 8-bit value to set the number of SYS_CLK periods the PWM signal is high
for.
• 8'd0: Disabled (default)
• 8'd1: Minimum
• 8'd255: Maximum
Register 50-49: PWM1 FREQUENCY

Bits [15:0]
Default 16'd0

[15:0] PWM1_FREQ 16-bit value to set the frequency of the PWM signal in terms of SYS_CLK
divisions.
Valid from 16'h0000 to 16'hFFFF
𝑃𝑊𝑀1_𝐹𝑅𝐸𝑄 + 1
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 [%] = (𝑃𝑊𝑀1"_"𝐶𝑂𝑈𝑁𝑇)/(𝑃𝑊𝑀1"_"𝐹𝑅𝐸𝑄
+ 1)) × 100

Bits [7:0]
Default 8'd0

for.
• 8'd0: Disabled (default)
• 8'd1: Minimum
• 8'd255: Maximum

Bits [15:0]
Default 16'd0

divisions.
+ 1)) × 100

Bits [7:0]
Default 8'd0
VERSION 0.1.3
ES9069 Datasheet

for.
Valid from 8'd0 to 8'd255

Bits [15:0]
Default 16'd0

divisions.
+ 1)) × 100
VERSION 0.1.3
ES9069 Datasheet
DAC Registers
Register 57: INPUT SELECTION
Bits [7] [6] [5] [4] [3] [2:1] [0]
Default 1'b0 1'b1 1'b0 1'b0 1'b0 2'd0 1'b0

[7] AUTO_CH_DETECT Auto detect BCK/FRAME ratio to determine the number of TDM channels.
• 1'b1: Enabled
[6] ENABLE_DSD_FAULT_DETECTION Sets a channel to a DSD mute pattern (0x96) if the DSD data has no
changes in 64 DATA_CLKs.
• 1'b0: Disabled
• 1'b1: Enabled (default)
[5] DSD_MASTER_MODE DSD master mode config.
• 1'b0: DSD slave mode (default)
• 1'b1: DSD master mode. DSD_CLK outputs from DATA_CLK
[4] PCM_MASTER_MODE PCM master mode config.
• 1'b0: PCM slave mode (default)
• 1'b1: PCM master mode enabled. Master BCK and WS output from
DATA_CLK and DATA1
[3] RESERVED NA
[2:1] INPUT_SEL Selects input data format when AUTO_INPUT_SEL is disabled.
• 2'd0: PCM (default)
• 2'd1: DSD
• 2'd2: DoP
• 2'd3: S/PDIF
[0] AUTO_INPUT_SEL Automatic input data selection config.
• 1'b0: Disables auto input select. Input data format is set by
INPUT_SEL (default)
• 1'b1: Automatically determine the input data format.
Note: When using AUTO_INPUT_SEL & DSD, it is required that DSD data
lines are on DATA1 & DATA2.
VERSION 0.1.3
ES9069 Datasheet
Register 58: MASTER ENCODER CONFIG

Bits [7] [6] [5] [4:3] [2] [1] [0]
Default 1'b0 1'b0 1'b0 2'd0 1'b0 1'b0 1'b1

[7] TDM_RESYNC Force TDM decoder to resync.
• 1'b0: Enable TDM decoder synchronization (default)
• 1'b1: Force TDM decoder to desynchronize.
[6] BCK_INV Invert the slave BCK
• 1'b0: Normal operation
• 1'b1: Invert slave BCK
[5] RESERVED NA
[4:3] MASTER_FRAME_LENGTH Selects the bit length in each TDM channel in master mode.
• 2'd0: 32-bit (default)
• 2'd1: 24-bit
• 2'd2: 16-bit
• 2'd3: Reserved
[2] MASTER_WS_PULSE_MODE When enabled, master WS is a pulse signal instead of a 50% duty cycle
signal. The pulse width is 1 BCK cycle.
• 1'b0: 50% duty cycle WS signal (default)
• 1'b1: Pulse WS signal
[1] MASTER_WS_INVERT Inverts master WS.
• 1'b0: Non-inverted (default)
• 1'b1: Inverted
[0] MASTER_BCK_INVERT Inverts master BCK or DSD_CLK.
• 1'b0: Non-inverted
• 1'b1: Inverted (default)
Register 59: TDM CONFIG

Bits [7:5] [4:0]
Default 3'd0 5'd1

[7:5] RESERVED NA
[4:0] TDM_CH_NUM Total number of TDM slots per frame = TDM_CH_NUM + 1.
VERSION 0.1.3
ES9069 Datasheet
Register 60: TDM CONFIG1

Bits [7] [6] [5:0]

[7] TDM_LJ_MODE TDM LJ mode.
• 1'b0: Standard I2S (default)
• 1'b1: LJ mode
[6] TDM_VALID_EDGE TDM WS valid edge.
• 1'b0: negative edge (default)
• 1'b1: positive edge
[5:0] RESERVED NA
Register 61: TDM CONFIG2

Bits [7] [6:5] [4:0]

[7] RESERVED NA
[6:5] TDM_BIT_WIDTH Bit width of each TDM slot.
• 2'b00: 32-bit (default)
• 2'b01: 24-bit
• 2'b10: 16-bit
• 2'b11: Reserved
[4:0] TDM_DATA_LATCH_ADJ Sets the position of the start bit within each TDM slot.
Can be moved by TDM_DATA_LATCH_ADJ clock cycles.
• 5'd0: Normal position
• 5'd1-31: Number of clock cycles to wait
VERSION 0.1.3
ES9069 Datasheet
Register 62: BCK/WS MONITOR CONFIG

Bits [7] [6] [5] [4] [3] [2:0]
Default 1'b0 1'b0 1'b1 1'b1 1'b0 3'd0

[7] DISABLE_DSD_DC • 1'b0: DSD DC can trigger an automute if automute is enabled
(default)
• 1'b1: DSD DC is ignored.
[6] DISABLE_DSD_MUTE • 1'b0: DSD mute pattern can trigger an automute is automute is
enabled (default)
• 1'b1: DSD mute pattern is ignored.
[5] ENABLE_WS_MONITOR Enable WS monitor.
• 1'b0: Disable
• 1'b1: Enable (default)
[4] ENABLE_BCK_MONITOR Enable BCK monitor.
• 1'b0: Disable (default)
• 1'b1: Enable
[3] DISABLE_PCM_DC • 1'b0: PCM DC signal can trigger an automute if automute is enabled.
• 1'b1: PCM DC is ignored.
[2:0] RESERVED NA
Register 64: CH1 SLOT CONFIG

Bits [7:5] [4:0]
Default 3'd0 5'd0

[7:5] DSD_CH1_SOURCE Selects the source for the CH1 DSD data.
• 3'd0: DATA1 (default)
• 3'd1: DATA2
• 3'd2: GPIO1
• 3'd3: GPIO2
• 3'd4: GPIO3
• 3'd5: GPIO4
• 3'd6: GPIO5
• 3'd7: GPIO6
Note: If AUTO_INPUT_SEL is enabled, DSD data lines must be on DATA1
& DATA2.
[4:0] PCM_CH1_SLOT_SEL CH1 data slot selection. CH1 receives data from Mth slot.
M = TDM_CH1_SLOT_SEL + 1.
Note: Valid for TDM, PCM and DoP.
VERSION 0.1.3
ES9069 Datasheet
Register 65: CH2 SLOT CONFIG

Bits [7:5] [4:0]
Default 3'd1 5'd1

[7:5] DSD_CH2_SOURCE Selects the source for the CH2 DSD data.
• 3'd0: DATA1
• 3'd1: DATA2 (default)
• 3'd2: GPIO1
• 3'd3: GPIO2
• 3'd4: GPIO3
• 3'd5: GPIO4
• 3'd6: GPIO5
• 3'd7: GPIO6
Note: If AUTO_INPUT_SEL is enabled, DSD data lines must be on DATA1
& DATA2.
[4:0] PCM_CH2_SLOT_SEL CH2 data slot selection. CH2 receives data from Mth slot.
M = PCM_CH2_SLOT_SEL + 1.
Note: Valid for PCM and DoP.
Register 74: VOLUME CH1

Bits [7:0]
Default 8'd0

[7:0] VOLUME_CH1 DAC CH1 volume. -0dB to -127.5dB, 0.5dB steps
• 8'd0: 0dB
• 8'd255: -127.5dB
Register 75: VOLUME CH2

Bits [7:0]
Default 8'd0

[7:0] VOLUME_CH2 DAC CH2 volume. -0dB to -127.5dB, 0.5dB steps
• 8'd0: 0dB
• 8'd255: -127.5dB
VERSION 0.1.3
ES9069 Datasheet
Register 82: DAC VOL UP RATE

Bits [7:0]
Default 8'h04

[7:0] DAC_VOL_RATE_UP Linear step size from the current volume to a target volume, represented as
a fraction of full-scale.
• 8'h00: Instant change
• 8'h01: Slowest change
• 8'h04: Default
• 8'hFF: Fastest change
𝑖𝑛𝑐 𝐷𝐴𝐶_𝑉𝑂𝐿_𝑅𝐴𝑇𝐸_𝑈𝑃 ∗ 𝐹𝑆
• 𝑣𝑜𝑙_𝑠𝑡𝑒𝑝_𝑟𝑎𝑡𝑒 [ ] = 12
𝑠 2
Register 83: DAC VOL DOWN RATE

Bits [7:0]
Default 8'h04

[7:0] DAC_VOL_RATE_DOWN Linear step size from the current volume to a target volume, represented as
• 8'h04: Default
• 8'hFF: Fastest change
𝑑𝑒𝑐 𝐷𝐴𝐶_𝑉𝑂𝐿_𝑅𝐴𝑇𝐸_𝐷𝑂𝑊𝑁 ∗ 𝐹𝑆
𝑠 2
Register 84: DAC VOL DOWN RATE FAST

Bits [7:0]
Default 8'hFF

[7:0] DAC_VOL_RATE_FAST Linear step size from the current volume to a target volume, represented as
Only used during abnormal mute (PLL unlock or BCK_WS ratio failed)
• 8'hFF: Fastest change (default)
𝑑𝑒𝑐 𝐷𝐴𝐶_𝑉𝑂𝐿_𝑅𝐴𝑇𝐸_𝐹𝐴𝑆𝑇 ∗ 𝐹𝑆
𝑠 2
VERSION 0.1.3
ES9069 Datasheet
Register 86: DAC MUTE

Bits [7:2] [1] [0]

[7:2] RESERVED NA
[1] DAC_MUTE_CH2 • 1'b0: Normal CH2 operation (default)
• 1'b1: Mute CH2
[0] DAC_MUTE_CH1 • 1'b0: Normal CH1 operation (default)
• 1'b1: Mute CH1
Register 87: DAC INVERT

Bits [7:2] [1] [0]

[7:2] RESERVED NA
[1] DAC_INVERT_CH2 Invert the output on CH2 at the input to the noise shaped modulator
(NSMOD).
• 1'b0: Uninverted CH2 DAC output (default)
• 1'b1: Inverted CH2 DAC output
[0] DAC_INVERT_CH1 Invert the output on CH1 at the input to the noise shaped modulator
(NSMOD).
• 1'b0: Uninverted CH1 DAC output (default)
• 1'b1: Inverted CH1 DAC output
Register 88: FILTER SHAPE

Bits [7:3] [2:0]
Default 5'd12 3'd0

[7:3] RESERVED NA
[2:0] FILTER_SHAPE Selects the 8x interpolation FIR filter shape.
• 3'd0: Minimum phase (default)
• 3'd1: Linear phase fast roll-off apodizing
• 3'd2: Linear phase fast roll-off
• 3'd3: Linear phase fast roll-off low ripple
• 3'd4: Linear phase slow roll-off
• 3'd5: Minimum phase fast roll-off
• 3'd6: Minimum phase slow roll-off
• 3'd7: Minimum phase slow roll-off low dispersion
VERSION 0.1.3
ES9069 Datasheet
Register 89: IIR BANDWIDTH & S/PDIF SEL

Bits [7:4] [3] [2:0]
Default 4'd0 1'b0 3'd4

[7:4] SPDIF_SEL Selects the S/PDIF data input pin
• 4'd0: Disconnected
• 4'd1: DATA1
• 4'd2: DATA2
• 4'd3: GPIO1
• 4'd4: GPIO2
• 4'd5: GPIO3
• 4'd6: GPIO4
• 4'd7: GPIO5
• 4'd8: GPIO6
• 4'd9: GPIO7
• 4'd10: GPIO8
• Others: Reserved
Note: GPIOx pins also require the GPIOx_SDB to be enabled.
[3] VOLUME_HOLD Hold volume coefficients to allow for all channels to update at same time.
• 1'b0: Channel volume will update with changes to reg 74-75.
• 1'b1: Channel volumes will not update.
[2:0] IIR_BW Controls the IIR bandwidth in the digital datapath.
• 3'd0: Reserved
• 3'd1: BW * 8
• 3'd2: BW * 4
• 3'd3: BW * 2
• 3'd4: BW (default)
• 3'd5: BW / 2
• 3'd6: BW / 4
• 3'd7: BW / 8
Register 90: DAC PATH CONFIG

Bits [7:3] [2] [1] [0]
Default 5'b00000 1'b0 1'b0 1'b0

[7:3] RESERVED NA
[2] BYPASS_IIR Bypass the IIR filter.
• 1'b0: Non-bypassed (default)
• 1'b1: Bypassed
[1] BYPASS_FIR4X Bypass the 4X FIR filter.
• 1'b1: Bypassed
[0] BYPASS_FIR2X Bypass the 2X FIR filter.
• 1'b1: Bypassed
Register 94-91: THD C2

Bits [31:16] [15:0]
Default 16'd0 16'd0
VERSION 0.1.3
ES9069 Datasheet

[31:16] THD_C2_CH2 A 16-bit signed coefficient for correcting for the CH2 second harmonic
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
[15:0] THD_C2_CH1 A 16-bit signed coefficient for correcting for the CH1 second harmonic
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
Register 110-107: THD C3

Bits [31:16] [15:0]
Default 16'd0 16'd0

[31:16] THD_C3_CH2 A 16-bit signed coefficient for correcting for the CH2 third harmonic
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
[15:0] THD_C3_CH1 A 16-bit signed coefficient for correcting for the CH1 third harmonic
distortion.
𝑜𝑢𝑡𝑝𝑢𝑡 = 𝑥 + 𝑐2 ∗ 𝑥 2 + 𝑐3 ∗ 𝑥 3
Register 123: AUTOMUTE ENABLE

Bits [7:2] [1] [0]

[7:2] RESERVED NA
[1] AUTOMUTE_EN_CH2 • 1'b0: Disables ch2 automute
• 1'b1: Enables ch2 automute (default)
Note: Automute is available for PCM only
[0] AUTOMUTE_EN_CH1 • 1'b0: Disables ch1 automute
• 1'b1: Enables ch1 automute (default)
Note: Automute is available for PCM only
VERSION 0.1.3
ES9069 Datasheet
Register 125-124: AUTOMUTE TIME

Bits [15:12] [11] [10:0]
Default 4'b0000 1'b1 11'h00F

[15:12] RESERVED NA
[11] MUTE_RAMP_TO_GROUND • 1'b0: When ramped to min volume during normal mute, do not soft
ramp to ground
• 1'b1: When ramped to min volume during normal mute, soft ramp to
ground for power saving (default)
normal mute includes: automute, mute by register, mute by GPIO
[10:0] AUTOMUTE_TIME Configures the amount of time in seconds the audio must remain below
AUTOMUTE_LEVEL before an automute condition is flagged.
• 11'h000: Disabled
• 11'h001: Slowest
• 11'h00F: Default
• 11'h7FF: Fastest
218
• 𝑇𝑖𝑚𝑒 [𝑠] =
𝐴𝑈𝑇𝑂𝑀𝑈𝑇𝐸_𝑇𝐼𝑀𝐸∗𝐹𝑆
Register 127-126: AUTOMUTE LEVEL

Bits [15:0]
Default 16'0008

[15:0] AUTOMUTE_LEVEL The threshold which the audio must be below before an automute condition
is flagged.
Shift right 1 bit corresponds to -6dB
• 16'h0001: -132dB
• 16'h0008: -119dB (default)
• 16'hFFFF: -42dB
Note: Only applies to PCM automute conditions.
Register 129-128: AUTOMUTE OFF LEVEL

Bits [15:0]
Default 16'000A

[15:0] AUTOMUTE_OFF_LEVEL The threshold which the audio must be above before the automute condition
is immediately cleared.
Shift right 1 bit corresponds to -6dB
• 16'h0001: -132dB
• 16'h000A: -117.5dB (default)
• 16'hFFFF: -42dB
Note: Only applies to PCM automute conditions.
VERSION 0.1.3
ES9069 Datasheet
Register 130: SOFT RAMP CONFIG

Bits [7:5] [4:0]
Default 3'b000 5'd3

[7:5] RESERVED NA
[4:0] SOFT_RAMP_TIME Sets the amount of time that it takes to perform a soft start ramp.
This time affects both ramp to ground and ramp to AVCC/2.
Valid from 0 to 20 (inclusive).
2𝑆𝑂𝐹𝑇_𝑅𝐴𝑀𝑃_𝑇𝐼𝑀𝐸+1
𝑇𝑖𝑚𝑒 [𝑠] = 4096 ∗
𝐶𝐿𝐾𝐼𝐷𝐴𝐶[𝐻𝑧]
Register 135: PROGRAM RAM CONTROL

Bits [7:2] [1] [0]

[7:2] RESERVED NA
[1] PROG_COEFF_WE Enables writing to the programmable coefficient RAM.
• 1'b0: Disables write signal to the coefficient RAM (default).
• 1'b1: Enables write signal to the coefficient RAM.
[0] PROG_COEFF_EN Enables the custom oversampling filter coefficients.
• 1'b0: Uses a built-in filter selected by filter_shape (default).
• 1'b1: Uses the coefficients programmed via prog_coeff_data.
Register 136: S/PDIF READ CONTROL

Bits [7:5] [4:0]
Default 3'b000 5'd0

[7:5] RESERVED NA
[4:0] SPDIF_DATA_SEL Selects the byte of the S/PDIF payload in register 251 spdif_payload_read
• 24 bytes total
VERSION 0.1.3
ES9069 Datasheet
Register 137: PROGRAM RAM ADDRESS

Bits [7] [6:0]
Default 1'b0 7'd0

[7] PROG_COEFF_STAGE Selects which stage of the filter to write.
• 1'b0: Selects the 2x stage of the oversampling filter (default).
• 1'b1: Selects the 4x stage of the oversampling filter.
[6:0] PROG_COEFF_ADDR Selects the coefficient address when writing custom coefficients for the
oversampling filter.
Register 140-138: PROGRAM RAM DATA

Bits [23:0]
Default 24'd0

[23:0] PROG_COEFF_IN A 24-bit signed filter coefficient that will be written to the address defined in
prog_coeff_addr.
Register 141: MQA CONFIG

Bits [7:1] [0]
Default 5'b1000000 1'b0

[7:1] RESERVED NA
[0] MQA_RENDERING_ENABLE This allows the Sabre ES9069 to render decoded MQA streams.
• 1'b1: Enabled
VERSION 0.1.3
ES9069 Datasheet
Readback Registers
Register 225: CHIP ID READ

Bits [7:0]
Default -

[7:0] CHIP_ID Chip ID for ES9069 is 0x62 (98d)
Register 230-229: INTERRUPT STATES

Bits [15:14] [13:12] [11] [10:8] [7] [6] [5:4] [3:2] [1:0]
Default - - - - - - - - -

[15:14] RESERVED NA
[13:12] INPUT_SELECT_OVERRIDE_STATE State of the INPUT_SELECT_OVERRIDE interrupt.
Note: Interrupt clear bits are required to reset value.
[11] TDM_DATA_VALID_STATE State of the TDM_DATA_VALID interrupt.
Note: Interrupt clear bit is required to reset value.
[10:8] RESERVED NA
[7] BCK_WS_FAIL_STATE State of the BCK_WS_FAIL interrupt.
[6] DOP_VALID_STATE State of the DOP_VALID interrupt.
[5:4] SS_FULL_RAMP_STATE State of each channel's SS_FULL_RAMP interrupt.
[3:2] AUTOMUTE_STATE State of each channel's AUTOMUTE_STATE interrupt.
[1:0] VOL_MIN_STATE State of each channel's VOL_MIN_STATE interrupt.
VERSION 0.1.3
ES9069 Datasheet
Register 235-234: INTERRUPT SOURCES

Bits [15:14] [13:12] [11] [10:8] [7] [6] [5:4] [3:2] [1:0]
Default - - - - - - - - -

[15:14] RESERVED NA
[13:12] INPUT_SELECT_OVERRIDE_SOURCE Output of the AUTO_INPUT_SELECT logic.
[11] TDM_DATA_VALID_SOURCE TDM data valid flag.
[10:8] RESERVED NA
[7] BCK_WS_FAIL_SOURCE Validity of BCK, WS, and ASYNC_LOCK flag.
Requires respective monitor bits to be set.
[6] DOP_VALID_SOURCE Valid DoP flag for Channels 1 and 2.
[5:4] SS_FULL_RAMP_SOURCE Channel flag for whether it is automute is active.
[3:2] AUTOMUTE_SOURCE Channel flag for whether it is automute is active.
[1:0] VOL_MIN_SOURCE Channel flag for whether the corresponding volume register = 0x00
Register 239: RATIO VALID READ

Bits [7] [6:0]
Default - -

[7] RATIO_VALID Indicates validity of the CLK_DAC/CLK_IDAC ratio
• 1'b0: Invalid
• 1'b1: Valid
[6:0] RESERVED NA
Register 240: GPIO READ

Bits [7] [6] [5] [4] [3] [2] [1] [0]
Default - - - - - - - -

[7] GPIO8_I_READ GPIO8 input readback.
VERSION 0.1.3
ES9069 Datasheet
Register 241: VOL MIN READ

Bits [7:2] [1] [0]
Default - - -

[7:2] RESERVED NA
[1] VOL_MIN_CH2 Volume min flag ch2
[0] VOL_MIN_CH1 Volume min flag ch1
Register 242: AUTOMUTE READ

Bits [7:2] [1] [0]
Default - - -

[7:2] RESERVED NA
[1] AUTOMUTE_CH2 Automute status ch2
[0] AUTOMUTE_CH1 Automute status ch1
Register 243: SOFT RAMP UP READ

Bits [7:2] [1] [0]
Default - - -

[7:2] RESERVED NA
[1] SS_RAMP_UP_CH2 Soft ramped up flag ch2
[0] SS_RAMP_UP_CH1 Soft ramped up flag ch1
Register 244: SOFT RAMP DOWN READ

Bits [7:2] [1] [0]
Default - - -

[7:2] RESERVED NA
[1] SS_RAMP_DOWN_CH2 Soft ramped down flag ch2
[0] SS_RAMP_DOWN_CH1 Soft ramped down flag ch1
VERSION 0.1.3
ES9069 Datasheet
Register 245: INPUT STREAM READBACK

Bits [7:5] [4] [3] [2] [1:0]
Default - - - - -

[7:5] RESERVED NA
[4] SPDIF_VALID S/PDIF valid flag
[3] TDM_DATA_VALID TDM valid data flag
[2] DOP_VALID DoP valid flag
[1:0] INPUT_SELECT_OVERRIDE AUTO_INPUT_SEL value
• 2'd0: PCM (default)
• 2'd1: DSD
• 2'd2: DoP
• 2'd3: S/PDIF
Register 248-246: PROG COEFF OUT READ

Bits [23:0]
Default -

[23:0] PROG_COEFF_OUT Programmable FIR coefficient readback
Register 251: S/PDIF DATA READ

Bits [7:0]
Default -

[7:0] SPDIF_DATA_READ Contains a byte of the S/PDIF payload.
Controlled by register 136[4:0] spdif_data_sel
VERSION 0.1.3
ES9069 Datasheet
ES9069 Reference Schematics

Typical Application Schematic
3.3V 3.3V 3.3V 3.3V
AVCC_DAC2 AVCC_DAC1 VCCA AVDD
CLK Input MCLK
DVDD
2
Hi/Lo (SPI/I C)
Mode (SW)
CHIP_EN
I2C/SPI
8 GPIO1-8*
SDA/MOSI
ES9069 DAC1
Output Stage
Application SCL/SCLK
Processor DAC1B
DATA2
DATA1
DATA_CLK
PCM/DSD/DoP/MQA
DAC2
DAC2B
ADDR0/MISO
ADDR1/SS
RT1 AGND_DAC2 AGND_DAC1 GND
(also Exposed pad)
Figure 20. Typical ES9069 Software Mode Application Diagram
*Note: See GPIO section for configuration of GPIOs including GPIO8.
VERSION 0.1.3
ES9069 Datasheet
Hardware (HW) mode
Figure 21 – Hardware (HW) mode reference schematic for ES9069Q
Note: ES9069Q has an exposed pad (EPAD, pin 33) and should be connected to ground.
VERSION 0.1.3
ES9069 Datasheet
Software (SW) mode
Figure 22 – Software mode reference schematic for ES9069Q
Note: ES9069Q has an exposed pad (EPAD, pin 33) and should be connected to ground.
VERSION 0.1.3
ES9069 Datasheet
Recommended Output Stage
Figure 15 – Output stage schematic for ES9069Q
Note 1: Schematic is representative of ES9069 EVB v2.0

Note 2: A 3 opamp output stage schematic with slightly improved THD+N performance with a slight increase in noise is available, see distributor or
FAE for more information if required.
Note 3: C6, C10 & C11 values are chosen specifically for OPA1612, change depending on desired frequency response.
VERSION 0.1.3
ES9069 Datasheet
Internal Pad Circuitry
Pin Type Pin Name Equivalent Circuit
AVCC_DAC1 1
AVCC_DAC2 8
Power
AVDD 10
VCCA 31
AGND_DAC1 4
AGND_DAC2 5
Ground
GND 11
GND 30
CHIP_EN Reset 18
DATA_CLK 12
DATA1 13
DATA2 14
SCLK/SCL/HW1 15
MOSI/SDA/HW0 16
RT1 17
SS/ADDR1/HW2 19
MISO/ADDR0/MUTE_CTRL 20
Digital I/O
GPIO1 21
GPIO2 22
GPIO3 23
GPIO4 24
GPIO5 25
GPIO6 26
GPIO7 27
MODE 29
VERSION 0.1.3
ES9069 Datasheet
Digital I/O
GPIO 8 28
Cal_Res
DAC1B 2
DAC1 3
DAC2B Analog IO DAC 6
DAC2 7
MCLK 32
DVDD IO Power 9
Table 28 – Internal Pad Circuitry
VERSION 0.1.3
ES9069 Datasheet
32 QFN Package Dimensions
Figure 23 – ES9069Q 32 QFN package dimensions
VERSION 0.1.3
ES9069 Datasheet
32 QFN Top View Marking
Figure 24 – ES9069Q Marking
Dimension in mm
Package Type A B C D E F G
32 QFN 5mm x 5mm 4.0 1.6 0.2 0.4 0.2 0.1 0.3
T Tracking number
W Work week
Y Last digit of year
L Lot number
R Silicon Revision
VERSION 0.1.3
ES9069 Datasheet
Reflow Process Considerations

Temperature Controlled
For lead-free soldering, the characterization and optimization of the reflow process is the most important factor to consider.
The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperature of 235°C to ensure good wetting. The
maximum reflow temperature is in the 245°C to 260°C range, depending on the package size (RPC-2 Pb-Free Process – Classification
Temperatures (Tc)). This narrows the process window for lead-free soldering to 10°C to 20°C.
The increase in peak reflow temperature in combination with the narrow process window makes the development of an optimal reflow profile a
critical factor for ensuring a successful lead-free assembly process. The major factors contributing to the development of an optimal thermal profile
are the size and weight of the assembly, the density of the components, the mix of large and small components, and the paste chemistry being used.
Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other critical locations on the
board to ensure that all components are heated to temperatures above the minimum reflow temperatures and that smaller components do not
exceed the maximum temperature limits (Table RPC-2).
To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by ESS are based on the
JEDEC/IPC standard J-STD-020 revision D.1.
Figure 25 – IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)
Reflow is allowed 3 times. Caution must be taken to ensure time between re-flow runs does not exceed the allowed time by the moisture sensitivity
label. If the time elapsed between the re-flows exceeds the moisture sensitivity time bake the board according to the moisture sensitivity label
instructions.
Manual
Allowed up to 2 times with maximum temperature of 350°C no longer than 3 seconds.
VERSION 0.1.3
ES9069 Datasheet
RPC-1 Classification reflow profile

Profile Feature Pb-Free Assembly
Preheat/Soak
Temperature Min (Tsmin) 150°C
Temperature Max (Tsmax) 200°C
Time (ts) from (Tsmin to Tsmax) 60-120 seconds
Ramp-up rate (TL to Tp) 3°C / second maximum
Liquidous temperature (TL) 217°C
Time (tL) maintained above TL 60-150 seconds
For users Tp must not exceed the classification temp in Table RPC-
2.
Peak package body temperature (Tp)
For suppliers Tp must equal or exceed the Classification temp in
Table RPC-2.
Time (tp)* within 5°C of the specified classification temperature (Tc) 30* seconds
Ramp-down rate (Tp to TL) 6°C / second maximum
Time 25°C to peak temperature 8 minutes maximum
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Table 29 – RPC-1 Classification reflow profile
All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug).
If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ±2°C of the live-bug Tp and still
meet the Tc requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body
temperatures, refer to JEP140 for recommended thermocouple use.
Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly
profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table RPC-1.
For example, if Tc is 260°C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260°C. The time above 255°C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260°C. The time above 255°C must not exceed 30 seconds.
All components in the test load shall meet the classification profile requirements.
RPC-2 Pb-Free Process – Classification Temperatures (Tc)

Package Thickness Volume mm3, <350 Volume mm3, 350 to 2000 Volume mm3, >2000
<1.6 mm 260°C 260°C 260°C
1.6 mm – 2.5 mm 260°C 250°C 245°C
>2.5 mm 250°C 245°C 245°C
Table 30 – RPC-2 Pb free classification temperatures
At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the
values specified in Table RPC-2. The use of a higher Tp does not change the classification temperature (Tc).
Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks.
The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes
reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist.
VERSION 0.1.3
ES9069 Datasheet
Ordering Information
Part Number Description Package
ES9069Q SABRE 32-bit high performance 2 Channel DAC 5mm x 5mm 32 QFN
Revision History
Current Version 0.1.3
Rev. Date Notes
0.1.2 March, 2023 Initial release
• Updated output stage schematic
• Updated S/PDIF section
0.1.3 March 14, 2023
• Updated Reg 57[0], Reg64[7:5], Reg65[7:5]
• Corrected Reg 137 heading
© 2023 ESS Technology, Inc.
ESS IC’s are not intended, authorized, or warranted for use as components in military applications, medical devices or life support systems. ESS assumes no liability and disclaims
any expressed, implied or statutory warranty for use of ESS IC’s in such unsuitable applications.
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise,
without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications
are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.

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ES9069

32-bit High performance 2 Channel DAC with MQA

The ES9069 SABRE® DAC improves on previous designs to include:

Patented 32-bit HyperStream® IV Architecture

32-bit processing Distortion free signal processing

Analog Features ............................................................................................................................................................................................................. 41

Functional Block Diagram

VCCA DVDD AVDD

CHIP_EN CLK DETECT / POR

Figure 1 - ES9069 Block Diagram

Figure 2. ES9069Q Pinout*

32 QFN Pin Descriptions

MODE PIN Configuration

Each hardware mode pin has 4 states:

In Hardware mode, most GPIOs have specific functions:

GPIO # Input/Output HW mode function

Table 4 – GPIO function in Hardware mode

Figure 2 - Hardware mode pin configurations

HW MUTE Control (Pin 20) Condition

Table 5 – Mute Control for HW mode configuration

Hardware Mode Pin Configurations

Table 6 - Hardware mode pin configurations table

Recommended Hardware Mode Setup Sequence

Figure 3 - Hardware mode startup sequence

Digital Signal Path

SABRE DAC DIGITAL PATH

8x interpolation Noise Shaped

Volume Control Registers

Mode Detection Condition Time

Table 7 – Automute Configuration

8x FIR Interpolation Oversampling Filter

For more information on filters see Digital filters section

Figure 4 – THD Compensation Block Diagram

THD Compensation Coefficient Registers

GPIO Software Configuration

Table 8 - GPIO Configuration function

GPIO Configuration Descriptions

System mode control

When any GPIOx_CFG = 4’d6 (system mode control):

• 1’b0: Disable datapath when GPIOx input is 1’b1

SRC Lock status

Each PWM signal can be controlled by the following registers:

• PWM1: register 48 PWM1_COUNT, register 49-50 PWM1_FREQ

Soft ramp done

GPIO Pin Descriptions

GPIOx Hardware Mode Software mode

Table 9 - GPIO Hardware & Software mode pin descriptions

Note*: In Hardware mode GPIO7 needs to be connected to Ground.

Audio Input Formats

For Hardware mode see hardware mode for inputs.

This formats include:

PCM (I2S, LJ, RJ)

PCM Pin Connections (default configuration)

Table 10 - PCM pin connections

Note: RJ is supported but only in software mode.

TDM (Time-division multiplexing)

TDM Pin Connections (default configuration)

Table 11 - TDM pin connections

Figure 6 – TDM128 mode