ESP32

Hardware Design Guidelines

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Espressif Systems
Jun 28, 2024
Table of contents

Table of contents i

1 About This Document 3

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Latest Version of This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Product Overview 5

3 Schematic Checklist 7
3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Digital Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Analog Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 RTC Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Chip Power-up and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Flash and PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1 In-Package Flash and PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2 Off-Package Flash and PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1 External Crystal Clock Source (Compulsory) . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.2 RTC Clock Source (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.1 RF Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.2 RF Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Strapping Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 External Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Touch Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 PCB Layout Design 21

4.1 General Principles of PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Positioning a Module on a Base Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.1 General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.2 3.3 V Power Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.3 Analog Power Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.4 Two-layer PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5.1 RF Layout on Four-layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5.2 RF Layout on Two-layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Flash and PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.7 External RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.9 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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 4.10 Touch Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10.1 Electrode Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.11 Typical Layout Problems and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.1 1. The voltage ripple is not large, but the TX performance of RF is rather poor. . . . . . . 32
4.11.2 2. When ESP32 sends data packages, the voltage ripple is small, but RF TX performance
is poor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.3 3. When ESP32 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. . . . . . . . . . . . . . . . . . . . . . 32
4.11.4 4. TX performance is not bad, but the RX sensitivity is low. . . . . . . . . . . . . . . . . 32

5 Hardware Development 33
5.1 ESP32 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 ESP32 Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Download Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 Related Documentation and Resources 35

7 Glossary 37

8 Revision History 39
8.1 ESP Hardware Design Guidelines v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9 Disclaimer and Copyright Notice 41

ii
Table of contents

This document provides guidelines for the ESP32 SoC.

Schematic Checklist PCB Layout Design Hardware Development

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Table of contents

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Chapter 1

About This Document

1.1 Introduction
The hardware design guidelines advise on how to integrate ESP32 into a product. These guidelines will help to
achieve optimal performance of your product, ensuring technical accuracy and adherence to Espressif’s standards.
The guidelines are intended for hardware and application engineers.
The document assumes that you possess a certain level of familiarity with the ESP32 SoC. In case you lack prior
knowledge, we recommend utilizing this document in conjunction with the ESP32 Series Datasheet.

1.2 Latest Version of This Document

Check the link to make sure that you use the latest version of this document: https://docs.espressif.com/projects/
esp-hardware-design-guidelines/en/latest/esp32/index.html

3
Chapter 1. About This Document

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Chapter 2

Product Overview

ESP32 is a system on a chip that integrates the following features:

• Wi-Fi (2.4 GHz band)
• Bluetooth®
• Dual high-performance Xtensa® 32-bit LX6 CPU cores
• Ultra Low Power coprocessor
• Multiple peripherals
Powered by 40 nm technology, ESP32 provides a robust, highly-integrated platform, which helps meet the continuous
demands for efficient power usage, compact design, security, high performance, and reliability. Typical application
scenarios for ESP32 include:

• Smart Home
• Industrial Automation
• Health Care
• Consumer Electronics
• Smart Agriculture
• POS Machines
• Service Robot
• Audio Devices
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers
• Cameras for Video Streaming
• Speech Recognition
• Image Recognition
• SDIO Wi-Fi + Bluetooth Networking Card
• Touch and Proximity Sensing
For more information about ESP32, please refer to ESP32 Series Datasheet.

Note: Unless otherwise specified,“ESP32”used in this document refers to the series of chips, instead of a specific
chip variant.

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Chapter 2. Product Overview

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Chapter 3

Schematic Checklist

The integrated circuitry of ESP32 requires only 20 electrical components (resistors, capacitors, and inductors) and
a crystal, as well as an SPI flash. The high integration of ESP32 allows for simple peripheral circuit design. This
chapter details the schematic design of ESP32.
The following figure shows a reference schematic design of ESP32. It can be used as the basis of your schematic
design.

Fig. 1: ESP32 Reference Schematic

Note that Figure ESP32 Reference Schematic shows the connection for quad 3.3 V external flash/PSRAM. PSRAM’
s SCLK and flash can share the clock from SD_CLK or GPIO17.
• In cases where quad 1.8 V external flash/PSRAM is used, R9 should be populated.
• In cases where ESP32-D0WDR2-V3 with in-package quad 3.3 V PSRAM is used, the external flash can be
connected as Figure ESP32 Reference Schematic shows.
• In cases where ESP32-U4WDH with in-package quad 3.3 V flash is used, the in-package flash is connected as
Figure ESP32 Schematic for Quad 3.3 V In-Package Flash shows.
Any basic ESP32 circuit design may be broken down into the following major building blocks:

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Chapter 3. Schematic Checklist

Fig. 2: ESP32 Schematic for Quad 3.3 V In-Package Flash

• Power supply
• Chip power-up and reset timing
• Flash and PSRAM
• Clock source
• RF
• UART
• Strapping pins
• GPIO
• ADC
• External capacitor
• SDIO
• Touch sensor
The rest of this chapter details the specifics of circuit design for each of these sections.

3.1 Power Supply

The general recommendations for power supply design are:
• When using a single power supply, the recommended power supply voltage is 3.3 V and the output current is
no less than 500 mA.
• It is suggested to add an ESD protection diode at the power entrance.
More information about power supply pins can be found in ESP32 Series Datasheet > Section Power Supply.

3.1.1 Digital Power Supply

ESP32 has pin37 VDD3P3_CPU as the digital power supply pin(s) working in a voltage range of 1.8 V ~ 3.6 V. It is
recommended to add an extra 0.1 μF decoupling capacitor close to the pin(s).
Pin VDD_SDIO can serve as the power supply for the external device at either 1.8 V or 3.3 V (default).
• When VDD_SDIO operates at 1.8 V, it is powered by ESP32’s internal LDO. The maximum current this
LDO can offer is 40 mA, and the output voltage range is 1.65 V ~ 2.0 V. When the VDD_SDIO outputs 1.8 V,

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Chapter 3. Schematic Checklist

it is recommended that users add a 2 kΩ ground resistor and a 4.7 μF ground capacitor close to VDD_SDIO.
See Figure ESP32 Schematic for 1.8 V VDD_SDIO Power Supply Pin.
• When VDD_SDIO operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 6 Ω resistor (internal to
the chip), therefore, there will be some voltage drop from VDD3P3_RTC. When the VDD_SDIO outputs 3.3
V, it is recommended that users add a 1 μF filter capacitor close to VDD_SDIO. See Figure ESP32 Schematic
for 3.3 V VDD_SDIO Power Supply Pin.

Attention: When using VDD_SDIO as the power supply pin for in-package or off-package 3.3 V flash/PSRAM,
the supply voltage should be 3.0 V or above, so as to meet the requirements of flash/PSRAM’s working voltage.

Fig. 3: ESP32 Schematic for 1.8 V VDD_SDIO Power Supply Pin

Fig. 4: ESP32 Schematic for 3.3 V VDD_SDIO Power Supply Pin

VDD_SDIO can also be driven by an external power supply as shown in Figure ESP32 Schematic for VDD_SDIO Pin
Powered by External Supply.

3.1.2 Analog Power Supply

ESP32’s VDDA and VDD3P3 pins are the analog power supply pins, working at 2.3 V ~ 3.6 V.
For VDD3P3, when ESP32 is transmitting signals, there may be a sudden increase in the current draw, causing
power rail collapse. Therefore, it is highly recommended to add a 10 μF capacitor to the power rail, which can work
in conjunction with the 1 μF capacitor(s).
Add a LC circuit on the VDD3P3 power rail to suppress high-frequency harmonics. The inductor’s rated current is
preferably 500 mA and above.
Place appropriate decoupling capacitors near the other analog power pins according to Figure ESP32 Schematic for
Analog Power Supply Pins.

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Fig. 5: ESP32 Schematic for VDD_SDIO Pin Powered by External Supply

Fig. 6: ESP32 Schematic for Analog Power Supply Pins

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3.1.3 RTC Power Supply

ESP32’s VDD3P3_RTC pin is the RTC and analog power pin. It is recommended to place a 0.1 μF decoupling
capacitor near this power pin in the circuit.
Note that this power supply cannot be used as a single backup power supply.
The schematic for the RTC power supply pin is shown in Figure ESP32 Schematic for RTC Power Supply Pin.

Fig. 7: ESP32 Schematic for RTC Power Supply Pin

3.2 Chip Power-up and Reset Timing

ESP32’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low.
When ESP32 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is
pulled up and the chip is enabled. Therefore, CHIP_PU needs to be asserted high after the 3.3 V rails have been
brought up.
To reset the chip, keep the reset voltage VIL_nRST in the range of (–0.3 ~ 0.25 × VDD) V. To avoid reboots caused
by external interferences, make the CHIP_PU trace as short as possible.
Figure ESP32 Power-up and Reset Timing shows the power-up and reset timing of ESP32.

Fig. 8: ESP32 Power-up and Reset Timing

Table Description of Timing Parameters for Power-up and Reset provides the specific timing requirements.

Table 1: Description of Timing Parameters for Power-up and Reset

Parameter Description Minimum (µs)
tSTBL Time reserved for the power rails to stabilize before the CHIP_PU 50
pin is pulled high to activate the chip
tRST Time reserved for CHIP_PU to stay below VIL_nRST to reset the 50
chip

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Chapter 3. Schematic Checklist

Attention:
• CHIP_PU must not be left floating.
• To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, specific
parameters should be adjusted based on the characteristics of the actual power supply and the power-up
and reset timing of the chip.
• If the user application has one of the following scenarios:
– Slow power rise or fall, such as during battery charging.
– Frequent power on/off operations.
– Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being
unable to boot correctly. In this case, additional designs need to be added, such as:
– Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0
V.
– Implementing reset functionality through a button or the main controller.

3.3 Flash and PSRAM

ESP32 requires in-package or off-package flash to store application firmware and data. In-package PSRAM or off-
package RAM is optional.

3.3.1 In-Package Flash and PSRAM

The tables list the pin-to-pin mapping between the chip and in-package flash/PSRAM. Please note that the following
chip pins can connect at most one flash and one PSRAM. That is to say, when there is only flash in the package, the
pin occupied by flash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM,
the pin occupied by PSRAM can only connect flash; when there are both flash and PSRAM, the pin occupied cannot
connect any more flash or PSRAM.

Table 2: Pin-to-Pin Mapping Between Chip and In-Package Flash

ESP32-U4WDH In-Package Flash (4 MB)
SD_DATA_1 IO0/DI
GPIO17 IO1/DO
SD_DATA_0 IO2/WP#
SD_CMD IO3/HOLD#
SD_CLK CLK
GPIO16 CS#
GND VSS
VDD_SDIO VDD

Table 3: Pin-to-Pin Mapping Between Chip and In-Package PSRAM

ESP32-D0WDR2-V3 In-Package PSRAM (2 MB)
SD_DATA_1 SIO0/SI
SD_DATA_0 SIO1/SO
SD_DATA_3 SIO2
SD_DATA_2 SIO3
SD_CLK SCLK
GPIO16 CE#
GND VSS
VDD_SDIO VDD

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3.3.2 Off-Package Flash and PSRAM

ESP32 supports up to 16 MB off-package flash and 8 MB off-package RAM. If VDD_SDIO is used to supply power,
make sure to select the appropriate off-package flash and RAM according to the power voltage on VDD_SDIO (1.8
V/3.3 V). It is recommended to add a zero-ohm series resistor on the SPI communication lines to lower the driving
current, reduce interference to RF, adjust timing, and better shield from interference.

3.4 Clock Source

ESP32 supports two external clock sources:
• External crystal clock source (Compulsory)
• RTC clock source (Optional)

3.4.1 External Crystal Clock Source (Compulsory)

The ESP32 firmware only supports 40 MHz crystal.

The circuit for the crystal is shown in Figure ESP32 Schematic for External Crystal. Note that the accuracy of the
selected crystal should be within ±10 ppm.

Fig. 9: ESP32 Schematic for External Crystal

Please add a series component (resistor or inductor) on the XTAL_P clock trace. Initially, it is suggested to use an
inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF performance, and the value should
be adjusted after an overall test.
The initial values of external capacitors C1 and C2 can be determined according to the formula:

C1 × C2
CL = + Cstray
C1 + C2
where the value of CL (load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to the
PCB’s stray capacitance. The values of C1 and C2 need to be further adjusted after an overall test as below:
1. Select TX tone mode using the Certification and Test Tool.
2. Observe the 2.4 GHz signal with a radio communication analyzer or a spectrum analyzer and demodulate it to
obtain the actual frequency offset.
3. Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load capacitance.
• When the center frequency offset is positive, it means that the equivalent load capacitance is small, and the
external load capacitance needs to be increased.
• When the center frequency offset is negative, it means the equivalent load capacitance is large, and the external
load capacitance needs to be reduced.

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Chapter 3. Schematic Checklist

• External load capacitance at the two sides are usually equal, but in special cases, they may have slightly different
values.

Note:
• Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable
performance within the operating temperature range, etc) may lead to the malfunction of ESP32, resulting in
a decrease of the RF performance.
• It is recommended that the amplitude of the crystal is greater than 500 mV.
• When Wi-Fi or Bluetooth connection fails, after ruling out software problems, you may follow the steps men-
tioned above to ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides
of the crystal.

3.4.2 RTC Clock Source (Optional)

ESP32 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC clock.
The external RTC clock source enhances timing accuracy and consequently decreases average power consumption,
without impacting functionality.
Figure ESP32 Schematic for 32.768 kHz Crystal shows the schematic for the external 32.768 kHz crystal.

Fig. 10: ESP32 Schematic for 32.768 kHz Crystal

Please note the requirements for the 32.768 kHz crystal:

• Equivalent series resistance (ESR) ≤ 70 kΩ.
• Load capacitance at both ends should be configured according to the crystal’s specification.
The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ≤ 10 MΩ). In general, you do not need to
populate the resistor.
When ESP32-D0WD-V3 connects to an external 32.768 kHz crystal, the parallel resistor must be populated. For
other ESP32 series chips, the resistor can be reserved.
If the RTC clock source is not required, then the pins for the 32.768 kHz crystal can be used as GPIOs.
The external signal can be input to 32K_XN. A capacitor larger than 200 pF should be added to the 32K_XP side.
Figure ESP32 Schematic for External Oscillator shows the schematic of the external signal.
The signal should meet the following requirements:

External signal Amplitude (Vpp, unit: V)

Sine wave or square wave 0.6 < Vpp < VDD

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Fig. 11: ESP32 Schematic for External Oscillator

3.5 RF

3.5.1 RF Circuit

ESP32’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit,
the antenna and the antenna matching circuit. Each part should meet the following requirements:
• For the RF traces on the PCB board, 50 Ω impedance control is required.
• For the chip matching circuit, it must be placed close to the chip. A CLC structure is preferred.

– The CLC structure is mainly used to adjust the impedance point and suppress harmonics, and
a set of LC can be added if space permits.
– The RF matching circuit is shown in Figure ESP32 Schematic for RF Matching.
• For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic
impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust
the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to
be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.

Fig. 12: ESP32 Schematic for RF Matching

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3.5.2 RF Tuning

The RF matching parameters vary with the board, so the ones used in Espressif modules could not be applied directly.
Follow the instructions below to do RF tuning.
Figure ESP32 RF Tuning Diagram shows the general process of RF tuning.

Fig. 13: ESP32 RF Tuning Diagram

The initial value of the parameters in the matching network can be 0 Ω. The recommended value of S11 is 25+j0.
The recommended central frequency is 2442 MHz.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD
protection devices near the antenna.

Note: If RF function is not required, then the RF pin can be left floating.

3.6 UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0,
please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available
GPIO by software configurations. For these interfaces, it is also recommended to add a series resistor to the TX line
to suppress harmonics.
When using the AT firmware, please note that the UART GPIO is already configured (refer to AT Firmware Down-
load). It is recommended to use the default configuration.

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3.7 Strapping Pins

At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to load
the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal
function pins.
All the information about strapping pins is covered in ESP32 Series Datasheet > Section Strapping Pins. In this
document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO0 and GPIO2 controls the boot mode. See Table Boot Mode
Control.

Table 4: Boot Mode Control

Boot Mode GPIO0 GPIO2
Default Config 1 0
SPI Boot 1 Any value
Joint Download Boot1 0 0

Signals applied to the strapping pins should have specific setup time and hold time. For more information, see Figure
Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.

Fig. 14: Setup and Hold Times for Strapping Pins

Table 5: Description of Timing Parameters for Strapping Pins

Parameter Description Minimum (ms)
tSU Time reserved for the power rails to stabilize before the chip enable 0
pin (CHIP_PU) is pulled high to activate the chip.
tH Time reserved for the chip to read the strapping pin values after 3
CHIP_PU is already high and before these pins start operating as
regular IO pins.

Attention: Do not add high-value capacitors at GPIO0, otherwise, the chip may not boot successfully.

1 Joint Download Boot mode supports the following download methods:

• UART Download Boot
• SDIO Download Boot

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Chapter 3. Schematic Checklist

3.8 GPIO
The pins of ESP32 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configurations,
whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about IO
MUX and GPIO matrix, please refer to ESP32 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.
Some peripheral signals have already been routed to certain GPIO pins, while some can be routed to any available
GPIO pins. For details, please refer to ESP32 Series Datasheet > Section Peripheral Pin Configurations.
When using GPIOs, please:

• Pay attention to the states of strapping pins during power-up.

• Pay attention to the default configurations of the GPIOs after reset. The default configurations can be found
in Table IO MUX Pin Functions. It is recommended to add a pull-up or pull-down resistor to pins in the
high-impedance state or enable the pull-up and pull-down during software initialization to avoid extra power
consumption.
• Avoid using the pins already occupied by flash/PSRAM.

Table 6: IO MUX Pin Functions

GPIO Pin Func- Func- Func- Func- Func- Func- Reset
Name tion tion tion tion tion tion
0 1 2 3 4 5
0 GPIO0 GPIO0 CLK_OUT1 GPIO0 – – EMAC_TX_CLK
3
1 U0TXD U0TXD CLK_OUT3 GPIO1 – – EMAC_RXD2 3
2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0– 2
3 U0RXD U0RXD CLK_OUT2 GPIO3 – – – 3
4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1EMAC_TX_ER2
5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 – EMAC_RX_CLK
3
6 SD_CLK SD_CLK SPI- GPIO6 HS1_CLK U1CTS – 3
CLK
7 SD_DATA_0
SD_DATA0SPIQ GPIO7 HS1_DATA0 U2RTS – 3
8 SD_DATA_1
SD_DATA1SPID GPIO8 HS1_DATA1 U2CTS – 3
9 SD_DATA_2
SD_DATA2SPIHD GPIO9 HS1_DATA2 U1RXD – 3
10 SD_DATA_3
SD_DATA3SPIWP GPIO10 HS1_DATA3 U1TXD – 3
11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMDU1RTS – 3
12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2EMAC_TXD3 2
13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3EMAC_RX_ER2
14 MTMS MTMS HSPI- GPIO14 HS2_CLK SD_CLK EMAC_TXD2 3
CLK
15 MTDO MTDO HSPICS0 GPIO15 HS2_CMDSD_CMD EMAC_RXD3 3
16 GPIO16 GPIO16 – GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT1
17 GPIO17 GPIO17 – GPIO17 HS1_DATA5 U2TXD EMAC_CLK_1801
18 GPIO18 GPIO18 VSPI- GPIO18 HS1_DATA7 – – 1
CLK
19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS – EMAC_TXD0 1
21 GPIO21 GPIO21 VSPIHD GPIO21 – – EMAC_TX_EN1
22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS – EMAC_TXD1 1
23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE – – 1
25 GPIO25 GPIO25 – GPIO25 – – EMAC_RXD0 0
26 GPIO26 GPIO26 – GPIO26 – – EMAC_RXD1 0
27 GPIO27 GPIO27 – GPIO27 – – EMAC_RX_DV0
32 32K_XP GPIO32 – GPIO32 – – – 0
33 32K_XN GPIO33 – GPIO33 – – – 0
34 VDET_1 GPIO34 – GPIO34 – – – 0
35 VDET_2 GPIO35 – GPIO35 – – – 0
continues on next page

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Chapter 3. Schematic Checklist

Table 6 – continued from previous page

GPIO Pin Func- Func- Func- Func- Func- Func- Reset
Name tion tion tion tion tion tion
0 1 2 3 4 5
36 SEN- GPIO36 – GPIO36 – – – 0
SOR_VP
37 SEN- GPIO37 – GPIO37 – – – 0
SOR_CAPP
38 SEN- GPIO38 – GPIO38 – – – 0
SOR_CAPN
39 SEN- GPIO39 – GPIO39 – – – 0
SOR_VN

Reset:
• 0: IE=0 (input disabled)
• 1: IE=1 (input enabled)
• 2: IE=1, WPD=1 (input enabled, pull-down resistor)
• 3: IE=1, WPU=1 (input enabled, pull-up resistor)

3.9 ADC
Please add a 0.1 μF filter capacitor between ESP pins and ground when using the ADC function to improve accuracy.
When RTC peripherals (SAR ADC1/SAR ADC2/AMP) is powered on, the inputs of GPIO36 (SENSOR_VP) and
GPIO39 (SENSOR_VN) will be pulled down for approximately 80 ns. Therefore, it is recommended to use SEN-
SOR_VP and SENSOR_VN as ADC pins.
If SENSOR_VP and SENSOR_VN are used as GPIOs in the design, while ADC is supported by other pins, then
software should disregard the glitch. Optionally, make SENSOR_VP and SENSOR_VN active high pins.
ADC1 is recommended over ADC2 as the latter cannot be used when Wi-Fi function is enabled.
The calibrated ADC results after hardware calibration and software calibration are shown in the list below. For higher
accuracy, you may implement your own calibration methods.

• When ATTEN=0 and the effective measurement range is 100 ~ 950 mV, the total error is ±23 mV.
• When ATTEN=1 and the effective measurement range is 100 ~ 1250 mV, the total error is ±30 mV.
• When ATTEN=2 and the effective measurement range is 150 ~ 1750 mV, the total error is ±40 mV.
• When ATTEN=3 and the effective measurement range is 150 ~ 2450 mV, the total error is ±60 mV.

3.10 External Capacitor

Figure ESP32 Schematic for External Capacitor shows the schematic of components connected to pin47 CAP2 and
pin48 CAP1.
C5 (10 nF) that connects to CAP1 should be of 10% tolerance and is required for proper operation of ESP32.
RC circuit between CAP1 and CAP2 pins may be omitted under certain conditions. This circuit is used when entering
Deep-sleep mode. During this process, to minimize power consumption, the voltage to power ESP32 internals is
dropped from 1.1 V to around 0.7 V. The RC circuit is used to minimize the period of the voltage drop. If removed,
this process will take longer and the power consumption in Deep-sleep will be higher. If particular application of
ESP32 is not using Deep-sleep mode, or power consumption is less critical, then this circuit is not required.

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Fig. 15: ESP32 Schematic for External Capacitor

3.11 SDIO
There are two sets of GPIOs (slot0 and slot1) that can be assigned to SDIO on ESP32, as shown in Table SDIO Pin
Configuration. When ESP32 works as an SDIO host or slave, connect GPIOs in slot1 to signal lines.

Table 7: SDIO Pin Configuration

CMD CLK DAT0 DAT1 DAT2 DAT3 Note
Slot0 GPIO11 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 Used to connect flash by de-
fault. Not recommended for
other use.
Slot1 GPIO15 GPIO14 GPIO2 GPIO4 GPIO12 GPIO13 Multiplexed with JTAG, touch,
EMAC, and strapping func-
tions.

When connecting GPIOs in slot1 to signal lines, please note:

• When ESP32 works as an SDIO host, it is recommended to add pull-up resistors on the used pins. Unused
pins can be utilized for other purposes.
• When ESP32 works as an SDIO slave, add pull-up resistors on all pins, regardless of whether these pins are
used for SDIO or not. Unused pins cannot be used for other purposes.
For more information on SDIO configuration, please refer to API References.

3.12 Touch Sensor

When using the touch function, it is recommended to populate a zero-ohm series resistor at the chip side to reduce
the coupling noise and interference on the line, and to strengthen the ESD protection. The recommended resistance
is from 470 Ω to 2 kΩ, preferably 510 Ω. The specific value depends on the actual test results of the product.

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Chapter 4

PCB Layout Design

This chapter introduces the key points of how to design an ESP32 PCB layout using an ESP32 module (see Figure
ESP32 Reference PCB Layout) as an example.

Fig. 1: ESP32 Reference PCB Layout

4.1 General Principles of PCB Layout

It is recommended to use a four-layer PCB design:
• Layer 1 (TOP): Signal traces and components.
• Layer 2 (GND): No signal traces here to ensure a complete GND plane.

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Chapter 4. PCB Layout Design

• Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal. Route power traces and
a few signal traces on this layer, provided that there is a complete GND plane under the RF and crystal.
• Layer 4 (BOTTOM): Route a few signal traces here. It is not recommended to place any components on this
layer.
A two-layer PCB design can also be used:
• Layer 1 (TOP): Signal traces and components.
• Layer 2 (BOTTOM): Do not place any components on this layer and keep traces to a minimum. Please make
sure there is a complete GND plane for the chip, RF, and crystal.

4.2 Positioning a Module on a Base Board

If module-on-board design is adopted, attention should be paid while positioning the module on the base board. The
interference of the baseboard on the module’s antenna performance should be minimized.
It is suggested to place the module’s on-board PCB antenna outside the base board, and the feed point of the
antenna closest to the board. In the following example figures, positions with mark ✓ are strongly recommended,
while positions without a mark are not recommended.

Fig. 2: Placement of ESP32 Modules on Base Board (antenna feed point on the right)

If the PCB antenna cannot be placed outside the board, please ensure a clearance of at least 15 mm around the antenna
area (no copper, routing, or components on it), and place the feed point of the antenna closest to the board. If there
is a base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna. Figure
Keepout Zone for ESP32 Module’s Antenna on the Base Board shows the suggested clearance for modules whose
antenna feed point is on the right.
When designing an end product, attention should be paid to the interference caused by the housing of the antenna
and it is recommended to carry out RF verification. It is necessary to test the throughput and communication signal
range of the whole product to ensure the product’s actual RF performance.

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Fig. 3: Keepout Zone for ESP32 Module’s Antenna on the Base Board

4.3 Power Supply

Figure ESP32 Power Traces in a Four-layer PCB Design shows the overview of the power traces in a four-layer PCB
design.

Fig. 4: ESP32 Power Traces in a Four-layer PCB Design

4.3.1 General Guidelines

• Four-layer PCB design is preferred.

• The power traces should be routed on the inner third layer whenever possible.
• Vias are required for the power traces to go through the layers and get connected to the pins on the top layer.
There should be at least two vias if the main power traces need to cross layers. The drill diameter on other
power traces should be no smaller than the width of the power traces.

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Chapter 4. PCB Layout Design

• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine ground
vias.
• If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to
employ a square grid on the EPAD, cover the gaps with solder paste, and place ground vias in the gaps, as
shown in Figure ESP32 Power Traces in a Four-layer PCB Design. This can avoid chip displacement caused
by tin leakage and bubbles when soldering the module EPAD to the substrate.

4.3.2 3.3 V Power Layout

The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure ESP32 Power Traces in a Four-layer
PCB Design.
The 3.3 V power layout should meet the following guidelines:
• The ESD protection diode is placed next to the power port (circled in red in Figure ESP32 Power Traces in a
Four-layer PCB Design). The power trace should have a 10 µF capacitor on its way before entering into the
chip, and a 0.1 or 1 µF capacitor could also be used in conjunction. After that, the power traces are divided
into several branches using a star-shaped topology, which reduces the coupling between different power pins.
Note that all decoupling capacitors should be placed close to the corresponding power pin, and ground vias
should be added close to the capacitor’s ground pad to ensure a short return path.
• In Figure ESP32 Power Traces in a Four-layer PCB Design, the 10 µF capacitor is shared by the analog power
supply VDD3P3, and the power entrance since the analog power is close to the chip power entrance. If the
chip power entrance is not near VDD3P3, it is recommended to add a 10 µF capacitor to both the chip power
entrance and VDD3P3. Also, reserve two 1 µF capacitors if space permits.
• The width of the main power traces should be no less than 25 mil. The width of VDD3P3 power traces should
be no less than 20 mil. The recommended width of other power traces is 10 mil.

4.3.3 Analog Power Layout

The analog power layout should meet the following guidelines:

• VDD3P3 analog power supply should be surrounded by ground copper. It is required to add GND isolation
between VDD3P3, power trace and the surrounding GPIO and RF traces, and place vias whenever possible.

4.3.4 Two-layer PCB Design

In a two-layer PCB design, the 3.3 V power traces are routed as shown labelled with VDD33 in Figure ESP32 Power
Traces in a Two-layer PCB Design.
The power layout in a two-layer PCB design should meet the following guidelines:
• In contrast to the design practices for a four-layer PCB design, the power traces in a two-layer PCB design
should be routed on the top layer.
• Reduce the size of the thermal pad in the center of the chip. Route the power traces between the thermal pad
and its surrounding signal pins. Employ vias only when the power traces have to reach the bottom layer.
• Maintain a complete ground plane while reducing the surrounding area of the power traces.
• Other good practices for routing power traces in four-layer PCB designs still apply to two-layer PCB designs.

4.4 Crystal
Figure ESP32 Crystal Layout (with Keep-out Area on Top Layer) shows a reference PCB layout where the crystal is
connected to the ground through vias and a keep-out area is maintained around the crystal on the top layer for ground
isolation.
The layout of the crystal should follow the guidelines below:

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Chapter 4. PCB Layout Design

Fig. 5: ESP32 Power Traces in a Two-layer PCB Design

Fig. 6: ESP32 Crystal Layout (with Keep-out Area on Top Layer)

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Chapter 4. PCB Layout Design

• Ensure a complete GND plane for the RF, crystal, and chip.
• The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least
2.7 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers. The
clock traces should not intersect with each other.
• Components in series to the crystal trace should be placed close to the chip side.
• The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the
clock trace, but not connected directly to the series components. This is to make sure the ground pad of the
capacitor is close to that of the crystal.
• Do not route high-frequency digital signal traces under the crystal. It is best not to route any signal trace under
the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away
from the clock trace as possible, and the two sides of the clock trace should be surrounded by grounding copper.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interfer-
ence, for example large inductance component, and ensure that there is a clean large-area ground plane around
the crystal.

4.5 RF

4.5.1 RF Layout on Four-layer PCB

The RF trace is routed as shown highlighted in pink in Figure ESP32 RF Layout in a Four-layer PCB Design.

Fig. 7: ESP32 RF Layout in a Four-layer PCB Design

The RF layout should meet the following guidelines:

• A π-type matching circuit should be added to the RF trace and placed close to the chip, in a zigzag.
• The RF trace should have a 50 Ω characteristic impedance. The reference plane is the second layer. For
designing the RF trace at 50 Ω impedance, you could refer to the PCB stack-up design shown below.
• Add a stub to the ground at the ground pad of the first matching capacitor to suppress the second harmonics.
It is preferable to keep the stub length 15 mil, and determine the stub width according to the PCB stack-up so
that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the stub via to the
third layer, and maintain a keep-out area on the first and second layers. The trace highlighted in Figure ESP32
Stub in a Four-layer PCB Design is the stub. Note that a stub is not required for package types above 0201.
• The RF trace should have a consistent width and not branch out. It should be as short as possible with dense
ground vias around for interference shielding.
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should
be routed at a 135° angle, or with circular arcs if trace bends are required.
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR SDRAM, high-frequency clocks, etc. In

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Chapter 4. PCB Layout Design

Fig. 8: ESP32 PCB Stack-up Design

Fig. 9: ESP32 Stub in a Four-layer PCB Design

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Chapter 4. PCB Layout Design

addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header pins,
etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded by ground
copper and ground vias.

4.5.2 RF Layout on Two-layer PCB

In a two-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure ESP32 RF Layout in a Two-
layer PCB Design. The width of the RF trace should be greater than that of the RF trace in a four-layer board and
is normally over 20 mil. The actual width depends on the impedance formula where impedance-relevant parameters
may vary depending on the number of PCB layers.
Other good practices for routing RF traces in four-layer PCB designs still apply to two-layer board designs.

Fig. 10: ESP32 RF Layout in a Two-layer PCB Design

4.6 Flash and PSRAM

The layout for flash and PSRAM should follow the guidelines below:

• Place the zero-ohm series resistors on the SPI lines close to the chip.
• Route the SPI traces on the inner layer (e.g., the third layer) whenever possible, and add ground copper and
ground vias around the clock and data traces of SPI separately.
• Place the 0.1 μF capacitor to ground at the VDD_SPI close to corresponding flash and PSRAM power pins.
Figure ESP32 Flash and PSRAM Layout shows an example of flash (U3) and PSRAM (U4) layout.

4.7 External RC
External resistors and capacitors should be placed close to the chip pins, and there should be no vias around the traces.
Please ensure that 10 nF capacitors are placed close to the pins.

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Chapter 4. PCB Layout Design

Fig. 11: ESP32 Flash and PSRAM Layout

4.8 UART
Figure ESP32 UART Layout shows the UART layout.

Fig. 12: ESP32 UART Layout

The UART layout should meet the following guidelines:

• The series resistor on the U0TXD trace needs to be placed close to the chip side and away from the crystal.
• The U0TXD and U0RXD traces on the top layer should be as short as possible.
• The UART trace should be surrounded by ground copper and ground vias stitching.

4.9 SDIO
The SDIO layout should follow the guidelines below:
• Since SDIO traces have a high speed, it is necessary to control the parasitic capacitance.
• The trace length for SDIO_CMD and SDIO_DATA0 ~ SDIO_DATA3 should be 3 mil longer or shorter than
the trace length for SDIO_CLK. If necessary, use serpentine routing.

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Chapter 4. PCB Layout Design

• It is better to surround the SDIO_CLK trace with ground copper. The path from SDIO GPIOs to the master
SDIO interface should be as short as possible and no more than 2500 mil or even 2000 mil.
• Do not place SDIO traces across planes.

4.10 Touch Sensor

ESP32 offers up to 10 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or
proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows to use
touch pads with smaller area to implement the touch detection function. You can also use the touch panel array to
detect a larger area or more test points.
Figure ESP32 Typical Touch Sensor Application depicts a typical touch sensor application.

Fig. 13: ESP32 Typical Touch Sensor Application

To prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor system, the
following factors should be taken into account.

4.10.1 Electrode Pattern

The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a human fin-
gertip are commonly applied. Large size or irregular shape might lead to incorrect responses from nearby electrodes.
Figure ESP32 Electrode Pattern Requirements shows the proper and improper size or shape of electrode. Please note
that the examples illustrated in the figure are not of actual scale. It is suggested to use a human fingertip as reference.

4.10.2 PCB Layout

Figure ESP32 Sensor Track Routing Requirements illustrates the general guidelines to routing traces. Specifically,
• The trace should be as short as possible and no longer than 300 mm.
• The trace width (W) can not be larger than 0.18 mm (7 mil).
• The alignment angle (R) should not be less than 90°.
• The trace-to-ground gap (S) should be in the range of 0.5 mm to 1 mm.
• The electrode diameter (D) should be in the range of 8 mm to 15 mm.
• Hatched ground should be added around the electrodes and traces.
• The traces should be isolated well and routed away from that of the antenna.

Note: For more details on the hardware design of the touch sensor, please refer to Touch Sensor Application Note.

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Chapter 4. PCB Layout Design

Fig. 14: ESP32 Electrode Pattern Requirements

Fig. 15: ESP32 Sensor Track Routing Requirements

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Chapter 4. PCB Layout Design

4.11 Typical Layout Problems and Solutions

4.11.1 1. The voltage ripple is not large, but the TX performance of RF is rather poor.

Analysis: The voltage ripple has a strong impact on the RF TX performance. It should be noted that the ripple must
be tested when ESP32 is in the normal working mode. The ripple increases when the power gets high in a different
mode.
Generally, the peak-to-peak value of the ripple should be <80 mV when ESP32 sends MCS7@11n packets, and <120
mV when ESP32 sends 11 MHz@11b packets.
Solution: Add a 10 μF filter capacitor to the branch of the power trace (the branch powering the chip’s analog
power pin). The 10 μF capacitor should be as close to the analog power pin as possible for small and stable voltage
ripples.

4.11.2 2. When ESP32 sends data packages, the voltage ripple is small, but RF TX per-
formance is poor.

Analysis: The RF TX performance can be affected not only by voltage ripples, but also by the crystal itself. Poor
quality and big frequency offsets of the crystal decrease the RF TX performance. The crystal clock may be corrupted
by other interfering signals, such as high-speed output or input signals. In addition, high-frequency signal traces,
such as the SDIO traces and UART traces under the crystal, could also result in the malfunction of the crystal.
Besides, sensitive components or radiating components, such as inductors and antennas, may also decrease the RF
performance.
Solution: This problem is caused by improper layout for the crystal and can be solved by re-layout. Please refer to
Section Crystal for details.

4.11.3 3. When ESP32 sends data packages, the power value is much higher or lower than
the target power value, and the EVM is relatively poor.

Analysis: The disparity between the tested value and the target value may be due to signal reflection caused by
the impedance mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance
mismatch will affect the working state of the internal PA, making the PA prematurely access the saturated region in
an abnormal way. The EVM becomes poor as the signal distortion happens.
Solution: Match the antenna’s impedance with the π-type circuit on the RF trace, so that the impedance of the
antenna as seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.

4.11.4 4. TX performance is not bad, but the RX sensitivity is low.

Analysis: Good TX performance indicates proper RF impedance matching. Poor RX sensitivity may result from
external coupling to the antenna. For instance, the crystal signal harmonics could couple to the antenna. If the TX
and RX traces of UART cross over with RF trace, they will affect the RX performance, as well. If there are many
high-frequency interference sources on the board, signal integrity should be considered.
Solution: Keep the antenna away from crystals. Do not route high-frequency signal traces close to the RF trace.
Please refer to Section RF for details.

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Chapter 5

Hardware Development

5.1 ESP32 Modules

For a list of ESP32 modules please check the Modules section on Espressif’s official website.
To review module reference designs please check the Documentation section on Espressif’s official website.

5.2 ESP32 Development Boards

For a list of the latest designs of ESP32 boards please check the Development Boards section on Espressif’s official
website.

5.3 Download Guidelines

You can download firmware to ESP32 via UART.
To download via UART:
1. Before the download, make sure to set the chip or module to Joint Download Boot mode, according to Table
Boot Mode Control.
2. Power up the chip or module and check the log via the UART0 serial port. If the log shows “waiting for
download”, the chip or module has entered Joint Download Boot mode.
3. Download your firmware into flash via UART using the Flash Download Tool.
4. After the firmware has been downloaded, pull GPIO0 high or leave it floating to make sure that the chip or
module enters SPI Boot mode.
5. Power up the chip or module again. The chip will read and execute the new firmware during initialization.

Note:
• It is advised to download the firmware only after the “waiting for download”log shows via serial ports.
• Serial tools cannot be used simultaneously with the Flash Download Tool on one com port.

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Chapter 5. Hardware Development

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Chapter 6

Related Documentation and Resources

• Chip Datasheet (PDF)

• Technical Reference Manual (PDF)
• Chip Errata (PDF)
• Chip Variants
• Modules
• Development Boards
• Espressif KiCad Library
• ESP Product Selector
• Regulatory Certificates
• User Forum (Hardware)
• Technical Support

35
Chapter 6. Related Documentation and Resources

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Chapter 7

Glossary

The glossary contains terms and acronyms that are used in this document.

Term Description
CLC Capacitor-Inductor-Capacitor
DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory
ESD Electrostatic Discharge
LC Inductor-Capacitor
PA Power Amplifier
RC Resistor-Capacitor
RTC Real-Time Clock
Zero-ohm resistor A zero-ohm resistor is a placeholder on the circuit so that another higher ohm resistor can
replace it, depending on design cases.

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Chapter 7. Glossary

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Chapter 8

Revision History

8.1 ESP Hardware Design Guidelines v1.0

This is the first version of the ESP Hardware Design Guidelines in HTML format. During the migration from PDF
to HTML format, minor updates, improvements, and clarifications were made throughout the documentation.
If you would like to check previous versions of the document, please submit documentation feedback.

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Chapter 8. Revision History

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Chapter 9

Disclaimer and Copyright Notice

Information in this document, including URL references, is subject to change without notice.
All third party’s information in this document is provided as is with no warranties to its authenticity and accuracy.
No warranty is provided to this document for its merchantability, non-infringement, fitness for any particular purpose,
nor does any warranty otherwise arising out of any proposal, specification or sample.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this doc-
ument is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are
granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark
of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective
owners, and are hereby acknowledged.

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