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Power Analysis and Implementation of the 8 - bit Toggle Clock Gated ALU

Article in International Journal of Computer Applications · June 2016

DOI: 10.5120/ijca2016910202

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.8, June 2016

Power Analysis and Implementation of the 8 - bit Toggle

Clock Gated ALU
Vandana Prajapati Uday Panwar
Department of Electronics and Communication Department of Electronics and Communication
Sagar Institute of Research & Technology Sagar Institute of Research & Technology
Bhopal, India Bhopal, India

ABSTRACT Dynamic power is also on-off power defined as: P dynamic =

Power dissipation is major drawback in the digital sequential α * C *f (2) V2In equation 2, α is the switching activity, C is
circuit design of low power electronic devices. Clock signal is capacitance, V is supply voltage and f is frequency. Hence,
one input which is common for all the sequential circuits. The power optimization techniques can be tested at different levels
clock signal has major power dissipation at high frequencies. such as logic level, architecture level and design level etc.
The clock gating technique can be implemented at Dynamic power loss is a major factor in all the sequential
architectural level to reduce the power dissipation at dynamic circuits. It consumes upto 60% of the total power.
and clock power level. Aim of this paper is to analyze,
implement and comparison between various clock gating
2. RELATED WORK
techniques for a 8-bit ALU on a artix7,45 nm technology with Dynamic power dissipation can be reduced by clock gating
xc7a100t-3csg324 , xc6slx41-1Ltqg144 spartan6 with 40nm techniques at different levels. According to reference [2] AND
FPGA board. The two clock gating techniques are proposed gate based clock gating circuit for three bit full-adder system,
and used in the design are namely: T-flip flop and use of latch. the clock gate enabled function can be identified by Boolean
This technique is implemented by using Xilinx 14.1. T flip analysis of logic input for all adders. According to reference
flop is best for this design as it requires less number of gate [1] clock gating is implemented in various techniques for
counts and also less area. Operation using11 instructions are smaller circuits called D flip-flop and on large circuits called
performed in the proposed design. This technique is designed 16 bit register. The evaluation in percentage of dynamic
through T Flip-Flop based on gated clock ALU at RTL level. power exclusively for clock power is verified for different
At different operating frequencies of 100MHZ, 200MHZ, device operating frequencies. According to reference [3] flip-
300MHZ, 400MHZ & 500MHZ, the dissipated power is 5mw, flop is used to design 10 bits binary counter and 14 bits
9mw, 14mw, 19mw,24mw respectively. consecutive approximation register. A new clock gated flip-
flop is presented which reduces the consumption of clock
Keywords signal switching power. It conducts with no redundant clock
Sequential circuit, T-FF, Clock- Gating, Implementation, cycles and has reduced number of transistor to minimize the
Instruction, Gated ALU over head and to make it suitable for data signal with higher
on-off activity. As per reference [4] practical outcomes based
1. INTRODUCTION on the toggling activity, correlation of flip-flop and their
In the world of digital electronics, high performance and low physical position adjacency constraint in the layout has been
power electronic devices are dominant which lead to achieved. The arithmetic and logic units are coexistent circuit
continuous research on low power design techniques. This is which is incorporated into the results obtained from the
the basic need of any digital signal processing device in implementation. Section VI and IX will conclude the results
simple applications such as data acquisition to the complex and discussions carried out.
ones namely: network-on-chip system, memory re/wr process,
Counters and resistor. Device which performs the arithmetic 3. CLOCK GATING
and logical operations require higher power than the other Clock gating, is one of the most well-known low-power
peripherals. Thus the power reduction in the Device is the real consumption techniques. CG design is very effective for
challenge. The research on minimizing the power of the ALU reducing the power consumption in digital circuits and also
is spreading out and various low Power dissipation VLSI circuits. This CG design is implemented to reduce
approaches are being proposed. Power dissipation has unwanted transition of clock pulse which in turn reduces the
become the bottle neck in gating high efficiency and smaller dynamic power loss and also the power loss from the load
size of appliances. Thus the need for the research for capacitor switching. The goal of this technique is to disable or
achieving lower power dissipation and high speed VLSI suppress transitions from propagating to parts of the clock
Systems. Power dissipation is sum of the issues namely the lane (i.e., clock network & flip-flops) under a certain
[1] short condition computed by clock-gating circuits. CG is illustrated
in figure 1 clock gating, which hinder the clock signal in the
Circuit power, dynamic power and leakage power which are idle condition associated with each sequential logical unit.
influenced by frequency, supply voltage, The clock signal is computed by function Fcg. is the system
clock and CLKG the gated clock of the functional unit.
Switching activity and load capacitor charging and
discharging process. The power dissipation equation is given
as:
P = Pdynamic + Pshortcircuit + Pleakage

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.8, June 2016

4. FLOWCHART OF PROPOSED
FUNCTIONL WORK
FCG CG UNIT In this design pulse enable concept is an additive to clock
gating techniques by which clock signal remains sleepy
CLK G whenever enable pulse equals zero.

Fig 1: Clock Gated Function START

Clock gating (CG) is the technique which prevents the clock
YES
input to the functional modules which are idle. This implies
turning off the clock if not needed. There are various clock RESET
gating styles [5] used to optimize the power.
CLK
To name a few: latched free CG, latched based CG, flip-flop
based CG etc.[1] [2] In the latch free CG, the clock input to
the functional block is provided through the basic logic gates ENABLE
such as: AND, NAND, or NOR gate. The basic block
representation is as shown in the figure2.

YES NO
A B

8 BIT >Enable logic >Logic clock

SLE
operation from transfer (logic
E (op code select) clock to logic
ALU
CLK GATED unit)> Gated clock
CLK
> Set operation Tran.data byte to
active flag logic unit

Fig 2: Latch Free Clock Gating.

The problem with this technique is: If enable signal goes
inactive in between the clock pulse then gated clock gets Logic unit design under testing
terminated before its life time.

3.1 Latch Based Clock Gating

The latch-based clock gating technique adds a level-sensitive If reset-1-=Y
latch to the design and holds the EN signal from the active 0
peak of the clock till the dormant of the peak clock. Since the SOAF
For 0 - false
latch takes the state of the EN signal and keep stable it until
the entire clock has been produced, the EN signal need only
be stable around the rising peak of the gated clock, like as in
the traditional gated design style (figure 3). Y-OUTPUT

In some applications, latch-based designs are applied to D Flip

Flop (DFF)–based designs.[5][6] The basic concept is that a Fig 4: Flow Chart of Design
D-FF can be split into 2 latches, and each one is clocked with
a separate clock signal.
5. IMPLEMANTATION OF CLOCK
GATED ALU
The clock gating is simple to design. A simple AND gate is
employed to generate the gated clock. This technique (figure 5.1 T- Flip Flop Based Clock Gating
4) is glitch-free because the control signal, generated when There are many techniques that are implemented to generate a
EN is high, is stable and remains stable. clock gating signal flip flop has a feature to generate the clock
gating signal. T flip flop produce logic 1 at 0 signals which is
the foremost advantages to lower the power loss .It generates
A B clock gated signal at 0 logic that reduces the power loses
E SLE related to clock transition. The implementation of clock gating
D 8 BIT
signal is shown in figure5.
CLK Q ALU
Q Q
CLK

Fig 3: D-Flip Flop Latch Based ALU.

CLK Q

CLK
Q
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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.8, June 2016

A B
5.2 Generation of Gated Clock With D-Flip
E SLE Flop
T 8 BIT D flip flop is most frequently used to produce gated clock
pulse. This design provides negative and positive latch based
Clk Q ALU gated clock generation with low statics, dynamic and total
power consumption.
CLK
CLK Q

GC
Fig 5: Gated Clock With T Flip Flop.
T flip-flop is a sequential circuit where primarily the clock is
generated by T flip-flop which is applied to the ALU. In
below fig. when enable (T) is equal to 0, T-Flip-flop have
high value in its output (Q) which is applied to AND gate to
produce clock signal for ALU.
Table 1. Device Utilization with T-FF Based GC
RESOURCE USED AVAILABLE UTOLIZATION
Slice LUT’S 4 46,560 1%
Fig 8: Gated ALU with D Flip Flop
Used logic 4 46,560 1%
A low gated clock design is implemented with Spartan 6,
Use as 0 16,120 0 40nm FPGA technology .RTL view of D flip flop based
memory design is presented below figure 9.
Registers 5 93,120 1%
slice

5.1.1 RTL View Of Gated ALU

Below fig. shows architecture of clock gated ALU. RTL
schematic has been obtained from vertex-6 FPGA family
having 40nm technology.

Fig 9: Internal View of D-FF ALU

6. RESULT
6.1 Power Consumed In T- Flip Flop Based
ALU
The power consumption in gated ALU is carried out with
Fig 6: RTL View Of Gated ALU With T Flip Flop. artix7- xc7a100t-3csg324 with 45nm FPGA technology and
xc6slx41-1Ltqg144 Spartan 6 with 40 nm technology. Here
also static and dynamic power consumption is calculated at
60c & 50c temperature using both technologies. The table
shows total power consumed during overall operation in the
ALU by using clock gating.
Table 2.Total Power Consumption In Gated ALU At
Artix7
Clock Frequency Static Dynamic Total
signal(ns) (MHZ) power Power Power
1 500 42mw 24mw 66mw
2 400 42mw 19mw 61mw
3 300 43mw 14mw 57mw
5 200 43mw 9mw 52mw
Fig 7: Internal View of Gated ALU 10 100 42mw 5mw 47mw

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.8, June 2016

Table 3.Total Power Consumption In Gated ALU At 60c analysis of an 8-bit ALU is implemented for various resource
With Artix7. types namely: the clock power, dynamic power, signal power,
IO power and the total power.
Clock Frequency Static Dynamic Total
power The enable input EN of the T flip flop is initially made HIGH
signal(ns) (MHZ) Power Power and it generates half frequency signal of input signal. Then
1 500 82mw 24mw 106mw enable is made low which maintain the previous stage of
output. Finally the gated clock is applied to the logical and
2 400 92mw 19mw 111mw the arithmetic unit. The output is obtained at the Logic out
stage. The clock pulse remains constant till next operation is
3 300 102mw 14mw 116mw
select to be executed.
5 200 111mw 9mw 120mw
10 100 120mw 5mw 125mw

6.2 Measurement of Static and Dynamic

Power Consumption By Spartan
6,xc6slx41 -1Ltqg144 Technology With
40nm FPGA.
Table 4.Total Power Consumption In Gated ALU With
Spartan 6.
Clock Frequency Static Dynamic Total
signal(ns) (MHZ) power Power Power
1 500 12mw 30mw 42mw Fig 10: Simulated Result With T Flip Flop Gated ALU
2 400 12mw 24mw 36mw
3 300 11mw 18mw 29mw
70
5 200 12mw 12mw 23mw 60
10 100 12mw 6mw 17mw 50
40
Table 5. Power Consumption at 50c With Spartan 6. 30 Airtex7
20 spartan6
Clock Frequency Static Dynamic Total
10
signal(ns) (MHZ) power power Power
0 sp-6 at 50C
1 500 18mw 30mw 48mw
2 400 20mw 24mw 42mw
3 300 18mw 18mw 36mw
5 200 17mw 12mw 29mw
10 100 17mw 6mw 23mw

6.3 Power Consumption in D-FF Based Fig 11: Graphic Representations Of Total Power At
ALU Various Technology Level With T- Flip Flop Based ALU.
Power consumption analysis also done for D-FF based
design. In this design total power optimization during a
complete instruction is performed with the help x- power 8. COMPARISION IN VARIOUS
analyzer. The total power including static and dynamic power CLOCKS GATING TECHNIQUE
consumption is presented in the table VI.
Table 4. show the dynamic power comparison in various clock
Table 5. Power consumption in D-FF Based ALU gating techniques which shows improved results as we
integrate technology and implement new design.
Clock Frequency Static Dynamic Total
signal(ns) (MHZ) power power Power Table 6. Dynamic Power Comparisons In ALU.
1 500 197mw 465mw 664mw Clock Frequency Existing T flip flop
2 400 198mw 259mw 457mw signal(ns) (MHZ) technique Based
3 300 198mw 120mw 318mw (dynamic (dynamic
5 200 198mw 76mw 274mw power) Power)
1 500 465mw 24mw
10 100 199mw 46mw 243mw
2 400 259mw 19mw
3 300 120mw 14mw
7. SIMULATED RESULT
The simulated wave form of the 8-bit ALU using T flip flop 5 200 76mw 9mw
clock gating is shown in the Fig.9. From the simulated result 10 100 46mw 5mw
shown in Fig. 9, it is observed that, the 8-bit input is applied
to Ain and Bin and the input to the select lines of logical and
arithmetic functional units are also provided. The power

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.8, June 2016

9. CONCLUSION [7] M. S. Hosny and W. Yuejian, “Low power clocking

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