LPC11E3X

LPC11E3x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up

to 12 kB SRAM and 4 kB EEPROM; USART
Rev. 2.3 — 11 September 2014 Product data sheet
1. General description
The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit
microcontroller applications, offering performance, low power, simple instruction set and
memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11E3x operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to

12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface,
one RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up
to 54 general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I2C, and I2S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O Handler applications are available on http://www.LPCware.com.
2. Features and benefits

 System:
 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
 Non Maskable Interrupt (NMI) input selectable from several input sources.
 System tick timer.
 Memory:
 Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase
(256 byte) access.
 4 kB on-chip EEPROM data memory; byte erasable and byte programmable;
on-chip API support.
 12 kB SRAM data memory.
 16 kB boot ROM.
 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
 ROM-based 32-bit integer division routines.
NXP Semiconductors LPC11E3x
32-bit ARM Cortex-M0 microcontroller
 Debug options:
 Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
 Serial Wire Debug.
 Digital peripherals:
 Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
 Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
 Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
 High-current source output driver (20 mA) on one pin.
 High-current sink driver (20 mA) on true open-drain pins.
 Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outputs.
 Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
 Analog peripherals:
 10-bit ADC with input multiplexing among eight pins.
 Serial interfaces:
 USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
 Two SSP controllers with FIFO and multi-protocol capabilities.
 I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
 I/O Handler for hardware emulation of serial interfaces and DMA; supported through
software libraries.(LPC11E37HFBD64/401 only.)
 Clock generation:
 Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
 Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
 PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
 Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
 Power control:
 Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
 Power profiles residing in boot ROM provide optimized performance and minimized
power consumption for any given application through one simple function call.
 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
 Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, or the watchdog interrupt.
 Processor wake-up from Deep power-down mode using one special function pin.
LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 2 of 71

 Power-On Reset (POR).

 Brownout detect with four separate thresholds for interrupt and forced reset.
 Unique device serial number for identification.
 Single 3.3 V power supply (1.8 V to 3.6 V).
 Temperature range 40 C to +85 C.
 Available as LQFP64, LQFP48, and HVQFN33 packages.
3. Applications
 Consumer peripherals  Handheld scanners

 Medical  Industrial control
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC11E35FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 5  5  0.85 mm
LPC11E36FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2
LPC11E36FHN33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7  7  0.85 mm
LPC11E37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

4.1 Ordering options

Table 2. Ordering options
Type number
Total SRAM in kB
SRAM1 in kB[1]
EEPROM in kB
ADC channels
SRAM0 in kB
SRAM2 in kB
I2C-bus FM+
I/O Handler
Flash in kB
GPIO pins
USART
SSP
LPC11E35FHI33/501 64 4 8 2 2[1] 12 no 1 1 2 8 26
LPC11E36FBD64/501 96 4 8 2 2[1] 12 no 1 1 2 8 54
LPC11E36FHN33/501 96 4 8 2 2[1] 12 no 1 1 2 8 28
LPC11E37FBD48/501 128 4 8 2 2[1] 12 no 1 1 2 8 40
LPC11E37FBD64/501 128 4 8 2 2[1] 12 no 1 1 2 8 54
LPC11E37HFBD64/401 128 4 8 2 2[2] 10 yes 1 1 2 8 54
[1] For general-purpose use.

[2] For I/O Handler use only.

5. Block diagram
SWD, JTAG
XTALIN XTALOUT RESET
LPC11E3x SYSTEM OSCILLATOR

TEST/DEBUG CLOCK
INTERFACE GENERATION,
IRC, WDO
POWER CONTROL, CLKOUT
BOD SYSTEM
ARM
FUNCTIONS
CORTEX-M0
POR
PLL0
EEPROM
4 kB
FLASH SRAM ROM
system bus
96/128 kB 10/12 kB 16 kB
slave slave slave slave

HIGH-SPEED
GPIO ports 0/1
GPIO
AHB-LITE BUS
master
I/O
IOH_[20:0]
HANDLER(3)
slave
AHB TO APB
BRIDGE
RXD
TXD
USART/
DCD, DSR(1), RI(1) 10-bit ADC AD[7:0]
SMARTCARD INTERFACE
CTS, RTS, DTR
SCLK
I2C-BUS SCL, SDA
CT16B0_MAT[2:0]
16-bit COUNTER/TIMER 0
CT16B0_CAP[1:0](2)
SCK0, SSEL0,
CT16B1_MAT[1:0] SSP0 MISO0, MOSI0
CT16B1_CAP[1:0](2)
SCK1, SSEL1,
CT32B0_MAT[3:0] SSP1 MISO1, MOSI1
CT32B0_CAP[1:0](2)
CT32B1_MAT[3:0] IOCON
CT32B1_CAP[1:0](2)
SYSTEM CONTROL
WINDOWED WATCHDOG
TIMER PMU
GPIO pins GPIO INTERRUPTS
GPIO pins GPIO GROUP0 INTERRUPTS
GPIO pins GPIO GROUP1 INTERRUPTS
002aah401
(1) Not available on HVQFN33 packages.

(2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available LQFP48, and LQFP64
packages only; CT32B1_CAP1 available in LQFP64 packages only.
(3) LPC11E37HFBD64/401 only.
Fig 1. Block diagram

6. Pinning information
6.1 Pinning
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO0_18/RXD/CT32B0_MAT0
PIO0_19/TXD/CT32B0_MAT1
PIO0_23/AD7
VDD
terminal 1
index area
32
31
30
29
28
27
26
25
PIO1_19/DTR/SSEL1 1 24 TRST/PIO0_14/AD3/CT32B1_MAT1
RESET/PIO0_0 2 23 TDO/PIO0_13/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2 3 22 TMS/PIO0_12/AD1/CT32B1_CAP0
XTALIN 4 21 TDI/PIO0_11/AD0/CT32B0_MAT3
XTALOUT 5 20 PIO0_22/AD6/CT16B1_MAT1/MISO1
VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_20/CT16B1_CAP0 7 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0
10
11
12
13
14
15
16
9
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_21/CT16B1_MAT0/MOSI1
PIO1_23/CT16B1_MAT1/SSEL1
PIO1_24/CT32B0_MAT0
PIO0_6/SCK0
PIO0_7/CTS
002aah404
Transparent top view
For parts LPC11E36FHN33/501

Fig 2. Pin configuration (HVQFN33, 7x7)

PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO0_18/RXD/CT32B0_MAT0
PIO0_19/TXD/CT32B0_MAT1
PIO0_23/AD7
VDD
terminal 1
index area
32
31
30
29
28
27
26
25
PIO1_19/DTR/SSEL1 1 24 TRST/PIO0_14/AD3/CT32B1_MAT1
RESET/PIO0_0 2 23 TDO/PIO0_13/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE 3 22 TMS/PIO0_12/AD1/CT32B1_CAP0
XTALIN 4 21 TDI/PIO0_11/AD0/CT32B0_MAT3
XTALOUT 5 20 PIO0_22/AD6/CT16B1_MAT1/MISO1
VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_20/CT16B1_CAP0 7 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0
10
11
12
13
14
15
16
9
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO0_21/CT16B1_MAT0/MOSI1
VSS
VSS
PIO0_6/USB_CONNECT/SCK0
PIO0_7/CTS
aaa-014397
Transparent top view
For parts LPC11E35FHI33/501

Fig 3. Pin configuration (HVQFN33, 5x5)

29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2
30 PIO0_22/AD6/CT16B1_MAT1/MISO1
35 TRST/PIO0_14/AD3/CT32B1_MAT1
36 PIO1_13/DTR/CT16B0_MAT0/TXD
34 TDO/PIO0_13/AD2/CT32B1_MAT0
33 TMS/PIO0_12/AD1/CT32B1_CAP0
32 TDI/PIO0_11/AD0/CT32B0_MAT3
31 PIO1_29/SCK0/CT32B0_CAP1
28 PIO0_9/MOSI0/CT16B0_MAT1
27 PIO0_8/MISO0/CT16B0_MAT0
26 PIO1_21/DCD/MISO1
25 PIO1_31
PIO1_14/DSR/CT16B0_MAT1/RXD 37 24 PIO1_28/CT32B0_CAP0/SCLK
PIO1_22/RI/MOSI1 38 23 PIO0_7/CTS
SWDIO/PIO0_15/AD4/CT32B1_MAT2 39 22 PIO0_6/SCK0
PIO0_16/AD5/CT32B1_MAT3/WAKEUP 40 21 PIO1_24/CT32B0_MAT0
VSS 41 20 n.c.
PIO0_23/AD7 42 LPC11E37FBD48/501 19 n.c.
PIO1_15/DCD/CT16B0_MAT2/SCK1 43 18 PIO1_23/CT16B1_MAT1/SSEL1
VDD 44 17 PIO0_21/CT16B1_MAT0/MOSI1
PIO0_17/RTS/CT32B0_CAP0/SCLK 45 16 PIO0_5/SDA
PIO0_18/RXD/CT32B0_MAT0 46 15 PIO0_4/SCL
PIO0_19/TXD/CT32B0_MAT1 47 14 PIO0_3
PIO1_16/RI/CT16B0_CAP0 48 13 PIO1_20/DSR/SCK1
PIO0_2/SSEL0/CT16B0_CAP0 10
PIO1_26/CT32B0_MAT2/RXD 11
PIO1_27/CT32B0_MAT3/TXD 12
1
2
3
4
5
6
7
8
9
002aah402
PIO1_25/CT32B0_MAT1
PIO1_19/DTR/SSEL1
RESET/PIO0_0
VSS
XTALIN
XTALOUT
VDD
PIO0_1/CLKOUT/CT32B0_MAT2
PIO0_20/CT16B1_CAP0
Fig 4. Pin configuration (LQFP48)

38 SWCLK/PIO0_10
46 TRST/PIO0_14
45 TDO/PIO0_13
44 TMS/PIO0_12
42 TDI/PIO0_11
47 PIO1_13
43 PIO1_11
41 PIO1_29
40 PIO0_22
35 PIO1_21
39 PIO1_8
37 PIO0_9
36 PIO0_8
34 PIO1_2
48 VDD
33 VDD
PIO1_14 49 32 PIO1_5
PIO1_3 50 31 PIO1_28
PIO1_22 51 30 PIO0_7
SWDIO/PIO0_15 52 29 PIO0_6
PIO0_16 53 28 PIO1_18
VSS 54 27 PIO1_24
PIO1_9 55 LPC11E36FBD64/501 26 n.c.
PIO0_23 56 LPC11E37FBD64/501 25 n.c.
PIO1_15 57 LPC11E37HFBD64/401 24 PIO1_23
VDD 58 23 PIO1_17
PIO1_12 59 22 PIO0_21
PIO0_17 60 21 PIO0_5
PIO0_18 61 20 PIO0_4
PIO0_19 62 19 PIO0_3
PIO1_16 63 18 PIO1_20
PIO1_6 64 17 PIO1_1
VDD 10
PIO0_20 11
PIO1_10 12
PIO0_2 13
PIO1_26 14
PIO1_27 15
PIO1_4 16
1
2
3
4
5
6
7
8
9
PIO1_0
PIO1_25
PIO1_19
RESET/PIO0_0
PIO0_1
PIO1_7
VSS
XTALIN
XTALOUT
002aah403
See Table 3 for the full pin name.

Fig 5. Pin configuration (LQFP64)

6.2 Pin description

Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO
port number. The default function after reset is listed first. All port pins have internal
pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 3. Pin description

Symbol Reset Type Description
Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
RESET/PIO0_0 2 2 3 4 [2] I; PU I RESET — External reset input with 20 ns glitch

filter. A LOW-going pulse as short as 50 ns on this
pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH level
selects the ARM SWD debug mode.
- I/O PIO0_0 — General purpose digital input/output
pin.
PIO0_1/CLKOUT/ 3 3 4 5 [3] I; PU I/O PIO0_1 — General purpose digital input/output
CT32B0_MAT2 pin. A LOW level on this pin during reset starts the
ISP command handler.
- O CLKOUT — Clockout pin.
- O CT32B0_MAT2 — Match output 2 for 32-bit timer
0.
PIO0_2/SSEL0/ 8 8 10 13 [3] I; PU I/O PIO0_2 — General purpose digital input/output
CT16B0_CAP0/IOH_0 pin.
- I/O SSEL0 — Slave select for SSP0.
- I CT16B0_CAP0 — Capture input 0 for 16-bit timer
0.
- I/O IOH_0 — I/O Handler input/output 0.
LPC11E37HFBD64/401 only.
PIO0_3/R/IOH_1 9 9 14 19 [3] I; PU I/O PIO0_3 — General purpose digital input/output
pin.
- - R — Reserved.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
PIO0_4/SCL/IOH_2 10 10 15 20 [4] I; IA I/O PIO0_4 — General purpose digital input/output
pin (open-drain).
- I/O SCL — I2C-bus clock input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
PIO0_5/SDA/IOH_3 11 11 16 21 [4] I; IA I/O PIO0_5 — General purpose digital input/output
pin (open-drain).
- I/O SDA — I2C-bus data input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
PIO0_6/R/ 15 15 22 29 [3] I; PU I/O PIO0_6 — General purpose digital input/output
SCK0/IOH_4 pin.
- - R — Reserved.
- I/O SCK0 — Serial clock for SSP0.
PIO0_7/CTS/IOH_5 16 16 23 30 [5] I; PU I/O PIO0_7 — General purpose digital input/output
pin (high-current output driver).
- I CTS — Clear To Send input for USART.
PIO0_8/MISO0/ 17 17 27 36 [3] I; PU I/O PIO0_8 — General purpose digital input/output
CT16B0_MAT0/R/IOH_6 pin.
- I/O MISO0 — Master In Slave Out for SSP0.
0.
- - Reserved.
PIO0_9/MOSI0/ 18 18 28 37 [3] I; PU I/O PIO0_9 — General purpose digital input/output
CT16B0_MAT1/R/IOH_7 pin.
- I/O MOSI0 — Master Out Slave In for SSP0.
0.
- - Reserved.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
SWCLK/PIO0_10/SCK0/ 19 19 29 38 [3] I; PU I SWCLK — Serial wire clock and test clock TCK
CT16B0_MAT2 for JTAG interface.
- I/O PIO0_10 — General purpose digital input/output
pin.
- O SCK0 — Serial clock for SSP0.
0.
TDI/PIO0_11/AD0/ 21 21 32 42 [6] I; PU I TDI — Test Data In for JTAG interface.
CT32B0_MAT3 - I/O PIO0_11 — General purpose digital input/output
pin.
- I AD0 — A/D converter, input 0.
0.
TMS/PIO0_12/AD1/ 22 22 33 44 [6] I; PU I TMS — Test Mode Select for JTAG interface.
CT32B1_CAP0 - I/O PIO_12 — General purpose digital input/output
pin.
1.
TDO/PIO0_13/AD2/ 23 23 34 45 [6] I; PU O TDO — Test Data Out for JTAG interface.
pin.
1.
TRST/PIO0_14/AD3/ 24 24 35 46 [6] I; PU I TRST — Test Reset for JTAG interface.
pin.
1.
SWDIO/PIO0_15/AD4/ 25 25 39 52 [6] I; PU I/O SWDIO — Serial wire debug input/output.
pin.
1.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
PIO0_16/AD5/ 26 26 40 53 [6] I; PU I/O PIO0_16 — General purpose digital input/output
CT32B1_MAT3/IOH_8/ pin.
WAKEUP - I AD5 — A/D converter, input 5.
1.
- I WAKEUP — Deep power-down mode wake-up
pin with 20 ns glitch filter. Pull this pin HIGH
externally before entering Deep power-down
mode, then pull LOW to exit Deep power-down
mode. A LOW-going pulse as short as 50 ns
wakes up the part.
PIO0_17/RTS/ 30 30 45 60 [3] I; PU I/O PIO0_17 — General purpose digital input/output
CT32B0_CAP0/SCLK pin.
- O RTS — Request To Send output for USART.
0.
- I/O SCLK — Serial clock input/output for USART in
synchronous mode.
PIO0_18/RXD/ 31 31 46 61 [3] I; PU I/O PIO0_18 — General purpose digital input/output
CT32B0_MAT0 pin.
- I RXD — Receiver input for USART. Used in UART
ISP mode.
0.
PIO0_19/TXD/ 32 32 47 62 [3] I; PU I/O PIO0_19 — General purpose digital input/output
CT32B0_MAT1 pin.
- O TXD — Transmitter output for USART. Used in
UART ISP mode.
0.
PIO0_20/CT16B1_CAP0 7 7 9 11 [3] I; PU I/O PIO0_20 — General purpose digital input/output
pin.
1.
PIO0_21/CT16B1_MAT0/ 12 12 17 22 [3] I; PU I/O PIO0_21 — General purpose digital input/output
MOSI1 pin.
1.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
PIO0_22/AD6/ 20 20 30 40 [6] I; PU I/O PIO0_22 — General purpose digital input/output
CT16B1_MAT1/MISO1 pin.
1.
PIO0_23/AD7/IOH_9 27 27 42 56 [6] I; PU I/O PIO0_23 — General purpose digital input/output
pin.
PIO1_0/CT32B1_MAT0/ - - - 1 [3] I; PU I/O PIO1_0 — General purpose digital input/output
IOH_10 pin.
1.
IOH_11 pin.
1.
IOH_12 pin.
1.
IOH_13 pin.
1.
(LPC11E37HFBD64/401 only.)
PIO1_4/CT32B1_CAP0/ - - - 16 [3] I; PU I/O PIO1_4 — General purpose digital input/output
IOH_14 pin.
1.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
IOH_15 pin.
1.
PIO1_6/IOH_16 - - - 64 [3] I; PU I/O PIO1_6 — General purpose digital input/output
pin.
pin.
pin.
PIO1_9 - - - 55 [3] I; PU I/O PIO1_9 — General purpose digital input/output
pin.
pin.
pin.
pin.
PIO1_13/DTR/ - - 36 47 [3] I; PU I/O PIO1_13 — General purpose digital input/output
CT16B0_MAT0/TXD pin.
- O DTR — Data Terminal Ready output for USART.
0.
- O TXD — Transmitter output for USART.
PIO1_14/DSR/ - - 37 49 [3] I; PU I/O PIO1_14 — General purpose digital input/output
CT16B0_MAT1/RXD pin.
- I DSR — Data Set Ready input for USART.
0.
- I RXD — Receiver input for USART.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
PIO1_15/DCD/ 28 28 43 57 [3] I; PU I/O PIO1_15 — General purpose digital input/output
CT16B0_MAT2/SCK1 pin.
I DCD — Data Carrier Detect input for USART.
0.
PIO1_16/RI/ - - 48 63 [3] I; PU I/O PIO1_16 — General purpose digital input/output
CT16B0_CAP0 pin.
- I RI — Ring Indicator input for USART.
0.
RXD pin.
0.
TXD pin.
1.
PIO1_19/DTR/SSEL1 1 1 2 3 [3] I; PU I/O PIO1_19 — General purpose digital input/output
pin.
- O DTR — Data Terminal Ready output for USART.
PIO1_20/DSR/SCK1 - - 13 18 [3] I; PU I/O PIO1_20 — General purpose digital input/output
pin.
- I DSR — Data Set Ready input for USART.
PIO1_21/DCD/MISO1 - - 26 35 [3] I; PU I/O PIO1_21 — General purpose digital input/output
pin.
- I DCD — Data Carrier Detect input for USART.
PIO1_22/RI/MOSI1 - - 38 51 [3] I; PU I/O PIO1_22 — General purpose digital input/output
pin.
- I RI — Ring Indicator input for USART.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
PIO1_23/CT16B1_MAT1/ - 13 18 24 [3] I; PU I/O PIO1_23 — General purpose digital input/output
SSEL1 pin.
1.
PIO1_24/CT32B0_MAT0 - 14 21 27 [3] I; PU I/O PIO1_24 — General purpose digital input/output
pin.
0.
PIO1_25/CT32B0_MAT1 - - 1 2 [3] I; PU I/O PIO1_25 — General purpose digital input/output
pin.
0.
PIO1_26/CT32B0_MAT2/ - - 11 14 [3] I; PU I/O PIO1_26 — General purpose digital input/output
RXD/IOH_19 pin.
0.
PIO1_27/CT32B0_MAT3/ - - 12 15 [3] I; PU I/O PIO1_27 — General purpose digital input/output
TXD/IOH_20 pin.
0.
PIO1_28/CT32B0_CAP0/ - - 24 31 [3] I; PU I/O PIO1_28 — General purpose digital input/output
SCLK pin.
0.
- I/O SCLK — Serial clock input/output for USART in
synchronous mode.
PIO1_29/SCK0/ - - 31 41 [3] I; PU I/O PIO1_29 — General purpose digital input/output
CT32B0_CAP1 pin.
0.
PIO1_31 - - 25 - [3] I; PU I/O PIO1_31 — General purpose digital input/output
pin.
n.c. - - 19 25 - - Not connected.
n.c. - - 20 26 - - Not connected.


Pin HVQFN33
Pin HVQFN33
Pin LQFP48
Pin LQFP64
state
[1]
(5x5)
(7x7)
XTALIN 4 4 6 8 [7] - - Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed
1.8 V.
XTALOUT 5 5 7 9 [7] - - Output from the oscillator amplifier.
VDD 6; 29 6; 8; 10; - - Supply voltage to the internal regulator, the
29 44 33; external rail, and the ADC. Also used as the ADC
48; reference voltage.
58
VSS 33; 33 5; 7; - - Ground.
13; 41 54
14
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 29 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 28).
[4] I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 28);
includes high-current output driver.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 28); includes digital
input glitch filter.
[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating.
7. Functional description
7.1 On-chip flash programming memory

The LPC11E3x contain up to 128 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages can be erased using the IAP erase page command.
7.2 EEPROM
The LPC11E3x contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM
data memory. The EEPROM can be programmed using In-Application Programming (IAP)
via the on-chip boot loader software.

7.3 SRAM
The LPC11E3x contain a total of 10 kB (LPC11E37HFBD64/401) or 12 kB on-chip static
RAM memory.
On the LPC11E37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to

0x2000 07FFF is used for the I/O Handler software library. Do not use this memory
location for data or other user code.
7.4 On-chip ROM

The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
• IAP support for EEPROM.
• Power profiles for configuring power consumption and PLL settings.
• 32-bit integer division routines.
7.5 Memory map

The LPC11E3x incorporates several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided
to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This addressing scheme allows simplifying the address
decoding for each peripheral.

LPC11E3x
4 GB 0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
0xE000 0000
reserved
0x5000 4000
GPIO
0x5000 0000
APB peripherals
reserved 0x4008 0000
0x4008 4000 25 - 31 reserved
reserved 0x4006 4000
0x4008 0000 24 GPIO GROUP1 INT
0x4006 0000
APB peripherals
1 GB 0x4000 0000 23 GPIO GROUP0 INT
0x4005 C000
22 SSP1
0x4005 8000
reserved 20 - 21 reserved
0x4004 C000
0x2000 4800 19 GPIO interrupts
0x4004 C000
2 kB SRAM2
0x2000 4000 18 system control 0x4004 8000
reserved 17 IOCON
0x4004 4000
16 SSP0 0x4004 0000
0x2000 0800 15 flash/EEPROM controller
2 kB SRAM1/ 0x4003 C000
I/O Handler code area 14 PMU 0x4003 8000
0.5 GB for LPC11E37HFBD64/401 0x2000 0000
reserved 10 - 13 reserved
0x1FFF 4000
16 kB boot ROM 0x4002 8000
0x1FFF 0000 9 reserved
0x4002 4000
8 reserved 0x4002 0000
reserved
7 ADC 0x4001 C000
0x1000 2000 32-bit counter/timer 1
6 0x4001 8000
8 kB SRAM0
0x1000 0000 5 32-bit counter/timer 0 0x4001 4000
4 16-bit counter/timer 1 0x4001 0000
3 16-bit counter/timer 0 0x4000 C000
reserved
2 USART/SMART CARD 0x4000 8000
1 WWDT 0x4000 4000
0x0002 0000 0 I2C-bus 0x4000 0000
128 kB on-chip flash (LPC11E37) 0x0001 8000
96 kB on-chip flash (LPC11E36) 0x0000 00C0
active interrupt vectors
0x0000 0000
0 GB 0x0000 0000
002aah405
Fig 6. LPC11E3x memory map
7.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
7.6.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11E3x, the NVIC supports 24 vectored interrupts.

• Four programmable interrupt priority levels, with hardware priority level masking.
• Software interrupt generation.
7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but can have several
interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
7.7 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Connect peripherals to the appropriate pins before activating the peripheral and before
enabling any related interrupt. . Activity of any enabled peripheral function that is not
mapped to a related pin is treated as undefined.
7.7.1 Features
• Programmable pull-up, pull-down, or repeater mode.
• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned on by default.
• Programmable hysteresis.
• Programmable input inverter.
7.8 General-Purpose Input/Output GPIO

The GPIO registers control device pin functions that are not connected to a specific
peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple
outputs can be set or cleared in one write operation.
LPC11E3x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on
a level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.

2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO
pins.

7.8.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Any pin or pins in each port can trigger a port interrupt.
7.9 I/O Handler (LPC11E37HFBD64/401 only)

The I/O Handler is a software library-supported hardware engine for emulating serial
interfaces and DMA. The I/O Handler can emulate serial interfaces such as UART, I2C, or
I2S with no or very low additional CPU load. The software libraries are available with
supporting application notes from NXP (see http://www.LPCware.com.) LPCXpresso, Keil,
and IAR IDEs are supported. I/O Handler library code must be executed from the memory
area 0x2000 0000 to 0x2000 07FF. This memory is not available for other use.
For application examples, see Section 11.7 “I/O Handler software library applications”.
7.10 USART
The LPC11E3x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
• Maximum USART data bit rate of 3.125 Mbit/s.
• 16 byte receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
• Support for synchronous mode.
• Includes smart card interface.

7.11 SSP serial I/O controller

The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.11.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode).
• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments
SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• 4-bit to 16-bit frame.
7.12 I2C-bus serial I/O controller

The LPC11E3x contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, and
more than one bus master connected to the interface can be controlled the bus.
7.12.1 Features
• The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.

7.13 10-bit ADC

The LPC11E3x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD.
• 10-bit conversion time  2.44 s (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 General purpose external event counter/timers

The LPC11E3x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.14.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.

7.15 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.16 Windowed WatchDog Timer (WWDT)

The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
7.16.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time before watchdog
time-out.
• Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
• Incorrect feed sequence causes reset or interrupt, if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in
multiples of Tcy(WDCLK)  4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.
7.17 Clocking and power control
7.17.1 Integrated oscillators

The LPC11E3x include three independent oscillators: the system oscillator, the Internal
RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more
than one purpose as required in a particular application.
Following reset, the LPC11E3x operates from the internal RC oscillator until software
switches to a different clock source. The IRC allows the system to operate without any
external crystal and the bootloader code to operate at a known frequency.
See Figure 7 for an overview of the LPC11E3x clock generation.

CPU, system control,

PMU
SYSTEM CLOCK system clock n
DIVIDER memories,
peripheral clocks
SYSAHBCLKCTRLn
(AHB clock enable)
IRC oscillator
main clock
SSP0 PERIPHERAL
SSP0
CLOCK DIVIDER
watchdog oscillator
USART PERIPHERAL
UART
CLOCK DIVIDER
MAINCLKSEL
(main clock select) SSP1 PERIPHERAL
SSP1
CLOCK DIVIDER
IRC oscillator
SYSTEM PLL
system oscillator
SYSPLLCLKSEL
(system PLL clock select)
IRC oscillator
system oscillator CLKOUT PIN CLOCK
CLKOUT pin
watchdog oscillator DIVIDER
CLKOUTUEN
(CLKOUT update enable)
IRC oscillator
WDT
watchdog oscillator
WDCLKSEL
(WDT clock select)
002aah406
Fig 7. LPC11E3x clocking generation block diagram
7.17.1.1 Internal RC oscillator

The IRC can be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and then the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11E3x
use the IRC as the clock source. Software can later switch to one of the other available
clock sources.
7.17.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.

7.17.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is 40 % (see also Table 13).
7.17.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the
CCO within its frequency range while the PLL is providing the desired output frequency.
The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The
PLL output frequency must be lower than 100 MHz. Since the minimum output divider
value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off
and bypassed following a chip reset. Software can enable the PLL later. The program
must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL
as a clock source. The PLL settling time is 100 s.
7.17.3 Clock output

The LPC11E3x feature a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.17.4 Wake-up process

The LPC11E3x begin operation by using the 12 MHz IRC oscillator as the clock source at
power-up and when awakened from Deep power-down mode. This mechanism allows
chip operation to resume quickly. If the application uses the main oscillator or the PLL,
software must enable these components and wait for them to stabilize. Only then can the
system use the PLL and main oscillator as a clock source.
7.17.5 Power control

The LPC11E3x support various power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate can also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This power control mechanism allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals. This register allows fine-tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides even
better power control.
7.17.5.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11E3x for one of the following power modes:
• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.17.5.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and can generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, by memory systems and related controllers, and by
internal buses.
7.17.5.3 Deep-sleep mode

In Deep-sleep mode, the LPC11E3x is in Sleep-mode and all peripheral clocks and all
clock sources are off except for the IRC. The IRC output is disabled unless the IRC is
selected as input to the watchdog timer. In addition all analog blocks are shut down and
the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog
oscillator and the BOD circuit running for self-timed wake-up and BOD protection.
The LPC11E3x can wake up from Deep-sleep mode via reset, selected GPIO pins or a
watchdog timer interrupt.
Deep-sleep mode saves power and allows for short wake-up times.
7.17.5.4 Power-down mode

In Power-down mode, the LPC11E3x is in Sleep-mode and all peripheral clocks and all
clock sources are off except for watchdog oscillator if selected. In addition all analog
blocks and the flash are shut down. In Power-down mode, the application can keep the
BOD circuit running for BOD protection.
The LPC11E3x can wake up from Power-down mode via reset, selected GPIO pins or a
watchdog timer interrupt.
Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.
7.17.5.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin. The LPC11E3x can wake up from Deep power-down mode via the WAKEUP pin.
The LPC11E3x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in
Deep power-down mode.

7.17.6 System control
7.17.6.1 Reset
Reset has four sources on the LPC11E3x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
7.17.6.2 Brownout detection

The LPC11E3x includes four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
7.17.6.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC11Exx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable
flash update via the USART.

CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11Exx user manual.
7.17.6.4 APB interface

The APB peripherals are located on one APB bus.
7.17.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.17.6.6 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

7.18 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11E3x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage (core and [2] 0.5 +4.6 V
external rail)
VI input voltage 5 V tolerant digital I/O pins; [5][2] 0.5 +5.5 V
VDD  1.8 V
VDD = 0 V 0.5 +3.6 V
5 V tolerant open-drain pins [2][4] 0.5 +5.5
PIO0_4 and PIO0_5
VIA analog input voltage pin configured as analog input [2] 0.5 4.6 V
[3]
IDD supply current per supply pin - 100 mA

ISS ground current per ground pin - 100 mA
Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); - 100 mA
Tj < 125 C
Tstg storage temperature non-operating [6] 65 +150 C
Tj(max) maximum junction - 150 C
temperature
Ptot(pack) total power dissipation (per based on package heat - 1.5 W
package) transfer, not device power
consumption
VESD electrostatic discharge human body model; all pins [7] - +6500 V
voltage
[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 5.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 5) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See Table 6 for maximum operating voltage.
[4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[5] Including voltage on outputs in 3-state mode.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

9. Static characteristics
Table 5. Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage (core 1.8 3.3 3.6 V
and external rail)
IDD supply current Active mode; VDD = 3.3 V;
Tamb = 25 C; code
while(1){}
executed from flash;
system clock = 12 MHz [2][3][4] - 2 - mA
[5][6]
system clock = 50 MHz [3][4][5] - 7 - mA

[6]
Sleep mode; [2][3][4] - 1 - mA

VDD = 3.3 V; Tamb = 25 C; [5][6]
system clock = 12 MHz

Deep-sleep mode; VDD = 3.3 V; [3] - 300 - A
Tamb = 25 C
Power-down mode; VDD = 3.3 V; - 2 - A
Tamb = 25 C
Deep power-down mode; [8] - 220 - nA
VDD = 3.3 V; Tamb = 25 C
Standard port pins, RESET
IIL LOW-level input current VI = 0 V; on-chip pull-up resistor - 0.5 10 nA
disabled
IIH HIGH-level input VI = VDD; on-chip pull-down resistor - 0.5 10 nA
current disabled
IOZ OFF-state output VO = 0 V; VO = VDD; on-chip - 0.5 10 nA
current pull-up/down resistors disabled
VI input voltage pin configured to provide a digital [9] 0 - 5.0 V
function; VDD  1.8 V [10]
VDD = 0 V 0 - 3.6 V
VO output voltage output active 0 - VDD V
VIH HIGH-level input 0.7VDD - - V
voltage
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.4 - V
VOH HIGH-level output 2.0 V  VDD  3.6 V; IOH = 4 mA VDD  0.4 - - V
voltage 1.8 V  VDD < 2.0 V; IOH = 3 mA VDD  0.4 - - V
VOL LOW-level output 2.0 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V
voltage 1.8 V  VDD < 2.0 V; IOL = 3 mA - - 0.4 V
IOH HIGH-level output VOH = VDD  0.4 V; 4 - - mA
current 2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V 3 - - mA

Table 5. Static characteristics …continued

IOL LOW-level output VOL = 0.4 V 4 - - mA
1.8 V  VDD < 2.0 V 3 - - mA
IOHS HIGH-level short-circuit VOH = 0 V [11] - - 45 mA
output current
IOLS LOW-level short-circuit VOL = VDD [11] - - 50 mA
output current
Ipd pull-down current VI = 5 V 10 50 150 A
Ipu pull-up current VI = 0 V; 15 50 85 A
2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V 10 50 85 A
VDD < VI < 5 V 0 0 0 A
High-drive output pin (PIO0_7)
IIL LOW-level input current VI = 0 V; on-chip pull-up resistor - 0.5 10 nA
disabled
IIH HIGH-level input VI = VDD; on-chip pull-down resistor - 0.5 10 nA
current disabled
IOZ OFF-state output VO = 0 V; VO = VDD; on-chip - 0.5 10 nA
current pull-up/down resistors disabled
VI input voltage pin configured to provide a digital [9] 0 - 5.0 V
function [10]
VDD = 0 V 0 - 3.6 V
VO output voltage output active 0 - VDD V
voltage
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4 - - V
voltage 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4 - - V
VOL LOW-level output 2.0 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V
voltage 1.8 V  VDD < 2.0 V; IOL = 3 mA - - 0.4 V
IOH HIGH-level output VOH = VDD  0.4 V; 20 - - mA
1.8 V  VDD < 2.5 V 12 - - mA
IOL LOW-level output VOL = 0.4 V 4 - - mA
1.8 V  VDD < 2.0 V 3 - - mA
IOLS LOW-level short-circuit VOL = VDD [11] - - 50 mA
output current
Ipd pull-down current VI = 5 V 10 50 150 A

Table 5. Static characteristics …continued

Ipu pull-up current VI = 0 V 15 50 85 A
2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V 10 50 85 A
VDD < VI < 5 V 0 0 0 A
I2C-bus pins (PIO0_4 and PIO0_5)
voltage
Vhys hysteresis voltage - 0.05VDD - V
IOL LOW-level output VOL = 0.4 V; I2C-bus
pins configured 3.5 - - mA
current as standard mode pins
2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V 3 - -
IOL LOW-level output VOL = 0.4 V; I2C-bus pins configured 20 - - mA
current as Fast-mode Plus pins
2.0 V  VDD  3.6 V
1.8 V  VDD < 2.0 V 16 - -
ILI input leakage current VI = VDD [12] - 2 4 A
VI = 5 V - 10 22 A
Oscillator pins
Vi(xtal) crystal input voltage 0.5 1.8 1.95 V
Vo(xtal) crystal output voltage 0.5 1.8 1.95 V
Pin capacitance
Cio input/output pins configured for analog function - - 7.1 pF
capacitance I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF
pins configured as GPIO - - 2.8 pF
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] IRC enabled; system oscillator disabled; system PLL disabled.
[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] BOD disabled.
[5] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the SYSCON block.
[6] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[7] IRC disabled; system oscillator enabled; system PLL enabled.
[8] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[9] Including voltage on outputs in 3-state mode.
[10] 3-state outputs go into 3-state mode in Deep power-down mode.
[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[12] To VSS.

Table 6. ADC static characteristics

Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDD V
Cia analog input capacitance - - 1 pF
ED differential linearity error [1][2] - - 1 LSB
EL(adj) integral non-linearity [3] - - 1.5 LSB
EO offset error [4] - - 3.5 LSB
EG gain error [5] - - 0.6 %
ET absolute error [6] - - 4 LSB
Rvsi voltage source interface - - 40 k
resistance
Ri input resistance [7][8] - - 2.5 M
[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 8.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 8.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 8.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 8.
[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia).

offset gain
error error
EO EG
1023
1022
1021
1020
1019
1018
(2)
7
code (1)
out
6
(5)
4
(4)
3
(3)
2
1 1 LSB
(ideal)
0
1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
VIA (LSBideal)
offset error
EO VDD − VSS
1 LSB =
1024
002aaf426
(1) Example of an actual transfer curve.

(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 8. ADC characteristics

9.1 BOD static characteristics

Table 7. BOD static characteristics[1]
Tamb = 25 C.
Vth threshold voltage interrupt level 1
assertion - 2.22 - V
de-assertion - 2.35 - V
interrupt level 2
interrupt level 3
reset level 0
reset level 1
reset level 2
reset level 3
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the
LPC11Exx user manual.
9.2 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see the LPC11Exx user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

002aag749
9
IDD 48 MHz(2)
(mA)
6
36 MHz(2)
24 MHz(2)
3
12 MHz(1)
0
1.8 2.4 3.0 3.6
VDD (V)
Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash;
internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 9. Typical supply current versus regulator supply voltage VDD in active mode
002aag750
9
IDD 48 MHz(2)
(mA)
6
36 MHz(2)
24 MHz(2)
3
12 MHz(1)
0
-40 -15 10 35 60 85
temperature (°C)
Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal
pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL
register; all peripheral clocks disabled; low-current mode.
Fig 10. Typical supply current versus temperature in Active mode

002aag751
4
IDD
(mA)
3
48 MHz(2)
36 MHz(2)
2
24 MHz(2)
12 MHz(1)
1
0
-40 -15 10 35 60 85
temperature (°C)
Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD
disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled;
low-current mode..
Fig 11. Typical supply current versus temperature in Sleep mode
002aag745
385
IDD
(µA)
375
VDD = 3.6 V
VDD = 3.3 V
365
VDD = 2.0 V
355
VDD = 1.8 V
345
-40 -15 10 35 60 85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register.
Fig 12. Typical supply current versus temperature in Deep-sleep mode

002aag746
20
IDD VDD = 3.6 V, 3.3 V

(µA) VDD = 2.0 V
VDD = 1.8 V
15
10
0
-40 -15 10 35 60 85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register.
Fig 13. Typical supply current versus temperature in Power-down mode
002aag747
0.8
IDD VDD = 3.6 V

(µA) VDD = 3.3 V
VDD = 2.0 V
0.6 VDD = 1.8 V
0.4
0.2
0
-40 -15 10 35 60 85
temperature (°C)
Fig 14. Typical supply current versus temperature in Deep power-down mode
9.3 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 8. Power consumption for individual analog and digital blocks

Peripheral Typical supply current in Notes
mA
n/a 12 MHz 48 MHz
IRC 0.27 - - System oscillator running; PLL off; independent
of main clock frequency.
System oscillator 0.22 - - IRC running; PLL off; independent of main clock
at 12 MHz frequency.
Watchdog 0.004 - - System oscillator running; PLL off; independent
oscillator at of main clock frequency.
500 kHz/2
BOD 0.051 - - Independent of main clock frequency.
Main PLL - 0.21 - -
ADC - 0.08 0.29 -
CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV
register.
CT16B0 - 0.02 0.06 -
CT16B1 - 0.02 0.06 -
CT32B0 - 0.02 0.07 -
CT32B1 - 0.02 0.06 -
GPIO - 0.23 0.88 GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCONFIG - 0.03 0.10 -
I2C - 0.04 0.13 -
ROM - 0.04 0.15 -
SPI0 - 0.12 0.45 -
SPI1 - 0.12 0.45 -
UART - 0.22 0.82 -
WWDT - 0.02 0.06 Main clock selected as clock source for the
WDT.

9.4 Electrical pin characteristics
002aae990
3.6
VOH
T = 85 °C
(V)
25 °C
3.2 −40 °C
2.8
2.4
2
0 10 20 30 40 50 60
IOH (mA)
Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH.
002aaf019
60
IOL T = 85 °C
(mA) 25 °C
−40 °C
40
20
0
0 0.2 0.4 0.6
VOL (V)
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 16. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL

002aae991
15
IOL T = 85 °C
(mA) 25 °C
−40 °C
10
0
0 0.2 0.4 0.6
VOL (V)
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.

Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL
002aae992
3.6
VOH
(V)
T = 85 °C
3.2 25 °C
−40 °C
2.8
2.4
2
0 8 16 24
IOH (mA)
Conditions: VDD = 3.3 V; standard port pins.

Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH

002aae988
10
Ipu
(μA)
−10
−30
T = 85 °C
25 °C
−40 °C
−50
−70
0 1 2 3 4 5
VI (V)

Fig 19. Typical pull-up current Ipu versus input voltage VI
002aae989
80
T = 85 °C
Ipd
25 °C
(μA)
−40 °C
60
40
20
0
0 1 2 3 4 5
VI (V)

Fig 20. Typical pull-down current Ipd versus input voltage VI

10. Dynamic characteristics
10.1 Flash memory

Table 9. Flash characteristics
Nendu endurance [1] 10000 100000 - cycles
tret retention time powered 10 - - years
unpowered 20 - - years
ter erase time sector or multiple 95 100 105 ms
consecutive sectors
tprog programming time [2] 0.95 1 1.05 ms
[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
Table 10. EEPROM characteristics

Tamb = 40 C to +85 C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate <
10 ppm for parts as specified below.
Nendu endurance 100000 1000000 - cycles
tret retention time powered 100 200 - years
unpowered 150 300 - years
tprog programming time 64 bytes - 2.9 - ms
10.2 External clock

Table 11. Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD over specified ranges.[1]
Symbol Parameter Min Typ[2] Max Unit
fosc oscillator frequency 1 - 25 MHz
Tcy(clk) clock cycle time 40 - 1000 ns
tCHCX clock HIGH time Tcy(clk)  0.4 - - ns
tCLCX clock LOW time Tcy(clk)  0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.

tCHCX
tCHCL tCLCX tCLCH
Tcy(clk)
002aaa907
Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
10.3 Internal oscillators

Table 12. Dynamic characteristics: IRC
Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V[1].
fosc(RC) internal RC oscillator - 11.88 12 12.12 MHz
frequency
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
002aaf403
12.15
f
(MHz) VDD = 3.6 V
3.3 V
3.0 V
12.05
2.7 V
2.4 V
2.0 V
11.95
11.85
−40 −15 10 35 60 85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for
2.7 V  VDD  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to
fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V.
Fig 22. Internal RC oscillator frequency versus temperature

Table 13. Dynamic characteristics: Watchdog oscillator

fosc(int) internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 [2][3] - 9.4 - kHz
frequency in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF [2][3] - 2300 - kHz
in the WDTOSCCTRL register
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3] See the LPC11Exx user manual.
10.4 I/O pins

Table 14. Dynamic characteristics: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V.
tr rise time pin configured as output 3.0 - 5.0 ns
tf fall time pin configured as output 2.5 - 5.0 ns
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock Standard-mode 0 100 kHz
frequency Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tf fall time [3][4][5][6] of both SDA and SCL - 300 ns
signals
Standard-mode
Fast-mode 20 + 0.1  Cb 300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of the Standard-mode 4.7 - s
SCL clock Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
tHIGH HIGH period of the Standard-mode 4.0 - s
SCL clock Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
tHD;DAT data hold time [3][7][8] Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
tSU;DAT data set-up time [9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
[1] See the I2C-bus specification UM10204 for details.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
tf tSU;DAT
70 % 70 %
SDA
30 % 30 %
tHD;DAT tVD;DAT
tf
tHIGH
70 % 70 % 70 % 70 %
SCL 30 % 30 %
30 % 30 %
tLOW
S 1 / fSCL
002aaf425
Fig 23. I2C-bus pins clock timing

10.6 SSP interface

Table 16. Dynamic characteristics of SPI pins in SPI mode
SPI master (in SPI mode)
Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns
when only transmitting [1] 40 ns
tDS data set-up time in SPI mode [2] 15 - - ns
2.4 V  VDD  3.6 V
2.0 V  VDD < 2.4 V [2] 20 ns
1.8 V  VDD < 2.0 V [2] 24 - - ns
tDH data hold time in SPI mode [2] 0 - - ns
tv(Q) data output valid time in SPI mode [2] - - 10 ns
th(Q) data output hold time in SPI mode [2] 0 - - ns
SPI slave (in SPI mode)
Tcy(PCLK) PCLK cycle time 20 - - ns
tDS data set-up time in SPI mode [3][4] 0 - - ns
tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns
tv(Q) data output valid time in SPI mode [3][4] - - 3  Tcy(PCLK) + 11 ns
th(Q) data output hold time in SPI mode [3][4] - - 2  Tcy(PCLK) + 5 ns
[1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = 40 C to 85 C.
[3] Tcy(clk) = 12  Tcy(PCLK).
[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q) th(Q)
MOSI DATA VALID DATA VALID
tDS tDH CPHA = 1
MISO DATA VALID DATA VALID
tv(Q) th(Q)
tDS tDH CPHA = 0
002aae829
Fig 24. SSP master timing in SPI mode

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
tDS tDH
tv(Q) th(Q) CPHA = 1

tDS tDH
tv(Q) th(Q) CPHA = 0

002aae830
Fig 25. SSP slave timing in SPI mode

11. Application information
11.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed.
LPC1xxx
XTALIN
Ci Cg
100 pF
002aae788
Fig 26. Slave mode operation of the on-chip oscillator
In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 26), with an
amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a
square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin
in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 27 and in
Table 17 and Table 18. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (L, CL and RS represent the fundamental frequency).
Capacitance CP in Figure 27 represents the parallel package capacitance and must not be
larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.

LPC1xxx
XTALIN XTALOUT
= CL CP
XTAL
RS
CX1 CX2
002aaf424
Fig 27. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 17. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation Crystal load Maximum crystal External load
frequency FOSC capacitance CL series resistance RS capacitors CX1, CX2
1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF
20 pF < 300  39 pF, 39 pF
30 pF < 300  57 pF, 57 pF
5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF
20 pF < 200  39 pF, 39 pF
30 pF < 100  57 pF, 57 pF
10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF
20 pF < 60  39 pF, 39 pF
15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF
Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation Crystal load Maximum crystal External load
frequency FOSC capacitance CL series resistance RS capacitors CX1, CX2
15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF
20 pF < 100  39 pF, 39 pF
20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF
20 pF < 80  39 pF, 39 pF
11.2 XTAL Printed-Circuit Board (PCB) layout guidelines

Follow these guidelines for PCB layout:
• Connect the crystal on the PCB as close as possible to the oscillator input and output
pins of the chip.
• Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal
use have a common ground plane.

• Connect the external components to the ground plain.

• To keep parasitics and the noise coupled in via the PCB as small as possible, keep
loops as small as possible.
• Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase.
11.3 Standard I/O pad configuration

Figure 28 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver.

• Digital input: Pull-up enabled/disabled.
• Digital input: Pull-down enabled/disabled.
• Digital input: Repeater mode enabled/disabled.
• Analog input.
VDD VDD
open-drain enable
strong ESD
pin configured output enable
pull-up
as digital output
driver data output PIN
strong
pull-down ESD
VSS
VDD
weak
pull-up
pull-up enable
weak
repeater mode
pin configured pull-down
enable
as digital input pull-down enable
data input 10 ns RC
GLITCH FILTER
select data
inverter
select glitch
filter
select analog input
pin configured
as analog input analog input
002aaf695
Fig 28. Standard I/O pad configuration

11.4 Reset pad configuration
VDD
VDD
VDD
Rpu ESD
20 ns RC
reset PIN
GLITCH FILTER
ESD
VSS
002aaf274
Fig 29. Reset pad configuration
11.5 ADC effective input impedance

A simplified diagram of the ADC input channels can be used to determine the effective
input impedance seen from an external voltage source. See Figure 30.
ADC Block
Source
Rmux Rsw Rs
ADC
COMPARATOR <2 kΩ <1.3 kΩ
Rin
Cia
Cio VEXT
VSS
002aah615
Fig 30. ADC input channel
The effective input impedance, Rin, seen by the external voltage source, VEXT, is the
parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculated
using Equation 1 with
fs = sampling frequency
Cia = ADC analog input capacitance
Rmux = analog mux resistance
Rsw = switch resistance
Cio = pin capacitance
R in =  ------------------ + R mux + R sw   ------------------

1 1
(1)
f  C   f s  C io
s ia

Under nominal operating condition VDD = 3.3 V and with the maximum sampling
frequency fs = 400 kHz, the parameters assume the following values:
Cia = 1 pF (max)
Rmux = 2 kΩ (max)
Rsw = 1.3 kΩ (max)
Cio = 7.1 pF (max)
The effective input impedance with these parameters is Rin = 308 kΩ.
11.6 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
• The ADC input trace must be short and as close as possible to the LPC11E3x chip.
• Shield The ADC input traces from fast switching digital signals and noisy power
supply lines.
• The ADC and the digital core share the same power supply. Therefore, filter the power
supply line adequately.
• To improve the ADC performance in a noisy environment, put the device in Sleep
mode during the ADC conversion.
11.7 I/O Handler software library applications

The following sections provide application examples for the I/O Handler software library.
All library examples make use of the I/O Handler hardware to extend the functionality of
the part through software library calls. The library is available on
http://www.LPCware.com.
11.7.1 I/O Handler I2S

The I/O Handler software library provides functions to emulate an I2S master transmit
interface using the I/O Handler hardware block.
The emulated I2S interface loops over a 1 kB buffer, transmitting the datawords according
to the I2S protocol. Interrupts are generated every time when the first 512 bytes have been
transmitted and when the last 512 bytes have been transmitted. This allows the ARM core
to load the free portion of the buffer with new data, thereby enabling streaming audio.
Two channels with 16-bit per channel are supported. The code size of the software library
is 1 kB and code must be executed from the SRAM1 memory area reserved for the I/O
Handler code.
11.7.2 I/O Handler UART

The I/O Handler UART library emulates one additional full-duplex UART. The emulated
UART can be configured for 7 or 8 data bits, no parity and 1 or 2 stop bits. The baud rate
is configurable up to 115200 baud. The RXD signal is available on three I/O Handler pins
(IOH_6, IOH_16, IOH_20), while TXD and CTS are available on all 21 I/O Handler pins.
The code size of the software library is about 1.2 kB and code must be executed from the
SRAM1 memory area reserved for the I/O Handler code.

11.7.3 I/O Handler I2C

The I/O Handler I2C library allows to have an additional I2C-bus master. I2C read, I2C write
and combined I2C read/write are supported. Data is automatically read from and written to
user-defined buffers.
The I/O Handler I2C library combined with the on-chip I2C module allows to have two
distinct I2C buses, allowing to separate low-speed from high-speed devices or bridging
two I2C buses.
11.7.4 I/O Handler DMA

The I/O Handler DMA library offers DMA-like functionality. Four types of transfer are
supported: memory to memory, memory to peripheral, peripheral to memory and
peripheral to peripheral. Supported peripherals are USART, SSP0/1, ADC and GPIO.
DMA transfers can be triggered by the source/target peripheral, software, counter/timer
module CT16B1, or I/O Handler pin PIO1_6/IOH_16.

12. Package outline
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
D B A
terminal 1
index area
E A
A1
c
detail X
e1
C
v C A B
e b
w C y1 C y
9 16
L
8 17
Eh e2
33
1 24
X
terminal 1 32 25
index area Dh
0 2.5 5 mm
Dimensions scale
Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1
max 1.00 0.05 0.35 7.1 4.85 7.1 4.85 0.75

mm nom 0.85 0.02 0.28 0.2 7.0 4.70 7.0 4.70 0.65 4.55 4.55 0.60 0.1 0.05 0.08 0.1
min 0.80 0.00 0.23 6.9 4.55 6.9 4.55 0.45
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33_po
Outline References European

Issue date
version IEC JEDEC JEITA projection
09-03-17
---
09-03-23
Fig 31. Package outline HVQFN33 (7 x 7 x 0.85 mm)

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D B A
terminal 1
index area
A
E A1
c
detail X
C
e1
v C A B y1 C y
e 1/2 e b
w C
9 16
L
8 17
e
Eh e2
1/2 e
1 24
terminal 1
index area 32 25
Dh X
0 2.5 5 mm
Dimensions (mm are the original dimensions) scale
Unit(1) A(1) A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1
max 0.05 0.30 5.1 3.75 5.1 3.75 0.5

mm nom 0.85 0.2 0.5 3.5 3.5 0.1 0.05 0.05 0.1
min 0.00 0.18 4.9 3.45 4.9 3.45 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33f_po
Outline References European

Issue date
version IEC JEDEC JEITA projection
11-10-11
MO-220
11-10-17
Fig 32. Package outline HVQFN33 (5 x 5 x 0.85 mm)

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
y
X
36 25 A
37 24 ZE
e
E HE
A A2 (A 3)
A1
w M
θ
pin 1 index bp Lp
48 13 L
detail X
1 12
ZD v M A
e w M
bp
D B
HD v M B
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
mm 1.6 0.20 1.45 0.27 0.18 7.1 7.1 9.15 9.15 0.75 0.95 0.95 7o
0.25 0.5 1 0.2 0.12 0.1 o
0.05 1.35 0.17 0.12 6.9 6.9 8.85 8.85 0.45 0.55 0.55 0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
00-01-19
SOT313-2 136E05 MS-026
03-02-25
Fig 33. Package outline LQFP48 (SOT313-2)

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
c
y
48 33
49 32 ZE
e
E HE A
A2
(A 3)
A1
wM
θ
bp Lp
pin 1 index L
64 17
1 16 detail X
ZD v M A
e wM
bp
D B
HD v M B
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
max.
mm 1.6 0.20 1.45 0.27 0.18 10.1 10.1 12.15 12.15 0.75 1.45 1.45 7o
0.25 0.5 1 0.2 0.12 0.1 o
0.05 1.35 0.17 0.12 9.9 9.9 11.85 11.85 0.45 1.05 1.05 0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
00-01-19
SOT314-2 136E10 MS-026
03-02-25
Fig 34. Package outline LQFP64 (SOT314-2)

13. Soldering
Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
Ay
Hy Gy SLy By
nSPy
SLx
Bx
Ax
0.60
solder land
0.30
solder paste
detail X
occupied area
Dimensions in mm
P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy
0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3
11-11-15
Issue date 002aag766
11-11-20
Fig 35. Reflow soldering for the HVQFN33 (5x5) package

Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA
evia = 4.25
0.20 SR
W = 0.30 CU
chamfer (4×)
e = 0.65
GapE = 0.70 SP
evia = 1.05
SPE = 1.00 SP
PIE = 7.25 PA+OA

OwEtot = 5.10 OA
SEhtot = 2.70 SP
EHS = 4.85 CU
LbE = 5.80 CU
LaE = 7.95 CU
OIE = 8.20 OA
evia = 4.25
4.55 SR
0.45 DM
SPD = 1.00 SP 0.45 DM
GapD = 0.70 SP
evia = 2.40 B-side

SDhtot = 2.70 SP
Solder resist
4.55 SR covered via
DHS = 4.85 CU 0.30 PH
LbD = 5.80 CU 0.60 SR cover
LaD = 7.95 CU 0.60 CU
(A-side fully covered)

number of vias: 20
solder land solder land plus solder paste
solder paste deposit solder resist

Remark:
occupied area Dimensions in mm Stencil thickness: 0.125 mm 001aao134
Fig 36. Reflow soldering for the HVQFN33 (7x7) package

Footprint information for reflow soldering of LQFP48 package SOT313-2
Hx
Gx
P2 P1 (0.125)
Hy Gy By Ay
D2 (8×) D1
Bx
Ax
Generic footprint pattern

Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650
sot313-2_fr
Fig 37. Reflow soldering for the LQFP48 package

Footprint information for reflow soldering of LQFP64 package SOT314-2
Hx
Gx
P2 P1 (0.125)
Hy Gy By Ay
D2 (8×) D1
Bx
Ax
Generic footprint pattern

Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550
sot314-2_fr
Fig 38. Reflow soldering for the LQFP64 package

14. Revision history

Table 19. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC11E3X v.2.3 20140911 Product data sheet LPC11E3X v.2.2
Modifications: Added part LPC11E35FHI33/501.
LPC11E3X v.2.2 20140114 Product data sheet - LPC11E3X v.2.1
Modifications: ISP mode removed from pin PIO0_3 in Table 3.
LPC11E3X v.2.1 20131230 Product data sheet - LPC11E3X v.2
Modifications: Add reserved function to pins PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6 and
PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7.
LPC11E3X v.2 20131121 Product data sheet - LPC11E3X v.1.1
Modifications: • Parts LPC11E3HFBD64/401 added.
• 8 kB SRAM block at 0x1000 000 renamed to SRAM0 in Figure 5.
• I/O Handler pins added in Table 3.
• Typical range of watchdog oscillator frequency changed to 9.4 kHz to 2.3 MHz.
• Section 11.7 “I/O Handler software library applications” added.
• Condition VDD = 0 V added to Parameter VI in Table 5 for clarity.
LPC11E3X v.1.1 20130924 Product data sheet - LPC11E3X v.1
Modifications: • Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note.
• Table 7: Removed BOD interrupt level 0.
• Added Section 11.5 “ADC effective input impedance”.
• Programmable glitch filter is enabled by default. See Section 7.7.1.
• Table 5 “Static characteristics” added Pin capacitance section.
• Table 4 “Limiting values”:
– Updated VDD min and max.
– Updated VI conditions.
• Table 10 “EEPROM characteristics”:
– Removed fclk and ter; the user does not have control over these parameters.
– Changed the tprog from 1.1 ms to 2.9 ms; the EEPROM IAP always does an erase and
program, thus the total program time is ter + tprog.
LPC11E3X v.1 20121107 Objective data sheet - -

15. Legal information
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Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
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17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 7.17.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 27
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 7.17.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.17.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 27
7.17.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
7.17.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 28
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 7.17.5.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . 28
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.17.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 28
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.17.6 System control . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.17.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7.17.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 29
7 Functional description . . . . . . . . . . . . . . . . . . 18 7.17.6.3 Code security
7.1 On-chip flash programming memory . . . . . . . 18 (Code Read Protection - CRP) . . . . . . . . . . . 29
7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.17.6.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.17.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.17.6.6 External interrupt inputs . . . . . . . . . . . . . . . . . 30
7.5 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.18 Emulation and debugging . . . . . . . . . . . . . . . 31
7.6 Nested Vectored Interrupt Controller 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 Static characteristics . . . . . . . . . . . . . . . . . . . 33
7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 BOD static characteristics . . . . . . . . . . . . . . . 38
7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21 9.2 Power consumption . . . . . . . . . . . . . . . . . . . 38
7.7 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.3 Peripheral power consumption . . . . . . . . . . . 41
7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.4 Electrical pin characteristics. . . . . . . . . . . . . . 43
7.8 General-Purpose Input/Output GPIO . . . . . . . 21 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 46
7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46
7.9 I/O Handler 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46
(LPC11E37HFBD64/401 only) . . . . . . . . . . . . 22 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47
7.10 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.11 SSP serial I/O controller . . . . . . . . . . . . . . . . . 23 10.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11 Application information . . . . . . . . . . . . . . . . . 53
7.12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 23
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.1 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.2 XTAL Printed-Circuit Board
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 (PCB) layout guidelines . . . . . . . . . . . . . . . . . 54
7.14 General purpose external event 11.3 Standard I/O pad configuration . . . . . . . . . . . 55
counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.4 Reset pad configuration . . . . . . . . . . . . . . . . . 56
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.5 ADC effective input impedance . . . . . . . . . . . 56
7.15 System tick timer . . . . . . . . . . . . . . . . . . . . . . 25 11.6 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 57
7.16 Windowed WatchDog Timer 11.7 I/O Handler software library
(WWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.7.1 I/O Handler I2S. . . . . . . . . . . . . . . . . . . . . . . . 57
7.17 Clocking and power control . . . . . . . . . . . . . . 25 11.7.2 I/O Handler UART . . . . . . . . . . . . . . . . . . . . . 57
7.17.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 25 11.7.3 I/O Handler I2C. . . . . . . . . . . . . . . . . . . . . . . . 58
7.17.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 26 11.7.4 I/O Handler DMA . . . . . . . . . . . . . . . . . . . . . . 58
7.17.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 26 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 59
7.17.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 27 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.17.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 67
7.17.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 27
continued >>

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 68
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 68
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16 Contact information. . . . . . . . . . . . . . . . . . . . . 69
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 September 2014
Document identifier: LPC11E3X

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LPC11E3x

32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up

The LPC11E3x operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to

2. Features and benefits

Product data sheet Rev. 2.3 — 11 September 2014 2 of 71

 Power-On Reset (POR).

 Consumer peripherals  Handheld scanners

Product data sheet Rev. 2.3 — 11 September 2014 3 of 71

4.1 Ordering options

[1] For general-purpose use.

Product data sheet Rev. 2.3 — 11 September 2014 4 of 71

LPC11E3x SYSTEM OSCILLATOR

slave slave slave slave

GPIO pins GPIO INTERRUPTS

GPIO pins GPIO GROUP0 INTERRUPTS

GPIO pins GPIO GROUP1 INTERRUPTS

(1) Not available on HVQFN33 packages.

Product data sheet Rev. 2.3 — 11 September 2014 5 of 71

Transparent top view

For parts LPC11E36FHN33/501

Product data sheet Rev. 2.3 — 11 September 2014 6 of 71

Transparent top view

For parts LPC11E35FHI33/501

Product data sheet Rev. 2.3 — 11 September 2014 7 of 71

Fig 4. Pin configuration (LQFP48)

Product data sheet Rev. 2.3 — 11 September 2014 8 of 71

See Table 3 for the full pin name.

Product data sheet Rev. 2.3 — 11 September 2014 9 of 71

6.2 Pin description

Table 3. Pin description

RESET/PIO0_0 2 2 3 4 [2] I; PU I RESET — External reset input with 20 ns glitch

Product data sheet Rev. 2.3 — 11 September 2014 10 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 11 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 12 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 13 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 14 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 15 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 16 of 71

Table 3. Pin description

Product data sheet Rev. 2.3 — 11 September 2014 17 of 71

Table 3. Pin description

7.1 On-chip flash programming memory

Product data sheet Rev. 2.3 — 11 September 2014 18 of 71

On the LPC11E37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to

7.4 On-chip ROM

7.5 Memory map

Product data sheet Rev. 2.3 — 11 September 2014 19 of 71

Fig 6. LPC11E3x memory map

7.6 Nested Vectored Interrupt Controller (NVIC)

Product data sheet Rev. 2.3 — 11 September 2014 20 of 71

7.6.2 Interrupt sources

7.7 IOCON block

7.8 General-Purpose Input/Output GPIO