4 1 Introduction

keep the oversampling factor at a reasonable value while achieving very high
resolution, the technique of noise shaping, which is shaping the quantization noise
such that most of it resides outside the signal passband of interest, comes in handy.
The technique is illustrated in Fig. 1.1c, and it is the main concept behind all
ΣΔ-converters since it is the ΣΔ-modulator in such converters that allow achieving
the noise-shaping characteristic. To give some perspective, the simplest first-order
ΣΔ-modulator provides a 1.5-bit increase per doubling of OSR, resulting in it being
much more efficient than using only oversampling.

1.2.2 The Sigma-Delta Modulator

To understand how noise shaping is achieved, Fig. 1.2a illustrates the basic block
diagram of a low-pass (LP) ΣΔ-modulator, which consists of the following [1]:

• Loop filter
• Quantizer (ADC)
• Feedback digital-to-analog converter (DAC)

The basic idea of ΣΔ-modulation is easy enough to state [4]: to modulate the
analog input signal into a digital word sequence whose spectrum approximates that
of the analog input well in a narrow frequency range but which is otherwise noisy.
This noise arises from the quantization of the analog signal, and the loop filter shapes
the quantization noise such that most of its power lies away from the narrow, desired
frequency range. To accomplish this, filtered negative feedback compensation is
used to obtain the noise-shaping characteristic of the quantization error.

Fig. 1.2 (a) Low-pass

ΣΔ-modulator block diagram
A.
and (b) respective linear
model IN OUT
LOOP FILTER ADC

DAC

B. E= Quantization
Noise

U U-V Y= 1 (U-V) V
H(f )=1/f f

Quantizer
V=Y+E
1.2 Sigma-Delta Converters Fundamentals 5

Following the frequency domain analysis in Fig. 1.2b [6], the loop filter transfer
function corresponds to H( f ) ¼ 1/f. The amplitude response of H( f ) is inversely
proportional to the input frequency, hence resembling a low-pass filter. The quan-
tizer is treated as a white noise source, where the quantization noise E is injected
directly into the output signal. Naming the input signal U and the output signal V, the
signal coming out of the input summer block must equal to U " V. This signal is then
multiplied by the loop filter transfer function, 1/f, and the result summed with E at the
output. By inspection, the expression for the output signal V can then be written as:
1
V ¼ ðU " V Þ þ E ð1:1Þ
f
Rearranging and solving for V in terms of U, f, and E:
U Ef
V¼ þ ð1:2Þ
f þ1 f þ1
where the first term is the signal transfer function (STF) and the second one is the
noise transfer function (NTF). According to Eq. 1.2, as the frequency f approaches
zero, the output signal V approaches U with no noise component. At high
frequencies, the amplitude of the signal component U approaches zero, while the
noise component approaches E; hence the output V consists primarily of
quantization noise. Clearly, the loop filter determines the spectral properties of the
ΣΔ-modulator and has a low-pass effect on the signal and a high-pass effect on the
quantization noise, resulting in the desired noise-shaping characteristic [3].
The loop filter is formed by one or many cascaded integrators connected by a
series of feedback and/or feedforward paths. The number of integrators defines the
loop filter’s order, which determines the aggressiveness of the noise-shaping char-
acteristic in pushing the noise out of the band of interest. Intuitively, the higher the
order of the filter, the lower the noise left in the passband (Fig. 1.3). Unfortunately,
high-order loop filters are difficult to design for reasons that will be discussed to a
great extent later in this book, and so, for now, the important concept to grasp is that
when designing ΣΔ-converters, the main goal is to obtain a loop filter which
provides high stability and few artifacts, such that over the passband [7]:

Fig. 1.3 STF and various

order NTFs 2ND ORDER
NTF

1ST ORDER
1 STF NTF

Signal
Band

0 fs OSR*fs Freq. (Hz)

2 2
6 1 Introduction

OSR*fs fs

INPUT DOWN- OUT

AAF H(f ) ADC DIGITAL
FILTER SAMPLER

DAC

Σ∆ Modulator Decimation Filter

Fig. 1.4 ΣΔ-modulator block diagram

STF ffi 1 and NTF ffi 0 ð1:3Þ

This ensures that the signal passes unchanged, while the noise is being shaped
away from the band of interest.

1.2.3 The Sigma-Delta Analog-to-Digital Converter

Having understood the concept of noise shaping and how this is achieved, a complete
ΣΔ-ADC can now be analyzed. As illustrated in Fig. 1.4, it is formed by [1]:

• Anti-aliasing filter
• Sigma-Delta modulator
• Decimation filter

The anti-aliasing filter [6] is used to band-limit the analog input signal in order to
avoid aliasing during its subsequent sampling. It should be noted at this point that
since ΣΔ-ADCs operate at an oversampling ratio of OSR∗f s , the attenuation
requirements of the analog AAF are greatly relaxed so that smooth transition
bands are usually sufficient compared to Nyquist-rate converters (Fig. 1.5).
Having introduced the frequency domain analysis of the modulator, it is now
fundamental to investigate the ΣΔ-ADC behavior from a time domain perspective
[3]. Since the integrators forming the loop filter are memory [6] elements, each
output of the modulator is generated utilizing all preceding input values. Such
property fundamentally differs from the distinctive one-to-one relation of Nyquist-
rate converters between input and output samples; therefore only a comparison of the
complete input and output waveform allows to evaluate the ΣΔ-converter’s accu-
racy. This concept can be better appreciated by looking at Fig. 1.6. As it can be seen,
in each clock cycle, the value of the output of the modulator is either plus or minus
the full scale of the assumed single-bit quantizer (e.g., '1). When the sinusoidal
input to the modulator is close to a plus full scale, the output of the modulator is
1.2 Sigma-Delta Converters Fundamentals 7

High Order Lowpass

Anti-Alias Filter
for Nyquist Rate
ADC

Low Order Lowpass

Digital Anti-Alias Filter
Filter for Σ∆-ADC
for Σ∆-ADC

0 B B fs-2B 2B Freq. (Hz)

OSR OSR

Fig. 1.5 Nyquist vs. ΣΔ-ADCs anti-aliasing filter requirements

1
INPUT

0
-1
Integrator Input - DIFFERENCE
2
0
-2
Quantizer Input - LOOP FILTER OUT
2
0
-2
Before Decimation - MODULATOR OUT
1
0
-1
After Decimation - PCM
1
0
-1

Fig. 1.6 First-order, single-bit ΣΔ-modulator output at each conversion stage

positive during most clock cycles and vice versa. Thus, it is the local average of the
modulator output that tracks the analog input. When the input is near zero, the output
value of the modulator varies rapidly between a plus and a minus full scale with
approximately zero mean.
The last component of a ΣΔ-ADC is the decimation filter [7]. Since the output of
a ΣΔ-modulator is a stream of bits and since the final bandwidth of the output signal
is to be reduced by the digital filter, the output data rate may also be lowered
(downsampling) from the oversampling ratio of OSR∗f s to the Nyquist rate of fs.
In the process, redundant data caused by oversampling are eliminated while preserv-
ing an accurate AD conversion, since the Nyquist criterion [6] is not to be violated.
8 1 Introduction

TIME DOMAIN FREQUENCY DOMAIN

INPUT
fs/2 fs
Input Signal Input Spectrum

DECIMATOR
fs/M fs/2 fs
Decimation Rate Filter Transfer Function

EFFEC TIVE
SAMPLING
R A T E
OUTPUT
fs/M fs/2 fs
Output Signal Output Spectrum

Fig. 1.7 Decimation

Downsampling is usually desirable in order to minimize the amount of information

for subsequent transmission, storage, or digital signal processing as well as to meet
the working Nyquist frequency of most systems [5]. Downsampling of the output
data rate is achieved by passing every M-th result to the output and discarding the
remainder. The process is better known as decimation by a factor of M, where M can
have any integer value provided that the output data rate is more than twice the input
signal bandwidth. The decimation filtering process in the time and frequency
domains is illustrated in Fig. 1.7. As it can be seen, decimation simply reduces the
output sample rate and does not cause loss of information.
Another important aspect to be aware of is that in ΣΔ-converters the decimation
filter can also be used to provide increased resolution [1, 7]. An example of this is
presented in Fig. 1.8, which shows a 16:1 decimation process with 1-bit input
samples. Although the input data resolution to the decimation filter is only 1 bit,
the averaging method (decimation/downsampling) yields more resolution (4 bits)
through reducing the sampling rate by 16:1. Note that the signal full scale in the
example corresponds to 0 or 1, instead of the '1 of the modulator, due to the digital
nature of the filtering process.

1.3 Essential Performance Metrics

Performance metrics [1, 2] are used to evaluate the behavior of a converter. Contrary
to Nyquist-rate ADCs whose performance is mainly characterized by static perfor-
mance metrics such as gain and offset errors, monotonicity, differential nonlinearity
(DNL), integral nonlinearity (INL), etc. [6] – ΣΔ-ADCs are evaluated by dynamic
1.3 Essential Performance Metrics 9

Fig. 1.8 Increase of SAMPLE RATE REDUCTION MORE RESOLUTION

resolution through decimation
1
0
1
0
0
1 16:1 DECIMATION 7 = 0.4375 = 0111
0 16
1 AVERAGE
1 1 Multi-Bit Output
0
0
0
1
0
1

16 1-Bit Inputs

performance metrics. Dynamic metrics are time-dependent and obtained from the
frequency domain representation of the time domain digital output sequence. This
requires the computation of the fast Fourier transform (FFT) of a finite-length output
sequence with a specific windowing function [6], as it will be explained later. From
that power spectrum representation of a ΣΔ-modulator’s output sequence, some
spectral metrics are directly measured, and other noise and power metrics are
derived. The most common dynamic performance metrics of a ΣΔ-ADC are
illustrated in Fig. 1.9, and include:

• Signal-to-Noise Ratio (SNR): Ratio between the power of the sinusoidal signal
and the total noise power including quantization and circuit noise but excluding
the DC component and distortion, expressed in dB.

! "
PSignal
SNR ðdBÞ ¼ 10log10 ð1:4Þ
PNoise

• Signal-to-Noise and Distortion Ratio (SNDR): Ratio between the signal power of
the fundamental frequency to the power of all other spectrum components,
including noise and distortions, but excluding the DC component, expressed
in dB.

! "
PSignal
SNDR ðdBÞ ¼ 10log10 ð1:5Þ
PNoise þ PDistortions

• Signal to Quantization Noise Ratio (SQNR): Ratio between the fundamental

frequency signal power to the power of the quantization noise, expressed in
dB. The maximum SQNR is achieved with a full-scale input signal because,
according to the linear model [6], the quantization noise power is constant and not
10 1 Introduction

Linear Loss

Overload Loss

0 DR OL Vref Pin (dB)

Full Scale

Signal
SFDR (dBFS)

Harmonics

Noise Floor

0 (f )

Fig. 1.9 Graphical representation of the dynamic performance metrics

signal dependent. Typically used to estimate the upper limit for the theoretical
dynamic performance of the ΣΔ-ADC.
• Spurious-Free Dynamic Range (SFDR): Ratio of the signal power of the funda-
mental frequency to the power of the strongest spectral tone.
• Dynamic Range (DR): Ratio between the power of the full-scale input signal and
the power of the smallest detectable input signal, expressed in dB.
• Total Harmonic Distortion (THD): Ratio of the total power of the harmonics to
the signal power, expressed in dB.
! "
H D, 2 2 þ H D, 3 2 þ . . . þ H D, n 2
THD ðdBÞ ¼ 10log10 ð1:6Þ
H D, 1 2

• Signal to Total Harmonic Distortion + Noise (S/(THD + N)): The ratio of the rms
value of the fundamental input signal to the rms sum of all other spectral
components in the passband, expressed in dB.
1.4 The Role of Simulation in SD-Converter Design 11

• Overload Level (OL): The SNR of a ΣΔ-modulator increases monotonously with

the input signal amplitude but sharply drops for input amplitudes close to half of
the full-scale input range of the embedded quantizer due to its overload and the
associated in-band noise power increase. The overload level is considered to
define the maximum input amplitude for which the ΣΔ-modulator still operates
correctly and can almost be arbitrarily defined, but it is typically chosen as the
amplitude for which the SNR drops 6 dB below the peak SNR [8].
• Effective Number of Bit (ENOB): Effective ADC resolution, expressed in bits.
Assuming a sinusoidal input, it results to be:

SNR ðdBÞ " 1:76

ENOB ðBitÞ ¼ ð1:7Þ
6:02

1.4 The Role of Simulation in SD-Converter Design

Sigma-Delta modulators – irrespectively, from being ADCs, DACs, or even purely

digital designs such as a divider in a fractional-N phase-locked-loop (PLL) – are
typically designed following the “top-down” [8] design approach, which involves
the realization of one or multiple mathematical models in order to predict and
investigate system behaviors, optimize aspects of its performance, and/or compare
competing designs. Only once a satisfactory system-level design is achieved,
detailed implementation and/or circuital issues are considered.
However, it should be noted that Sigma-Delta modulators are nonlinear systems
since a quantizer is implemented in the ΣΔ-loop. Therefore, differently from linear
systems, an exact mathematical analysis is often very difficult or even impossible,
and to date there is no complete theoretical analysis for arbitrary ΣΔ-modulators that
can be used to accurately and unquestionably predict if a proposed modulator design
is going to fully meet its performance targets and do so with no undesirable side
effects [6]. Nevertheless, some useful analytical results that can be used in the design
process of a ΣΔ-modulator have been achieved over the years, including [1]:

• Few specific cases in which an exact mathematical analysis may be possible.

• Some general mathematical analyses become possible when making simplifying
assumptions, but violating these assumptions can result in the real modulator
behaving very differently than predicted (e.g., reduced stability, input signal
range, etc.).
• Some analyses yield only upper or lower performance bounds which may be
considered more like warning guidelines when constructing a new design rather
than as absolute design limits. Therefore, it may be possible to push some designs
to achieve higher performance without incurring in catastrophic results.
• Some commonly used analytical results are just accepted rules of thumb based
more on extensive experience than theoretical consideration! The consequence of
the various approximations and limitations invoked, either to get mathematically
12 1 Introduction

tractable results or simply because experience suggests they are good rules of
thumb, is that extensive system-level simulation is essential to verify whether a
ΣΔ-modulator will indeed perform to specifications when designed using existing
theory and without unwelcome surprises (i.e., instability, saturation, etc.).

Due to the difficulties in developing an accurate mathematical model and the

consequent importance that simulations play in the analysis of the initial design, this
book introduces MATLAB® and Simulink® as very useful tools for system-level
modeling and predicting the performance of ΣΔ-modulators. Important to note is
that, to prevent unwanted behaviors, it is common when designing and simulating
ΣΔ-modulators at system level to include some real circuit implementation effects
[2, 7] since these can have a strong influence on the modulator’s performance. As an
example, these may include:

• Finite signal-swing headroom effects (i.e., soft saturation, hard clipping, etc.)
• Practical circuital limitations (i.e., finite gain and bandwidth, etc.)
• Nonlinearities of the modulator circuits (i.e., quantizer, multi-bit DAC, etc.)
• Effects of systematic or random component deviations (i.e., mismatch)
• Timing issues (i.e., clock jitter in CT modulators, finite settling time, etc.)

These effects, even if only in approximate form, are often included at the system-
level simulation stage due to the fact that circuit-level simulation is typically not an
effective tool for investigating their effects. This is because system-level simulations
usually run at least thousands of times faster than circuit-level simulation using tools
such as HSPICE™ or Spectre™ (seconds/minutes versus hours/days). Considering
that many hundreds or thousands of simulations may be required to convince a
designer that the ΣΔ-modulator designed will behave as expected for likely inputs, it
is unreasonable in terms of simulation time requirements to use only circuit
simulators for examining the consequences of real circuit effects. Including
approximations of circuit effects in the system-level model can, however, allow
their likely effects to be studied under a wide range of modulator operating
conditions and hence hugely increases the likelihood that any problems they cause
will be found, and found early, in the design process.
Given the importance of simulations in ΣΔ-modulators and in order to keep the
focus on the design process, instead of system-level modeling techniques, this book
is accompanied with a dedicated Simulink® Toolbox which allows the reader to
perform all the common simulations required to evaluate a complete design, indi-
vidually investigate the non-idealities affecting single blocks, and even explore some
of the most famous ΣΔ-architectures. Moreover, the Toolbox facilitates the creation
of individual, personalized designs that the reader may want to implement. To
further facilitate the reader in these tasks, the Toolbox exploits a graphical approach,
and so not a single line of code has to be written! Therefore, particular knowledge of
either MATLAB® or Simulink® is not required, and everyone should hopefully be
able to enjoy designing modulators.
Exercises 13

The software is freely available on the MATLAB File Exchange website:

https://www.mathworks.com/matlabcentral/fileexchange/64429-sigma-delta-simulink-
toolbox

1.5 Conclusions and Essential Takeaways

In this chapter, an introduction to the topic of Sigma-Delta Analog-to-Digital

Converters has been provided. The benefits of employing oversampling and
quantization noise shaping in the digitization of signals have been analyzed and
compared to the performance of Nyquist-rate ADCs. Further, the process by which
noise shaping is achieved, along with the role of the various blocks forming a
complete ΣΔ-ADC, has been presented. Finally, essential performance metrics and
the importance of simulations and system-level modeling in the design of ΣΔ-ADCs
have been discussed. Although the rather descriptive tone used in providing initial
information, some very important concepts have been covered, including [1]:

• Oversampling an ADC can increase resolution beyond matching limit of the

analog components – speed is traded for accuracy.
• Simple oversampling (averaging) is very inefficient (0.5 bits increase per dou-
bling of OSR).
• Noise shaping moves quantization noise to high frequencies where it can be
separated from the signal by a low-pass filter (e.g., decimation filter).
• Sigma-Delta modulation is much more efficient (i.e., 1.5 bits increase per dou-
bling of OSR in first-order modulators).
• The spectral properties of noise shaping (aggressiveness) are determined by the
loop filter (i.e., number of integrators) in the ΣΔ-modulator.
• Since the integrators forming the loop filter are memory elements, it is the local
average of the modulator’s output that tracks the analog input.

These concepts have been discussed mainly considering the quantization noise as
the only source of error limiting the resolution of a ΣΔ-modulator. Therefore, in the
following chapters, the effects of non-idealities associated with the practical imple-
mentation of the modulator blocks are to be analyzed.

Exercises

The set of exercises proposed in this first chapter aims not only to test the concepts
covered but also to provide a brief review of the general ADC theoretical knowledge
expected to successfully understand the topic of the book. Although all the essential
information to complete the exercises have been provided, it is highly recommended
to follow the references in the text as a source of additional information in the case
some of the concepts covered are unclear or difficult to understand for the less
experienced reader.