DIGITAL LOGIC DESIGN

DIGITAL DICE
PROJECT REPORT

SUBMITTED BY:
Aysha Tariq 191 Umber Saleem 216

SUBMISSION DATE:
3rd Jun, 2011

TABLE OF CONTENTS
Topic..Page no

Introduction.. 3 Work Distribution. 4 Block Diagram............................. 5 Design Steps............................. 6 7 8 ICs Used........................................... 9 10 11 Schematic Diagram. .. 12 13 Explanation.... 14 15

Results and Achievements. 16 Recommended Future Work..... 16

INTRODUCTION
The electronic dice, throws up a random number from one to six each time the switch is pressed. It has no bias and can never roll on the floor and get lost. The project could be developed fairly easily into a double dice. Also, it provides an interesting introduction to a range of digital circuits - oscillator, counter and logic gates.

ABOUT THE PROJECT:

HOW DOES IT WORK?
When the push switch is pressed to 'throw' the dice, this makes the circuit rapidly cycle through the dice numbers so that an effectively random dice number is displayed by the LEDs when the push switch is released.

DISTRIBUTION OF THE WORK

3

All the work is done equally by us like: Buying of circuit components Circuit patching Testing of ICs Made the circuit working Presentation Project Report

BLOCK DIAGRAM OF THE SYSTEM

The diagram below shows the general arrangement. The pulse generator runs continually at a high speed. When the switch is pressed, this drives the counter, which cycles continually from 1 to 6. When the switch is released the number displayed is effectively random because the counter is running so fast.

DESIGN STEPS
The pulse generator generates the clock pulse and sends the input to the binary counter which starts counting till the time switch is pressed. When we release the switch the 5

counter stops counting and sends it input to the series of logic gates through which the final output is produced that we display using LEDs. The seven LEDs shown in block diagram can be divided into 4 groups labeled L, M, and Q.

TRUTH TABLE FOR THE LOGIC:

KARNAUGH MAPS: FOR L:

BA C 0 1 0 1 1 X 1 X 6 10 0 00 01 11

1 L= B + C

FOR M:
BA 0 1 M= A + C 1 1 1 X 0 X 11 0 1 C 10 00 01

FOR P:
BA 0 0 P= A.C 0 1 0 X 0 X 11 0 1 C 10 00 01

FOR Q:
BA C 1 1 Q= A 0 0 0 X 1 X 11 0 1 10 00 01

Thus four logic outputs are:

Another AND gate is also required to reset the counter on a cycle of six.

ICs USED:
555 timer IC NE555 4516B Cmos IC binary up-down counter 4071B Cmos IC quad 2-input OR gate 4081B Cmos IC quad 2-input AND gate 7404 Hex Inverter

NE 555:
The NE555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA. Pin connections are shown below:

4516B CMOS IC BINARY UP DOWN COUNTER:

The 4516B synchronous up/down binary counter is constructed with MOS Pchannel and Nchannel enhancement mode devices in a monolithic structure. This counter can be preset by applying the desired value, in binary, to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input. Cascading can be accomplished by connecting the Carry Out to the Carry In of the next stage while clocking each counter in parallel. The outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the reset (R) pin.

Pin configuration is shown below:

4071B CMOS IC QUAD 2 INPUT OR GATE:

The 4071B is a positive logic quadruple 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

4081B CMOS IC QUAD 2 INPUT AND GATE:

10

4081B Quadruple 2-input AND Gate provides the positive quadruple 2-input AND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

HEX INVERTOR:

11

SCHEMETIC DIAGRAM:

12

13

WORKING OF THE PROJECT: Components Used:

Logic Board: R9 -1 R10 - 1 R11- 1 C1, C3 C2 U1 555 U2 4516B U3 4071B U4 4081B 7404 10k 27k 2.7k 10nF disc 50V pitch 5mm 220uF x 16V axial pitch 0.5 timer IC NE555 Cmos IC binary up-down counter Cmos IC quad 2-input OR gate Cmos IC quad 2-input AND gate Hex Invertor

Led Board: R1 - 4 R5 - 7 R8 - 1 D1 - 7 TR1 - 3 TR4 - 1 Push Button - 1 10k 2.4k 3.3k 3mm red led, low current, pitch 2.5mm BC547B BC557B

We have patched the circuit on two bread boards. Logic board LED board

14

Logic board contains all the ICs. When the switch is pressed NE 555 generates the clock pulse which we have fed into pin 15 of the binary up/down counter. Counter produces its outputs to at pin 2, 6, 11 and 14, where pin number 2 represents the least significant bit and 14 is the most significant bit. In our project, we have only used pin 6, 11 and 14, reason being that we only have to count 6 on the counter. When the counter counts 6, we reset the counter. When the switch is released counter stops counting and produces its output at pin 6, 11 and 14. These outputs are further fed into logic gates which cause LEDs to glow patched on LED board.

RESULTS AND ACHIEVEMENTS:

15

The major problems faced in obtaining the output were in ne555 and counter. The pulse generating ne555 was not generating the output wave when we tested it through oscilloscope, thus for testing the circuit initially we used function generator to provide input pulse. Later on we arranged a new IC . The up/down counter also didnt work properly. In our project we had to show output on a dice consisting of 7 LEDs, and the counter was required to count up to 6. The output terminal of IC that we had to use were 6, 11 and 14.14th pin is the most significant bit and 6th is the least significant. When we started working either 14th or 6th pin was not working properly and therefore the combinational logic to display the output was not generating proper results. Thus we had to change the IC, and that caused delay in obtaining the final results. The project helped us to learn the working of different components and gave us a deep insight.

Recommended Future Work:

This project can further be extended and can be used to generate musical notes, by replacing the LEDs at output stage by buzzer or any other sound generating component. We are using single counter IC, but by using more counter ICs and combinational logics at the output the circuit can be made complex. Another interesting application that we found is in machine motion control, where devices called rotary shaft encoders convert mechanical rotation into a series of electrical pulses, these pulses "clocking" a counter circuit to track total motion. Furthermore the up/down counter used can also be used for Up/down difference counting, multistage synchronous counting, multistage ripple counting, synchronous frequency divider.

16

17