Switched Capacitor Converter by Prof Mi

This article has been accepted for publication in IEEE Transactions on Power Electronics.
This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2024.3444769
IEEE TRANSACTIONS ON POWER ELECTRONICS
A Novel Single-Phase Common Grounded

Converter Based on Switched-Capacitor
Naser Vosoughi Kurdkandi, Member, IEEE, Oleksander Husev, Senior Member, IEEE, Oleksander Matiushkin, Member,
IEEE, Dmitri Vinnikov, Fellow IEEE, Wei Gao, Member, IEEE, Chunting Chris Mi, Fellow, IEEE
Abstract- This paper presents a new common grounded converter to invest in these technologies. Despite the clear advantages of DC
based on a switched capacitor (SC). The converter can be used as a grids, the absence of a viable business model has been identified
suitable interface for single-phase AC or two-wire DC grids. The as the primary obstacle to their widespread adoption. As a result,
direct connection between the negative terminal of the input voltage
investors are hesitant to fund DC projects, and power electronics
source and the null terminal of the output source enables the
manufacturers are not rushing to produce DC-compatible
elimination of the leakage current in renewable energy systems,
especially in photovoltaic power generation. The proposed topology appliances. One potential solution to this problem could be the
offers voltage-boosting capability, so there is no need for an development of power electronics converters that can be used for
additional boost converter and it is possible to inject power into the both DC and AC applications [8], [9]. This approach would help
grid at DC input voltages lower than the peak value of the output mitigate the risks associated with investing in the DC
voltage, which helps improve the efficiency of the converter. In infrastructure, while also providing greater flexibility for
addition, the proposed topology has the ability to handle reverse consumers. This concept is shown in Fig. 1.
current, hence, it feeds non-unity power factor loads. The operating Rg Lg
modes and design of passive components are described in detail. The
~
performance and advantages of the proposed converter are
compared with other converters. Finally, through the experiment on dc-ac/dc universal
a (3.78 kW/7 kW) converter, the performance of the proposed interface converter with
converter is validated. common ground
Index Terms—Common grounded converter, voltage boosting, Rg Lg
+
single-stage system. -
I. INTRODUCTION Fig. 1. Universal DC-DC/AC interface converter concept.
The ever-increasing energy demands of humanity have led to
In parallel, several technical considerations need to be
a pressing need for new energy sources. It is estimated that by
addressed when implementing dc grids. Of these, grounding and
2050, the global consumption of electrical energy will have been
protection issues are of utmost importance [10]. Numerous
doubled, which highlights the urgency of sustainable energy
approaches to grounding design in electric power systems have
options like solar and wind power, as well as other Renewable
been proposed, each with a unique set of benefits and drawbacks
Energy Sources (RESs), to meet this demand. However, given the
that affect the overall system performance [11]. Grounding is
scale of this task, it is evident that the current electric infrastructure
primarily used for ground fault detection [12], as well as for the
will not be sufficient to support the transition. To mitigate this
safety of personnel and equipment. In the case of low voltage (LV)
challenge, storage elements will be essential in balancing the grid
DC microgrids, grounding can be achieved through either high or
with a high level of RES penetration. Presently, there is no viable
low-resistance grounding, with the ground connected to one of the
business model for this purpose. Additionally, the issue of storage
poles or the middle point, depending on availability. In the context
battery utilization looms as a potential obstacle.
of grounding, low resistance grounding refers to a grounded wire
The resurgence of interest in DC microgrids is largely due to
that has a potential very similar to that of an AC grid. However,
the fact that most RESs and battery storages are DC-based [1]-[2].
when designing the grounding of a DC installation, it is important
This trend is gaining momentum and has become a modern-day
to consider the potential for corrosion of the materials involved.
phenomenon [3]-[6]. A preferred DC voltage level of 325 V has
This is because DC leakage currents can cause electrochemical
been identified as the most technically and economically viable
reactions that may be harmful to concrete structures. To mitigate
option [5]. However, some studies suggest that a DC voltage level
this issue, anti-parallel diodes can be used in series with the
ranging from 350 to 380 V could become the future standard [7].
ground. The use of such diodes is recommended in the NPR
To implement this, a 3-wire DC grid configuration is being
9090:2018 standard as a method of preventing corrosion-related
considered, comprising +350 V, -350 V, and a neutral point.
damage to the installation.
Despite the potential advantages of such a grid, certain problems
The grounding approach utilized in DC grid systems is also
have been identified. Alternatively, a 700 V DC grid has been
influenced by the nature of the interconnection between the AC
proposed as an islanding microgrid for RES integration. While this
and DC grids. In situations where power is transferred between the
grid would allow for efficient energy transfer, it would not be
AC and DC microgrids, this can be achieved through the use of a
compatible with most household devices. In conclusion, the swift
low-frequency transformer in combination with a non-isolated
implementation of DC solutions is hindered by the rapidly
front-end rectifier. In the case of non-isolated power electronics
evolving power electronics landscape and market uncertainty.
This presents a major challenge for large market players looking
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This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and

interfaces, DC-AC energy conversion with a common ground is II. The PROPOSED NINE-LEVEL COMMON GROUNDED
typically the most effective solution. CONVERTER
Several DC-AC converters with common ground capability The topology of the proposed 9-level inverter is shown in Fig.
are presented in [13]-[17]. These converters are based on flying 2(a). In this inverter, nine power electronic switches, two power
inductors (FI), which have the ability to increase the input voltage diodes, and three capacitors are used to produce a nine-level
and can inject power to the output at input DC voltages lower than output voltage. Eight of the switches used in this inverter are
the peak voltage of the grid. However, since these converters are unidirectional and only one switch is bi-directional. For
based on the charging and discharging of the inductor, a large unidirectional switches, a normal MOSFET with an internal
inductor is needed. In [18], a common grounded converter based antiparallel diode can be used. For the bidirectional switches of the
on a flying capacitor (FC) is presented. Due to the presence of the proposed inverter, it is possible to use the series connection of a
boost converter at the input of this topology, it is possible to MOSFET and a diode or the back-to-back series connection of two
operate at input voltages lower than the peak value of the output MOSFETs, as shown in Fig. 2(b). It should be noted that the losses
voltage. In this converter, the combination of an inductor and a of two series MOSFETs with back-to-back connections are lower
capacitor is used to transfer power from the input source to the than in the series connection of a MOSFET and a diode. In
output, which makes the volume of the inductor used in the addition, in order to increase the efficiency of the inverter, active
converter high. In [19]-[21], several three-level common grounded diodes can be used instead of ordinary diodes. According to Fig.
converters based on a switched capacitor (SC) are presented. In 2(a), there is a direct connection between the negative terminal of
these topologies, a capacitor is used to pump power from the input the input voltage source and the neutral terminal of the output
source to the output grid. Since these typologies lack the capability power grid. This feature is suitable for power electronic interfaces
of voltage boosting, they need a boost converter for their input so used in renewable energy systems, especially photovoltaic
that the power transmission process can be performed at lower systems. As a result, the leakage current caused by parasitic
input voltages than the peak voltage of the grid. The presence of capacitors in photovoltaic systems is eliminated. Furthermore, the
an additional boost converter affects the efficiency and volume of ability to handle reverse current in the proposed inverter makes it
the entire system. In [22]-[25], several three-level and five-level possible to control the reactive power at the point of common
common grounded converters based on SC are presented. coupling (PCC) and in the grid-following mode. This inverter
Although these converters have voltage boosting capability, their enables feeding non-unity power factor loads in the grid-forming
voltage gain is limited to two and they will need an additional mode. Considering that the proposed converter is common-ground
boost converter at a lower input voltage. Also, two six-level and and can produce DC voltage with positive and negative polarity in
seven-level typologies are proposed in [26] and [27], respectively, its output terminal, this converter can be used as a suitable
which are a combination of a SC and a neutral point clamp (NPC) interface for AC or DC output application.
converter. Although the leakage current in these topologies is not S3 S6
completely eliminated, its value is low. In addition, their voltage
gain is limited to 1.5 and they will need an additional boost + + S7 +
D1 C1 C2 C3
converter at a lower input voltage. S1 - S4 - S8 - S9
The main purpose of this paper is to present a superior solution
that can work in the DC-AC and the DC-DC mode at the same + Lf
+_ S5 vout
output terminal. The proposed new SC structure with a common Vin - vg ~ D2
S2 Cf
ground feature has the capability of four times voltage boosting
and can perform the power transfer process from the input source
(a)
to the output in a wide range of input voltage. The ability to have
a common ground eliminates leakage current in the system, and
the ability to handle return current provides the possibility of
=
feeding non-unity power factor loads.
In the following, Section II explains the structure of the
(b)
proposed converter. The operation modes of the SC-based
Fig. 2. (a) The proposed nine-level SC-based common-grounded inverter, (b)
converter in the DC-AC condition are outlined in Section III. The bidirectional switches used in the inverter.
switching duty cycle of the inverter is computed in Section IV.
Design considerations for all key components of the solution are The proposed inverter has the ability to boost the voltage up to
described in Section V. The Control system strategy of the four times the input voltage. Therefore, in the grid-forming and
proposed converter is explained in Section VI. Section VII focuses the grid-following mode and at an input voltage lower than the
on the comparative evaluation to validate the performance and peak value of the output voltage, it can feed the load or the grid.
feasibility of the SC converter, while Section VIII provides some In this inverter, the capacitor C1 is charged as much as the input
experimental results. In the concluding section, the feasibility of voltage, the capacitor C2 is charged to twice the input voltage, and
the proposed converter is discussed. the capacitor C3 is charged to four times the input voltage. Since
the proposed inverter is based on the SC technology, the capacitors

are self-balancing, and no additional controller is needed to control source with capacitors C1, C2, and C3 is used. Since the polarity of
the voltage of the capacitors. the capacitor C3 is connected inversely with the polarity of
capacitors C1 and C2 and the input voltage source, the output
III. OPERATION MODES OF THE PROPOSED TOPOLOGY IN DC-
voltage is zero in this operation mode. This mode is the same for
AC STATE
the positive and the negative half-cycle. In this operating mode,
Fig. 3 shows the operating modes of the proposed inverter. The
capacitors C1 and C2 are in the discharging state and capacitor C3
inverter has nine operation modes, of which four operation modes
is in the charging state.
are related to the positive half-cycle and another four to the
vout = Vin + VC + VC − VC = 0 (1)
negative half-cycle. Another operation mode is related to the zero- 1 2 3
voltage vector, which is the same for positive and negative half- B. First-level operation mode in the positive half-cycle
cycles. In the operation modes, the active power path is shown The equivalent circuit of the proposed inverter in the first-level
with red lines, the reactive power path with green lines, and the operation mode of the positive half-cycle is shown in Fig. 3(b). In
capacitor charging path with blue lines. Next, the working modes this mode, when switches S3, S6, S7, and the diode D1 are turned
of the proposed inverter will be discussed. on, +Vin voltage is produced at the output of the inverter. In other
A. Zero-level operation mode words, the output voltage of the inverter is equal to the input
The equivalent circuit of the proposed inverter at zero level is voltage. Turning on switch S2 in this way causes the capacitor C1
shown in Fig. 3(a). In this operation mode, switches S1, S4, S6, S8 to be charged by the input source and through the diode D1. In this
and the diode D2 are on, which causes zero voltage to be produced operation mode, capacitors C2 and C3 are also in a disconnecting
at the output of the inverter. In order to produce zero voltage at the state.
output of the inverter, the series connection of the input voltage vout = Vin (2)
S3 S6 S3 S6 S3 S6
+ + S7 + + + S7 + + + S7 +
C1 C2 C3 C1 C2 C3 C1 C2 C3
D1 S1 - S4 - S8 - S9 D1 S1 - S4 - S8 - S9 D1 S1 - S4 - S8 - S9
Lf Lf Lf
+_ S5 +_ S5 +_ S5
Cf Cf
Vin S2 vg ~ Cf D2 Vin S2 vg ~ D2 Vin S2 vg ~ D2
(a) (b) (c)

S3 S6 S3 S6 S3 S6
+ + S7 + + + S7 + + + S7 +
C1 C2 C3 C1 C2 C3 C1 C2 C3
D1 S1 - S4 - S8 - D1 S1 - S4 - S8 - S9 D1 S1 - S4 - S8 - S9
Lf Lf Lf
+_ S5 +_ S5 +_ S5
Cf Cf Cf
Vin S2 vg ~ D2 Vin S2 vg ~ D2 Vin S2 vg ~ D2
(d) (e) (f)

S3 S6 S3 S6 S3 S6
+ + S7 + + + S7 + + + S7 +
C1 C2 C3 C1 C2 C3 C1 C2 C3
D1 S1 - S4 - S8 - S9 D1 S1 - S4 - S8 - S9 D1 S1 - S4 - S8 - S9
Lf Lf Lf
+_ S5 +_ S5 +_ S5
Cf Cf Cf
Vin S2 vg ~ D2 Vin S2 vg ~ D2 Vin S2 vg ~ D2
(g) (h) (i)

Fig. 3. Operation modes of the proposed 9-level inverter: (a) zero level, 0; (b) first level in the positive half-cycle, +Vin; (c) second level in the positive halfcycle,
+2Vin; (d) third level in the positive half-cycle, +3Vin; (e) fourth level in the positive half-cycle, +4Vin; (f) first level in the negative half-cycle, -Vin; (g) second level in the
negative half-cycle, -2Vin; (h) third level in the negative half-cycle, -3Vin; (i) fourth level in the negative half-cycle, -4Vin.
C. Second-level operation mode in the positive half-cycle When the switch S5 is turned on, the capacitor C2 will be charged
The equivalent circuit of the proposed inverter in the second twice as much as the input voltage. In this operating mode, the
level operation mode of the positive half-cycle is shown in Fig. capacitor C1 is in the discharging and the capacitor C3 is in the
3(c). Switches S1, S3, S6, and S7 are on in this operation mode and disconnecting state.
cause the series connection of the input voltage source with the vout = Vin + VC = +2Vin (3) 1
capacitor C1 to produce +2Vin voltage at the output of the inverter. D. Third-level operation mode in the positive half-cycle

The equivalent circuit of the proposed inverter in the third- For this purpose, switches S2, S3, S6 and S8 are turned on. Diode D1
level operation mode of the positive half-cycle is shown in Fig.3 is also active in this working mode so that it can charge the
(d). Turning on switches S4, S6, and S7 along with the diode D1 capacitor C1 from the input source if needed. In general, in this
causes the voltage of the input source to be transferred to the working mode, the capacitor C3 is discharged, the capacitor C1 is
output of the inverter along with the voltage of the capacitor C2; charged and the capacitor C2 is in the disconnecting mode.
thus, the output voltage of the inverter is equal to +3Vin. Turning vout = VC − VC = − 3Vin
1 3
(8)
on the switch S2 causes the capacitor C1 to be charged by the input I. Fourth-level operation mode in the negative half-cycle
source and through the diode D1. In this operation mode, the Finally, in order to produce -4Vin voltage at the output of the
capacitor C2 is in the discharging state and the capacitor C3 is in proposed inverter, the voltage of the capacitor C3 is connected to
the disconnecting state. the output of the inverter alone, which causes -4Vin voltage to be
vout = Vin + VC = +3Vin
2
(4) produced. For this purpose, switches S8 and S9 need to be turned
E. Fourth-level operation mode in the positive half-cycle on, and the switch S2 is turned on along with the diode D1, which
In order to produce the fourth voltage level at the output of the causes the capacitor C1 to be charged from the input source. In
proposed inverter, capacitors C1 and C2 need to be connected in general, in this operating mode, the capacitor C1 is charged, the
series with the input voltage source. In order to generate +4Vin capacitor C3 is discharged, and the capacitor C2 is disconnected.
voltage at the output of the inverter, it is necessary to turn on The equivalent circuit of the proposed inverter in the fourth-level
switches S1, S4, S6, and S7. Turning on the diode D2 causes the operation mode of the negative half-cycle is shown in Fig. 3(i).
capacitor C3 to be charged four times the input voltage. Therefore, vout = −VC = − 4Vin 3
(9)
in this operating mode, capacitors C1 and C2 are in the discharging
mode and capacitor C3 is in the charging mode. The equivalent In order to better understand the operating modes of the
circuit of the fourth-level operation mode in the positive half-cycle proposed topology, Table I shows the status of the switched-on
is shown in Fig. 3(e). switches as well as the charging and discharging status of the
vout = Vin + VC + VC = +4Vin (5) capacitors in different modes. The "↑" sign means charging the
1 2
capacitor, the "↓" sign means discharging the capacitor, and the
F. First-level operation mode in the negative half-cycle
"–" sign means disconnecting the capacitor.
The equivalent circuit of the proposed inverter in the first-level
TABLE I.
operation mode of the negative half-cycle is shown in Fig. 3(f). In SWITCHING STATE OF THE PROPOSED NINE-LEVEL INVERTER.
this operating mode, switches S2, S4, S6 and S8 are on and cause the Involved Capacitor’s Output
generated voltage by the series connection of three capacitors C1, Levels switches Mode voltage
C2 and C3 to be transferred to the output of the inverter. The output C1 C2 C3
1st (P) S2, S3, S6, S7 ↑ - - +Vin
voltage in this operating mode is equal to -Vin. The duty of the 2nd (P) S1, S3, S5, S6, S7 ↓ ↑ - +2Vin
supplying power in the negative half-cycle is the responsibility of 3rd (P) S2, S4, S6, S7 ↑ ↓ - +3Vin
the capacitor C3. Turning on the diode D1 also causes the capacitor 4th (P) S1, S4, S6, S7 ↓ ↓ ↑ +4Vin
Zero S1, S4, S6, S8 ↓ ↓ ↑ 0
C1 to be charged from the input source. In summary, capacitors C1
1st (N) S2, S4, S6, S8 ↑ ↑ ↓ -Vin
and C2 are charged in this operating mode, and the capacitor C3 is 2nd (N) S1, S3, S5, S6, S8 ↓ ↑ ↓ -2Vin
discharged. 3rd (N) S2, S3, S6, S8 ↑ - ↓ -3Vin
vout = VC + VC − VC = −Vin (6) 4th (N) S2, S8, S9 ↑ - ↓ -4Vin
1 2 3
G. Second-level operation mode in the negative half-cycle IV. SWITCHING DUTY CYCLE CALCULATION FOR THE
In order to be able to produce -2Vin voltage at the output of the PROPOSED NINE-LEVEL INVERTER
inverter, it is necessary to transfer the voltage caused by The 9-level output voltage of the proposed inverter along with the
connecting capacitors C2 and C3 in series to the output of the grid voltage in the positive half-cycle and negative half-cycle is
inverter. For this purpose, switches S5, S6, and S8 need to be turned shown in Fig. 4. According to this figure, the output voltage of the
on. Turning on switches S1, S3 causes the capacitor C1 to charge inverter in the positive half-cycle can be defined in Zone1, Zone2,
the capacitor C2 along with the input voltage source. Thus, in this Zone3, and Zone4. Each of the zones has a different switching
operating mode, capacitors C1 and C3 are discharged and the duty cycle, which will be calculated in the following. The grid
capacitor C2 is charged. The equivalent circuit of the proposed voltage and the grid current in the unity power factor are expressed
inverter in this operation mode is shown in Fig. 3(g). The output by (10) and (11):
voltage of the inverter in this working mode is equal to -2Vin. vg (t ) = Vmax sin t (10)
vout = VC − VC = − 2Vin
2 3
(7) ig (t ) = I max sin t (11)
H. Third-level operation mode in the negative half-cycle A. Zone1
Fig. 3(h) shows the equivalent circuit of the proposed inverter According to Fig. 4, in Zone1, the output voltage of the
in the third-level operation mode of the negative half-cycle. In inverter changes between zero and Vin. By applying the voltage
order to produce -3Vin voltage at the output of the inverter, it is balance law on the output inductor Lf in a complete switching
necessary to transfer the voltage resulting from the series cycle, the duty cycle of the inverter in Zone1 is obtained as
connection of capacitors C3 and C1 to the output of the inverter. follows:

Vgrid , Vout cycle, the duty cycle of the inverter in Zone3 is calculated as
LDC,C2
follows:
4Vin
Zone 4 d3Ts Ts
 (3Vin − vg )dt +  (2V − vg )dt = 0

3Vin
2Vin
Zone 3
in (16)
Zone 2 0 d3Ts
Vin
π 2π Zone 1 vg (t )
wt Vmax
ωt1 ωt2 ωt3 π-ωt3 π-ωt1
π-ωt2 Zone 5 d3 (t ) = −2 =  sin t − 2 ; t2  t  t3 (17)
-Vin Vin Vin
Zone 6
-2Vin
-3Vin
Zone 7 D. Zone4
-4Vin
Zone 8 From Fig. 4, it is clear that the output voltage of the inverter in
LDC,C3 Zone4 changes between +3Vin and +4Vin. Therefore, to calculate
Fig. 4. Nine-level output voltage of the inverter and grid voltage. the duty cycle, it is necessary to write the voltage balance law in a
complete switching cycle for the output inductor Lf. Equations (18)
d1Ts Ts
and (19) show how to calculate the duty cycle for Zone4.
 (Vin − vg )dt +  (−v )dt = 0
g (12) d4Ts Ts
0
vg (t ) V
d1Ts
 (4Vin − vg )dt +  (3V in − vg )dt = 0 (18)
= max  sin t ; 0  t  t1
0 d4Ts
d1 (t ) = (13)
Vin Vin vg (t ) Vmax T
d 4 (t ) = −3 =  sin t − 3 ; t3  t  − t3 (19)
In (12), Ts is the switching period of the inverter. Vin Vin 2
B. Zone2 In order to calculate the time values t1, t2, and t3, equations
It is clear from Fig. 4 that the output voltage of the inverter in (20)-(22) are used.
Zone2 changes between Vin and 2Vin. By applying the voltage
1 −1  Vin 
balance law on the output inductor Lf in a complete switching t1 = sin   (20)
cycle, the duty cycle of the inverter in Zone2 is obtained as   Vmax 
follows:
1 −1  2Vin 
d2Ts Ts
t2 = sin   (21)
 (2V in − vg )dt +  (V in − vg )dt = 0 (14)   Vmax 
0 d2Ts
1 −1  3Vin 
d 2 (t ) =
vg (t ) V
− 1 = max  sin t − 1 ; t1  t  t2 (15) t3 = sin   (22)
Vin Vin   Vmax 
C. Zone3
Using the symmetry of the circuit operation, the negative
Fig. 4 shows that the output voltage of the inverter in Zone3
half-cycle switching patterns can be easily derived. It is omitted
changes between +2Vin and +3Vin, so by applying the voltage
here for simplicity. The duty cycle of each of the switches in
balance law on the output inductor Lf in a complete switching
different operating Zones is shown in Table II.
TABLE II
THE DUTY CYCLE OF SWITCHES IN DIFFERENT OPERATING ZONES.
Switches S1 S2 S3 S4 S5 S6 S7 S8 S9
Positive Zone 1 1-d1(t) d1(t) d1(t) 1-d1(t) 0 1 d1(t) 1-d1(t) 0
half-cycle Zone 2 d2(t) 1-d2(t) 1 0 d2(t) 1 1 0 0
Zone 3 1-d3(t) d3(t) 1-d3(t) d3(t) 1-d3(t) 1 1 0 0
Zone 4 d4(t) 1-d4(t) 0 1 0 1 1 0 0
Negative Zone 5 1-d1(t) d1(t) 0 1 0 1 0 1 0
half-cycle Zone 6 d2(t) 1-d2(t) d2(t) 1-d2(t) d2(t) 1 0 1 0
Zone 7 1-d3(t) d3(t) 1 0 1-d3(t) 1 0 1 0
Zone 8 0 1 1-d4(t) 0 0 1-d4(t) 0 1 d4(t)
V. CALCULATION OF THE OUTPUT FILTER INDUCTOR AND By simplifying (23) and inserting (19) into it, the inductor
CAPACITORS value of the output filter is obtained as follows:
In this section, the value of the output filter inductor along with 1  2
Vmax 
the value of the filter capacitors C1, C2 and C3 are calculated. Lf =  max
7V sin(t ) −  sin 2 (t ) − 12Vin  (24)
I L f  f s  Vin 
A. Calculation of the output filter inductor
In order to calculate the value of the output filter inductor, the At the unity power factor, the maximum current ripple of the
inductor current equation can be written in each of the zones of the inductor Lf occurs at ωt=π/2. Therefore, the value of Lf for the
inverter. Since the current ripple of Lf has its highest value in maximum current ripple is calculated as follows:
Zone4, the current equation for iL(t) is written in Zone4. 1  2
Vmax 
Lf =  7Vmax − − 12Vin  (25)
1 T
I L f ,max  f s 
t
iLf (t ) =
Lf V
0 Lf dt + iLf (0) ; t3  t 
2
− t3 (23) Vin 

To calculate the value of the output filter capacitor Cf, the Double-line frequency power ripple is one of the
capacitor voltage equation can be written for each of the operating characteristics of single-phase systems. If the input voltage source
zones. Since the maximum voltage ripple of the output filter is a battery or a constant voltage source, then there is no need to
capacitor occurs in Zone4, the capacitor voltage equation Cf for remove this power ripple from the input source, but if the input
this zone is written: voltage source is a PV, then the power ripple should be removed
1 t T from the input source. For this purpose, two active and passive
vCf (t ) =
Cf 0 Cf
i dt + vCf (0) ; t3  t 
2
− t3 (26)
methods are used. In the passive method, a parallel capacitor is
I Lf T used with the input voltage source, which is calculated by the
VCf = ; t3  t  − t3 (27) following equation:
8C f f s 2
Pin Pout
1  Vg2,max  Cin = = (34)
Cf = 
2 
7V sin( t ) −  sin 2 (t ) − 12Vin  2  f grid  Vdc  VC ,in 2  f grid  Vdc  VC ,in 
8VCf  L f  f s 
g ,max
Vin 

(28) An advantage of switch-capacitor converters is that they
By placing (24) in (27) and simplifying it, equation (28) can require no additional controller to balance the voltage of the
be obtained. At the unity power factor, the maximum voltage capacitors. However, the disadvantage of these converters is the
ripple of the output filter capacitor occurs at ωt=π/2. Therefore, spike charging current of the capacitors. The spike charging
the value of Cf for the maximum voltage ripple is calculated as current increases the current stress of the switches. It is possible to
follows: reduce the voltage ripple of the capacitors by choosing the right
1  Vg2,max  value of the capacitors and thereby reduce the spike of the
Cf = 
2 
7V − − 12Vin  (29) capacitor charging current and the current stress of the switches. It
8VCf ,max  L f  f s 
g ,max
Vin 
 is also possible to reduce the level of EMI in the converter by
B. Calculation of capacitors C1, C2 and C3 proper PCB design for the power board. However, this issue was
The value of capacitors C1, C2, and C3 will be different in the addressed during PCB design where all switching cells were
multi-level and the three-level operating mode. In the multi-level carefully designed.
operating mode, since the charging and discharging currents of S3 S6
capacitors C1, C2, and C3 have a fraction of the fundamental
frequency, more capacitance is needed to have the allowable + + +
D1 C1 C2 S7 C3
voltage ripple value in the capacitors. In the three-level operating S1 - - S8 -
S4
mode, since the charging and discharging current of the capacitors
works at the switching frequency, a high capacitance is not needed S5 S9
S2 Lf
to achieve the allowable voltage ripple value in the capacitors. To +_ + D2
DC1 DC2 vout
calculate the value of the capacitors in the multi-level mode, the LC1 LC2 ~ - LC3
Vin vg
longest discharge (LDC) time can be used, which is shown in Fig.
4. Therefore, the capacitance values of capacitors C1, C2 and C3
are calculated by the following relations: Fig. 5. Proposed converter with capacitive charging current spike limiting
2 Pout (Vmax − 3Vin )
strategy.
C1 = (30)
VC1,max  f s  Vin  Vmax As a result, spreading of the electromagnetic field was minimized.
In fact, it is one of the reasons of our good results related to good
 −1  3Vin 
 −t3 4 P  cos  sin    efficiency. Another way to reduce the spike charging current in SC
C2 =
t3
iC 2 d (t )
=
out
  Vmax 
(31)
converters is to use a low value inductor in the charging path of
VC 2,max VC 2,max Vmax the capacitors. The location of these inductors in the proposed
converter is shown in Fig. 5. This technique is described in [36].
 −1  Vin  In Fig. 5, the charging current of each of the capacitors C1, C2 and
2 −t1 4 P  cos  sin   
C3 =
 i d (t )
 +t1 C 3
=
out
  Vmax 
(32)
C3 passes through the inductors LC1, LC2 and LC3, and thus, the
VC 3,max VC 3,max  Vmax spike charging current of the capacitors is limited. Considering
that the inductors LC1 and LC2 are placed in series with the switches
In (30), (31) and (32), the parameters VC1,max , VC 2,max ,
S2 and S5, to ensure that there is a current path for these inductors
VC 3,max , and Pout are the voltage ripple of capacitors C1, C2, C3, when the switches S2 and S5 are turned off, the diodes DC1 and DC2
and the injected power to the grid, respectively. The value of the are paralleled with the inductors LC1 and LC2. But a parallel diode
capacitors in the three-level operating mode is calculated as is not necessary for the inductor LC3 because this inductor is in
follows: series with the diode D2 and can form its path through the capacitor
2 Pout C3 and the internal diode of the switch S9.
C1 = C2 = C3 = (33)
3Vin  VC ,max  f s It is important to mention that the experimental results in this
study were obtained without the presence of inductors LC1, LC2 and
LC3 and diodes DC1 and DC2. Appropriate and accurate design of

the power board has made it possible to obtain experimental cycles required for realizing this voltage. These values are then fed
results from the proposed converter in the DC-DC mode up to 7 to the pulse width modulation (PWM) block. The MPPT and PLL
kW and in the DC-AC mode up to 3.78 kW, without EMI being blocks are not discussed in detail here. It can be concluded from
able to disrupt the operation of the microcontroller and its reset. the literature review that a conventional second order generalized
Also, the proposed converter showed high efficiency, which was integrator (SOGI) regulator is one the best options for PLL [31].
directly measured by the power analyzer. Similarly, the most common methods for the realization of MPPT
are the perturb and observe (P&O) or incremental conductance
VI. CONTROL SYSTEM DESCRIPTION
(IC). Some of the studies utilize modifications of the P&O or IC
Fig. 6 illustrates the block diagram of the control strategy for MPPT methods [32]-[35]. Various options exist for implementing
the proposed converter. The study considers various control the grid current control. In this case, the proportional-resonant and
modes. Prior to connecting the grid-side slid-state circuit breaker repetitive (PRR) controller is used for the AC mode, while the PI
(SSCB), the control system identifies the type of the grid available. controller is employed for the DC mode. Detailed tuning of the
In the case of an ac grid, the phase-locked loop (PLL) ensures PRR controller is described in [28], [29], and [30]. A proportional
synchronization. Once the voltage zero crossing is detected, the component eliminates possible injection of the DC current into the
SSCB is connected to the grid, and the AC grid-connected grid. Additionally, alternative nonlinear methods like Model
algorithm becomes operational. If the PLL fails to detect the AC Predictive Control (MPC) could be considered, as they have been
grid, the control system checks the DC voltage. found to be feasible for industrial implementation and suitable for
achieving desired output currents in the discussed solutions.
VIN
Vg yes Sin(Θ)
In common-grounded converters, due to the direct connection of
PLL d1(t)
S1the negative terminal of the input DC source and the neutral
? I*g i*g PRR Vmod
Eqs. (16), d2(t)
.
no regulator
(18),(20) d3(t) PWM . terminal of the AC grid, in the positive half-cycle, the injected
VIN and (22) d4(t) S9power to the output or AC grid is supplied directly from the input
no MPPT
dc or ig source. But in the negative half-cycle, the injected power to the
grid Reference
? IIN Definition VIN output or AC grid is supplied by the energy stored in the capacitor
yes I*g PI Vmod
regulator Eqs.
Dbuck S1or the inductor (in this proposed converter, it is provided by the
Dboost1 . capacitor). Therefore, it can have some DC-offset in the output
(10), (11) PWM
VREF* and (12) Dboost2
.
Reference voltage S9current, which is not a problem specific to the converter proposed
here, and all common-grounded converters have this problem.
Fig. 6. Simplified block diagram of the applied control system.
Pout =1kW Iout,ma x =6.15 A
If the DC grid is detected, the output capacitor is pre-charged to
the same voltage level, and SSCB switches on with the appropriate
DC current control mode. The control system can employ various
methods for the grid current controller, whether for DC or AC
grids. No additional computational resources are needed, as only Open-loop control
one strategy (DC or AC) is used at any given time. The control %THD =% 3.49
system is capable of injecting DC and AC harmonics, which are
Idc=(0.0019)*6.15=11mA
utilized to detect islanding operation. When islanding is detected,
the converter halts and restarts only after receiving the
corresponding external permission for the grid-forming operation.
Fig. 7. FFT analysis of the output current under open-loop control condition.
For solar applications, the maximum power point tracking
(MPPT) block is essential to adjust the reference grid current (Ig*)
based on the observed operation point on the PV array. The Pout =1kW Iout,ma x =6.15 A
approach for solar converters is similar. In battery applications, the

MPPT block is replaced by reference current generation,
considering measured voltage (Vin) and current (Iin). In the case of
AC grid connection, the AC reference grid current (ig*) is derived Close-loop control
by multiplying the reference current (Ig*) with a sinusoidal signal
%THD =% 0.13
from the PLL block. The reference ig* waveform is synchronized
with the fundamental component from the voltage at the point of Idc=(0.000045)*6.15=0.27mA
common coupling (PCC) (Vg) using scalable factors. The
difference between the reference ig* and the real grid current (ig)
Fig. 8. FFT analysis of the output current under close-loop control condition.
is then provided to the current control block. The current controller
produces a reference voltage (VMOD*) to be applied across the However, if the converter is controlled by the close-loop control
output capacitor (Cf). The intermediate calculation block utilizes system, the DC-offset value can be greatly reduced and brought
the measured input voltage to determine the corresponding duty close to zero. It is also important to mention that common-

grounded converters eliminate the leakage current caused by the capacitors of other converters, the values of the passive
dissipation capacitors of the solar panels. Here, in order to show components were obtained, which are given in Table III.
the DC-offset of the proposed converter and its elimination by the In all the compared converters as well as in the proposed
control system, a simulation was conducted. In this simulation, the converter, the value of the output filter capacitor was chosen equal
input voltage is 400 V DC, the output voltage is 230 V rms, the to 3.3 µF. The value of internal resistance for 1 mH inductor was
switching frequency is 32 kHz, the value of capacitors C1, C2 and considered equal to 0.2 Ω.
C3 is equal to 22 µF, the value of the output filter inductor is equal TABLE III
THE VALUES OF THE PASSIVE COMPONENTS IN THE COMPARED CONVERTERS
to 0.45 mH, and the value of the output filter capacitor is equal to Topologies Values of passive components
1 µF. The simulation was done in two open-loop and close-loop JESTPE-[13] L1=0.78mH, Lf=0.1mH, Cf= 3.3µF
scenarios; the FFT-analysis of the output current is shown for both TIE-[14] L1=0.78mH, L2=0.78mH, Lf=0.1mH, C2=10µF, Cf=3.3µF
scenarios. JESTIE-[18] L1=1.25mH, Lf=2.05mH, C=6µF, Cf= 3.3µF
TIE-[15] Lm=0.74mH, Lf=0.1mH, Cf= 3.3µF
Fig. 7 shows the FFT analysis of the output current in the open- TEC-[22] Lf=1mH, C1=22µF, C2=22µF, C3=100µF, Cf=3.3µF
loop control mode. In this figure, the output power is about 1 kW TPEL-[23] Lf= 0.77mH, C1= 4000µF, C2= 30µF, Cf=3.3µF
and the THD of the output current is 3.4%. Also, the DC-offset TPEL-[24] Lf= 0.75mH, C1=2000µF, C2=2000µF, Cf=3.3µF
RPG-[25] Lf=0.9mH, C1=1500µF, C2=100µF, C3=350µF, Cf=3.3µF
value of the output current is about 11 mA. In Fig. 8, the FFT
To match the internal resistance of all inductors, the following
analysis of the output current is shown in the output power of 1
formula was used:
kW and in the close-loop control mode. The THD value of the
Rnew Lnew
output current is equal to 0.13% and the DC-offset value is around = (35)
0.27 mA, which is a very low value. Therefore, it is concluded that Rold Lold
the control system used in this converter has very well addressed
In order to evaluate the volume of energy storage elements, the
the DC-offset problem.
value of stored energy in them can be calculated. Equations (36)
VII. COMPARATIVE STUDY and (37) show the total stored energy inside the inductors and
In this part, the performance of the proposed converter is capacitors of the converters. In these formulas, the capacitor and
compared with several other converters in order to demonstrate the the inductor in the output filter are also considered.
NL
VolL  WL = 0.5   Li  I L2,max
advantages and disadvantages of the proposed design. As the (36)
converters to be compared are designed on different power levels i =1
and conditions and with different power electronic devices and NC
facilities, they cannot be compared based on the information VolC  WC = 0.5   Ci  VC2,max (37)
i =1
reported in previous research. Since the converter proposed in this
In the above, NL and NC are the number of capacitors and
paper can produce both AC and DC voltage in its output, the
inductors in the converter, and ILmax and VCmax are the maximum
converters used for our comparison are able to produce AC and
current of the inductors and the maximum voltage of the
DC voltage in their output. For a fair comparison, the compared
capacitors.
converters were simulated in the same conditions using
To calculate the total standing voltage (TSV), equation (38)
MATLAB/Simulink. The converters compared are described in
was used, and this parameter is based on the input voltage.
[13]-[15], [18], and [22]-[25]. Data for the simulation are as N D + NS
follows: 1 kW output power, 200 V input voltage, 230 Vrms  Vi
output voltage, and 30 kHz switching frequency. The internal TSV = i =0
(38)
resistance of all switches and diodes is 50 mΩ, and the internal Vin
voltage drop of the diodes is 0.7 V. By choosing 1 mH for the In (38), ND and NS are the number of switches and diodes.
output filter of the proposed converter, its current ripple is about Table IV shows the comparison between the proposed converter
31%. By choosing 22 µF for each of the capacitors C1, C2, and C3, and other converters. WL and WC denote the total stored energy
their voltage ripple value is around 4.2%. By considering the same inside the inductors and capacitors of the converters. TSV shows
current ripple for the inductors and the same voltage ripple for the the total standing voltage in the switches and diodes, which is
based on the input voltage.
TABLE IV
COMPARISON TABLE BETWEEN PROPOSED CONVERTER AND OTHER CONVERTERS
Topologies NS ND NC NL WL WC (J) TSV Boosting Vin Vout Pout PCON MSV Reported
(mJ) (p.u.) factor rms (kW) (W) Efficiency
JESTPE-[13] 8 - 1 2 111.7 0.1743 13.4 d/(1-d) 200V 230V 1 41 Vin+Vout 97.5%@0.8kW
TIE- [14] 6 - 2 3 148.8 0.7024 11.13 d/(1-d) 200V 230V 1 30 Vin+Vout 97.6%@0.8kW
JESTIE- [18] 6 - 2 2 106.2 1.17 13.85 d/(1-d) 200V 230V 1 22 Vin+Vout 97.8%@1.5kW
TIE- [15] 10 - 1 2 106.3 0.1743 14.375 d/(1-d) 200V 230V 1 46 Vin+Vout 94.2%@0.3kW
TEC- [22] 6 3 4 1 18.9 10.2 18 2 200V 230V 1 32 2Vout 97.9%@0.5kW
TPEL- [23] 9 - 3 1 14.6 80.6 11 2 200V 230V 1 25 Vout 97.2%@0.6kW
TPEL- [24] 7 2 3 1 14.2 164 17 2 200V 230V 1 35 2Vout 98.1%@0.6kW
RPG- [25] 6 3 4 1 17 66 19 2 200V 230V 1 29 2Vout 97.5%@0.7kW
Proposed 9 3 4 1 18.9 2.81 14 4 200V 230V 1 26 Vout 98%@1.3kW

The parameter of the boosting factor shows the voltage gain of than the proposed converter. Instead, the proposed converter has
the converters and finally, PCON gives the total conduction losses twice the voltage gain compared to the converter in [23] and the
of the converters and MSV indicates the maximum switching capacitor stored energy in the converter in [23] is much higher than
voltage of the converters. The topologies in [13], [14], and [15] in the suggested converter. Fig. 9 shows a bar graph to compare
are based on flying inductors and the topology in [18] is based on the proposed converter with other converters and provide a better
flying capacitor technologies. In the topologies of [13], [14], and understanding of its advantages and disadvantages. The
[15], the process of power transfer from the input source to the information in this chart is extracted from Table IV.
grid or the output load is monitored by charging and discharging The number of capacitors (NC) and inductors (NL) in each
the inductor. Although converters in [13] and [14] have fewer converter has been added to the comparison table. Although the
switches than the proposed converter, the conduction losses in proposed converter has four capacitors (taking into account the
these converters are higher than in the proposed converter. Also, output filter capacitor for all converters), the total amount of
even though these converters have lower total capacitor stored energy stored in the capacitors is lower than in all the switch-
energy and TSV than the proposed converter, the value of stored capacitor converters [22]-[25], which is the reason of the low
energy inside the inductors of the converters in [13] and [14] is capacity of the capacitors in the proposed converter. The capacity
much higher than that of the proposed converter. The converter in of the capacitors used for each converter in the comparison section
[18] has less losses and fewer switches than the proposed is given in Table III. The converters in Table IV are completely
converter, and the value of stored energy in the capacitor is half of made in different conditions with different output power. In
that of the proposed converter, but the value of stored energy in reference [15], the output power is 0.3 kW, in references [22],
the inductor of the converter in [18] is much higher than that of the [24], [25], the power is around 0.7 kW and without PCB, made on
proposed converter. It is important to mention that another part of ready-made boards, while the proposed converter is made for 4
inductor losses is related to core losses, which are not considered kW/7kW power, and the PCB is designed for it. Therefore, it is
here. The presence of core losses brings about an increase in the not possible to compare the converters in Table IV in terms of cost
converter losses in [18]. In terms of TSV, both converters are of materials and overall size. Even in the case of the same power
almost the same, so that the TSV of the proposed converter is level, it is very difficult to provide fair cost analysis as it depends
slightly higher than that of the converter in [18]. The value of the on the supply chain and logistics. In the following, the volume of
capacitor stored energy of the converter in [15] is lower compared the proposed converter and its power density are calculated. Also,
to the proposed converter. This converter does not have a diode; the reported efficiency of each of the converter is given in Table
instead, the conduction losses and the TSV of that converter are IV. In order to calculate the power density of the proposed
higher than those of the proposed converter. The value of stored converter, it is necessary to calculate the volume of the energy
energy in the inductor in this converter is much higher than that of storage elements as well as the volume of the heatsink:
the proposed converter. Finally, this converter has fewer diodes
Volume _ Heatsink = L  W  H = 240  200  40 = 1924 cm3
and one more switch than the proposed converter. The topologies
in [22]- [25] are based on the SC technology and power is (39)
transferred from the input source to the output side by the Volume _ L f = 9.4  8.1 2.8 = 213.19 cm2 (40)
capacitors.
Volume _ C1,2,3 = 3  ( 4.1 2.2  3.6 ) = 97.41 cm3
Comparison Chart
(41)
1
0.9
0.8 Volume _ C f = 3.15 1.5  2.45 = 11.57 cm3 (42)
0.7
0.6 The total volume of the converter is calculated from the following
0.5
0.4
equation:
0.3
0.2 Total _ Volume = 1924 + 213.19 + 97.41 + 11.57 = 2246.17 cm3
0.1
0
(43)
N_S N_D WC WL TSV PCON
[13] [14] [18] [15] [22] [23] [24] [25] Proposed
Finally, the power density of the prototype is calculated as
Fig. 9. Comparison of the proposed converter and other converters. follows:
Pout 7000
The topologies in [22], [24], and [25] have fewer switches than the Power Density = = = 3.116 W / cm3
Total _ Volume 2246.17
proposed converter; in converters [23] and [25], the value of the
(44)
stored energy in the inductor is lower than that of the proposed
converter. However, these converters have higher conduction VIII. EXPERIMENTAL RESULTS
losses, the voltage gain is lower, and the TSV is higher than that of In this section, several experimental results are presented to
the proposed converter. Also, in these converters, the stored validate the performance of the proposed inverter. To control and
energy in the capacitors is higher than that of the proposed generate PWM pulses for the switches, the TMS320F28379D
converter. Finally, the converter in [23] has no diode and a lower series microcontroller from Texas Instrument was used. All the
TSV than the proposed converter. It also has about 1 W less voltage and current sensors, the isolator between the
conduction losses and about 4.9 mJ lower inductor stored energy microcontroller and the gate drivers, as well as the MCU unit are

placed in one board. Fig. 10 shows the designed experimental
setup. In order to feed the power circuit, programmable DC power
supply Chroma 62150H-1000s was used. For efficiency
measurements of the proposed inverter in different conditions, a
YOKOGAWA-WT1806E power analyzer was applied. A
Tektronix MDO4034B-3 oscilloscope was employed to measure
and display the required results. All the switches, gate drivers, gate
driver power supply, output filter, and the value of the capacitors
are shown in Table V. Instead of conventional diodes, active
diodes are used. The output of the inverter uses an LC filter instead
of an L filter. Fig. 11(a) shows the 9-level inverter output voltage,
load voltage, load current, and input current. In this figure, the
input voltage value is equal to 100 V, and the peak output voltage
equals 400 V. Therefore, this proposed topology produces four (a) (b)
Fig. 10. (a) Power board of the experimental setup, (b) control board of the
times higher voltage gain. The peak voltage of the load is equal to experimental setup.
325 V and the peak current of the load equals 4 A, so the power is Fig. 12(a) shows the performance of the proposed inverter in the
0.65 kW. Fig. 11(b) shows the voltage of each of the capacitors three-level working mode. Since the frequency of charge and
C1, C2, and C3. According to this figure, the capacitor C1 is charged discharge of capacitors C1, C2, and C3 is equal to the switching
as much as the input voltage, the capacitor C2 is charged twice the frequency, it results in a low value of the capacitor. In this figure,
input voltage, and the capacitor C3 is charged four times the input the output voltage of the inverter, the voltage and current of the
voltage. load, as well as the input current are provided. The input voltage
TABLE V
PARAMETERS OF THE PROPOSED UNIVERSAL CONVERTER
is 400 V, and the output power is 3.78 kW. It should be noted that
Parameters Value at 3.78 kW, the value of each of the capacitors is equal to 22µF.
Output voltage in dc- 230 V rms/ 350 V dc Fig. 12(b) shows the voltage and current of the load along with the
ac/dc-dc
input voltage and current of the inverter. In this figure, the input
Output power 3.78 kW(dc-ac)/ 7 kW(dc-dc)
Switching frequency 32 kHz voltage is equal to 400 V, and the output power equals 3.78 kW.
Output filter inductor Lf 0.45 mH Fig. 12(c) shows the performance of the proposed inverter in the
Output filter capacitor 3.3 µF condition of a step change in the output load. In this figure, the
Power switches C3M0030090K
Capacitor C1 0.56 mF in multi-level, 22 µF in three-level
output load has been changed from 1.8 to 3.6 kW, and it can be
Capacitor C2 1.12 mF in multi-level, 22 µF in three-level seen that the performance of the inverter is stable under step
Capacitor C3 1.36 mF in multi-level, 22 µF in three-level change conditions. In Fig. 12(c), the input voltage is equal to
Gate driver power MGJ2D121505SC 400V. Fig. 13(a) and (b) show the performance of the proposed
supply
Gate drivers ACPL-H342 converter at other input voltages. These two figures show the load
As the proposed converter is SC-based, there is no need for an voltage and current along with the input voltage and current. In
additional controller to control the voltage of the capacitors. In Fig. 13(a), the input voltage is equal to 200 V, and the output
addition, along with the voltage of the capacitors, this figure shows power equals 2 kW. Furthermore, in this working mode, only
the output current. Fig. 11(c) illustrates the performance of the capacitors C1 and C3 are in the path of the current and output
proposed converter in the seven-level mode where the output power, the capacitor C2 is disconnected, and the voltage gain is
voltage of the inverter, the load voltage along with the load current equal to two.
are shown. The input voltage is equal to 135 V, and the output
power equals 0.8 kW.
ILoad (2.5A/div)
Vout (200V/div) VLoad (250V/div) Vout (200V/div)
VC3 (100V/div) VC2 (100V/div)

VLoad (250V/div)
VC1 (50V/div) ILoad (5A/div)
ILoad (5A/div) IIN (50A/div)
(a) (b) (c)

Fig. 11. (a) The nine-level output voltage of the inverter, load voltage and current, and input current in the output power at 0.65 kW and 200 V input voltage, (b) the
voltage across capacitors C1, C2, C3 along with the load current, (c) the seven-level output voltage along with the load voltage and current at 0.8 kW and input voltage
of 135 V.
Vout (500V/div) ILoad (20A/div) ILoad (25A/div) VLoad (200V/div) ILoad (25A/div) VLoad (200V/div)
VIN (200V/div) VIN (200V/div)

IIN (25A/div) VLoad (200V/div) IIN (20A/div) IIN (20A/div)
(a) (b) (c)

Fig. 12. (a) The output voltage of the inverter, load voltage and current, and input current at 3.78 kW and 400 V input voltage, (b) load voltage and current, and input
voltage and current at 3.78 kW and input voltage of 400 V, (c) load voltage and current, and input voltage, and current in the step-change condition from 1.8 kW to 3.6
kW.
ILoad (10A/div) VLoad (200V/div) ILoad (10A/div) VLoad (200V/div) ILf (10A/div)
VIN (100V/div) VIN (50V/div) VLoad (100V/div) VIN (100V/div)

IIN (20A/div) IIN (20A/div)
IIN (10A/div)
d
(a) (b) (c)
Fig. 13. The load voltage and current, and the input voltage and current: (a) at 2 kW and with the input voltage of 200 V, (b) at 1.13 kW and the input voltage of 135 V
(c) DC-DC operation mode: output inductor current and load voltage, and input current and input voltage at 7 kW and the input voltage of 500 V.
VLoad (100V/div) VLoad (100V/div)
ILf (2.5A/div) VLoad (100V/div) VIN (100V/div) ILf (5A/div) VIN (50V/div) ILoad (2.5A/div)
VIN (100V/div) IIN (20A/div) Vout (500V/div) IIN (10A/div)
(a) (b) (c)

Fig. 14. DC-DC operation modes, input voltage and load voltage: (a) input current and output inductor current with the input voltage of 200 V, the load voltage of 350 V
and the output power of 2.49 kW, (b) output voltage Vout before the LC filter, and output inductor current, with the input voltage of 200 V, the load voltage of 350 V, and
the output power of 1.75 kW, (b) input current and load current with the input voltage of 150 V, the output voltage of 350 V and the output power of 0.9 kW.
In Fig. 13(b), the input voltage is equal to 135 V and the output DC condition with 200 V input voltage, 350 V output load voltage,
power equals 1.13 kW. The voltage gain in this working mode is and 2.49 kW output power. In this figure, the input voltage and
equal to three and all the capacitors are in the output power path. current are shown along with the load voltage and output inductor
Since the converter in this study is proposed for DC-AC and DC- current. Since the average value of the load current is equal to the
DC applications, it is necessary to show its performance in the DC- average value of the output inductor current, according to the blue
DC mode. For this purpose, Fig. 13(c) demonstrates the correct figure, the average value of the output inductor current is around
operation of the converter in the DC-DC working mode. In this 7.1 A. As a result, for the load voltage of 350 V, the output power
figure, the input voltage and the current of the converter are shown is 2.49 kW. Fig. 14(b) shows the output voltage Vout before the LC
along with the output voltage and the current of the output filter. In this figure, the input voltage, load voltage, output voltage
inductor. The input voltage is 500 V and the output voltage is 350 Vout, and output inductor current ILf are shown. The average output
V. Since the output current is equal to the average value of the current equals 5 A, and at the load voltage of 350 V, the output
output filter inductor current, it can be concluded from Fig. 13(c) power value equals 1.75 kW. Fig. 14(c) is given shows the voltage
that the output load current is equal to 20 A. DC output current boosting capability of the proposed converter in the DC-DC mode
with an average value of 20 A and output voltage of 350 V results to the best possible extent where the input voltage equals 150 V,
in an output power of 7 kW. Therefore, the power in Fig. 13(c) is the load voltage equals 350 V, and the output power equals 0.9
equal to 7 kW. Fig. 14(a) shows the experimental result in the DC- kW.

VLoad (250V/div) ILoad (25A/div)
VIN (250V/div) Vout (500V/div) VIN (250V/div) VLoad (250V/div) VIN (250V/div) VLoad (250V/div)
PF=0.267 Leading ILoad (25A/div) ILoad (25A/div)
IIN (10A/div)
IIN (10A/div)
(a) (b) (c )
Fig. 15. (a) Non-unity power factor mode: load voltage and current, output voltage and input voltage at the output power of 1.71 kVA, the power factor of 0.267 Leading,
and at the input voltage of 400 V, the input voltage and current, and the load voltage and current at the output power of 2.2 kW: (b) during the transition at the input
voltage from 200 to 350 V, (c) during the transition at the input voltage from 350 to 200 V.
VIN (250V/div) VLoad (250V/div) VIN (250V/div) VLoad (250V/div) VIN (250V/div) VLoad (250V/div)
IIN (10A/div) ILoad (25A/div) IIN (10A/div) ILoad (25A/div) IIN (10A/div) ILoad (25A/div)
(a) (b) (c)

Fig. 16. Zoomed mode of Fig. 15(b) during the transition in the input voltage and at the output power of 2.2 kW: (a) input voltage is lower than the peak value of the load
voltage (b) input voltage is equal to the peak value of the load voltage, and (c) input voltage is higher than the peak value of the load voltage.
Vout (200V/div)
VIN (200V/div) Vout (200V/div) VIN (250V/div) VLoad (250V/div)
IGrid (20A/div)
THD=5.62% ILoad (25A/div)
VIN (200V/div) VGrid (200V/div) THD=1.19% IIN (10A/div)
VGrid (200V/div) IGrid (20A/div)
(a) (b) (c)

Fig. 17. DC-AC in the grid-connected condition: input voltage, grid voltage and current, and output voltage (a) with the input voltage of 400 V, the grid voltage of 230
Vrms, and the output power of 2.53 kW, (b) grid injected current with the THD of 5.62% and the output power of 2.53 kW, (c) the THD of the output load current in the
local load conditions, with the input voltage of 400 V, the output power of 2.99 kW, and the THD of 1.19% for load current.
Experimental efficiency in dc-ac mode Experimental efficiency in dc-ac mode Experimental efficiency in dc-ac mode Experimental efficiency in dc-dc mode
100
98 98 98
98
Efficiency %
Efficiency %
Efficiency %
Efficiency %
96 96 96
96
94 94 94
Vin=400 V Vin=200 V Vin=135 V 94 Vin=400 V
92 92 92
92 Vin=200 V
90 90 90
0 0.5 1 1.5 2 2.5 3 3.5 4 90
0 0.5 1 1.5 2 2.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 1 2 3 4 5 6
Output power (kW) Output power (kW) Output power (kW) Output power (kW)
(a) (b) (c) (d)

Fig. 18. Experimental efficiencies in DC-AC modes: (a) with the input voltage of 400 V, (b) with the input voltage of 200 V, (c) with the input voltage of 135 V, (d)
experimental efficiency in the DC-DC mode with the input voltage of 200 V and 400 V.
Therefore, it can be concluded from Fig. 14 that the proposed the leading power factor mode, which can be created by the RC
converter, in addition to the DC-AC operating mode, also has the load at the output of the inverter. Fig. 15(a) shows the input
ability to increase the voltage in the DC-DC operating mode. voltage, the output load voltage and current, and the voltage of the
In order to show the ability of the proposed converter to control inverter. In this figure, the input voltage is 400 V, the output
and support the reactive power, the experimental result is given in apparent power is 1.71 kVA, the active power is 0.46 kW, and the

output reactive power is 1.65 kVAR. The output leading power V, 97% at 200 V, and 96% at 135 V input voltage. Also,
factor is equal to 0.267. For this amount of the power factor, the experimental efficiency in the DC-DC working mode is presented
phase difference between the output load voltage and the current in Fig. 18(d). In this figure, two efficiency curves are given for the
is equal to 74.47 degrees. This value of the output power factor input voltages of 200 V and 400 V. Fig. 18(d) shows that the
means that the proposed converter is able to control the reactive maximum efficiency is 97.5% for the 200 V input voltage and 99%
power at lower power factors. for the 400 V input voltage.
Fig. 15(b) demonstrates the performance of the proposed IX. CONCLUSION
converter for changes in the input DC voltage. In this figure, the In this paper, a new power electronic interface based on SC
input voltage and current, as well as the load voltage and current was presented. The proposed converter is common grounded,
are shown. In order to demonstrate the stability of the proposed which eliminates the leakage current in photovoltaic systems and
converter, changes were applied to the input voltage, which increases the safety of the system. The ability to boost four times
increased from 200 to 350 V. In Fig. 15(b), despite the changes in the input voltage makes the proposed converter capable of
the input voltage, the load voltage and current are kept constant by supplying the loads at input voltages lower than the peak value of
the control system. Therefore, in the process of changing the input the output voltage without the need of an additional boost
voltage, the output load power is constant and is equal to 2.2 kW. converter. An explanation of the operating modes as well as the
The constant of the output power has caused the input current to design of the values of the passive components were provided. A
decrease when the input voltage increases. In the case of a grid- comparison was made between the proposed converter and other
connected solar system, the behavior will be different, but these converters in order to evaluate the pros and cons of the proposed
tests show the ability of performance with changing input voltage. converter. The experimental efficiency curves were shown for
In Fig. 15(c), the input voltage changes from 350 to 200 V, while different input voltages and in two states, DC-DC and DC-AC,
the output voltage, current and output power remain constant, and with all these curves directly extracted from the power analyzer.
the converter maintains its stability. Fig. 16 shows the zoomed Finally, to show the accurate operation of the proposed converter,
state of Fig. 15(b) at three different points. In Fig. 16(a), the input experimental results were presented in the DC-AC and the DC-DC
voltage is lower than the peak value of the load voltage; in Fig. working modes and at power levels of 3.78 kW and 7 kW, which
16(b), the input voltage is equal to the peak value of the output is not typical for SC solutions. In turn, it demonstrates the
load voltage, and in Fig. 16(c), the input voltage is higher than the feasibility of such approaches for industrial applications. Due to
peak of the output load voltage. According to these figures, despite the minor presence of magnetic materials and corresponding
the changes in the input voltage, the voltage and current of the conduction losses, a very flat efficiency curve can be achieved. To
output load are constant, which indicates proper operation of the increase the lifespan of switched-capacitor converters and to use
control system and stability of the converter. Fig. 17(a) shows the them at higher power levels, it is recommended to use a converter
result of the proposed converter in the DC-AC mode and when the in which the capacitors can be charged and discharged at the
converter is connected to a single-phase grid with the voltage of switching frequency. In this way, low-value capacitors can be
230 Vrms and frequency of 50 Hz. This figure shows the input used, with film capacitors being a suitable option for this purpose.
voltage, grid voltage and injected current into the grid, and output
voltage of the inverter. The value of the input voltage is equal to ACKNOWLEDGMENT
400 V and the injected power to the grid is 2.53 kW. According to The authors would like to acknowledge the financial support
Fig. 17(a), the output voltage of the inverter is well synchronized of the California Energy Commission under grant number EPC-
with the grid, and the proposed converter works in grid-connected 19-053.
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This article has been accepted for publication in IEEE Transactions on Power Electronics.

IEEE TRANSACTIONS ON POWER ELECTRONICS

A Novel Single-Phase Common Grounded

IEEE TRANSACTIONS ON POWER ELECTRONICS

IEEE TRANSACTIONS ON POWER ELECTRONICS

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

IEEE TRANSACTIONS ON POWER ELECTRONICS

IEEE TRANSACTIONS ON POWER ELECTRONICS

 (3Vin − vg )dt +  (2V − vg )dt = 0

IEEE TRANSACTIONS ON POWER ELECTRONICS

IEEE TRANSACTIONS ON POWER ELECTRONICS

approach for solar converters is similar. In battery applications, the

IEEE TRANSACTIONS ON POWER ELECTRONICS

and conditions and with different power electronic devices and NC

IEEE TRANSACTIONS ON POWER ELECTRONICS

IEEE TRANSACTIONS ON POWER ELECTRONICS

VC3 (100V/div) VC2 (100V/div)

(a) (b) (c)

IEEE TRANSACTIONS ON POWER ELECTRONICS

VIN (200V/div) VIN (200V/div)

(a) (b) (c)

VIN (100V/div) VIN (50V/div) VLoad (100V/div) VIN (100V/div)

VLoad (100V/div) VLoad (100V/div)

VIN (100V/div) IIN (20A/div) Vout (500V/div) IIN (10A/div)

(a) (b) (c)

IEEE TRANSACTIONS ON POWER ELECTRONICS

PF=0.267 Leading ILoad (25A/div) ILoad (25A/div)

(a) (b) (c)

VGrid (200V/div) IGrid (20A/div)

(a) (b) (c)

(a) (b) (c) (d)

IEEE TRANSACTIONS ON POWER ELECTRONICS

IEEE TRANSACTIONS ON POWER ELECTRONICS

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