Digital Electronics Pulse Technique

Lecture 1 Review of CSE250

This course consists of two parts
turn
EENETETH init discrete time
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1Terminologiest Éo Hage between two points is the
difference in energy level of unit charge
located at each of the two points

15É ÉÉ
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to move an unit chargefrom
point A to B
VAB Z VA VB VBA VB VA VAB
Unit of voltage Vote V

currentFlow of e across any

charge
cross section of a conductor or a semiconduct
Unit of current Ampere A
Direction
Igf 141
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Resistor an element which opposes resist
current flow
A conductor with specific resistance
Mt 52
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a Unit is Ohm r
Short circuit
A device with zero
resistance

open circuit
A device with infinite
resistance

MITTER
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point of connection between the
terminals of two or more circuit elements

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Any elements that is connected between

two nodes of a circuit

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circuit
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s
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 PARTS Review of CSE 251

Electronic Non linear I V characteristic

Devices to help implement complex
logic
functions
intrinsic Pure
Semiconductor
Extrinsic Impure
rape
N type

digestion DA
NÉPÉATHOPE

I A
10112nA
I Is Nt 2
0.2598
efponential relation bet
I VD
threshold voltage to turn the
diode on so current can flow
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solve by hand
in TDD

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Bipolar Junction O Two
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like Emitter in forward Activemode.So UBC RA BE FA 0

Lecture 03: DL and RTL

BIPOLAR UNIPOLAR

i
t

Whos Transistorisswitched
i
between

off active regions

UPTO Lee 11812

holes
ayyy
Unipolar
I charge carrier either e
 ate

Replaced bulky and costly active vaccum tubes

Uses diodes silicon to construct logic gates

FFÉÉÉ and vis su and for alfanin.TT

a Indochineoutfit'rottage levels
b Find out the maximum power dissipation

RBI O 25122

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when conducting

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a Find output voltage levels
2 input or gate
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2 5
15 EE 7 4 944

b Maximum Power Dissipation

put
no sina.gl Y
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a
5 0 X I
5 0 0 043mA
Vo
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Practice Problem
Vo oft
l
IÉ value of y 30 find the output voltage levels considering

input voltage level to be ON and 12N

Iput logics lov case I 22K

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As input Vi 12W lets assume
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120
findest
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ievds finpu.ae
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Any 2 transistors
are
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effin
I

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if
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1 210 1 3

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i

All 3 transistors are in saturation

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0.2845 LB
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Lecture 04: RTL( power dissipation, Noise Margin and Fan-out)

problemIT Find the total power dissipation of the given

RTL circuit

Iii paths
120 ti

I
0
SI 0 128mA

3 5,0700mA
1
IV I P 1213 12 4123 0.128mA
Power dissipation P
12 0 Bt k
1P 84mnf
74 when in saturation
 i

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As Q is in cutoff VBE o c o su
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i
0 104mA

Ferassiptionstout
0 1 14 x 0 104mA

1m t

É t
É
logicI
 RTL Noise Margin

NoiseMargity
Mani mum allowed voltage imposed on input
so the
gate does not malfunction or give wrong op
Do Ian.at ageisaddedwith

logic'sFER'SOUTPUT

it logicO
Vit logic I

ZIie saturatedlogi
shtudbo.ae

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 Vol 0.2 V Von 12 o 5 v 11 5 arbitary
value
given in Question

Twisiygintifurn on the transistor

ie
161 141 Tfutinputofload.transistory
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load to turn on malfunction
i IL 0.125mA
i 4
o.zryqty.IE
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LYL
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T.si F atentorwaraaavemoot
But if input is decreased

Tiatterwaratiettransition
from 12N

point
Marginal Value
samtg o.gr
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2173 V

Viv NoiseMargin min UNH Vive

IFt
É maximum number of logic gates
e

inputs of the same logic family that can a output

drive reliably without changing disturbing the output
levels Fan out can be defined with N

To Do I 31

Driver 11 Ito I N XI

p
LOAD
E
yFanoutin
This driver drive 3 loads without changing the
can

output level The tanout

1532
IProblemI calculate the fan out of this RTL circuit

Assume Monty

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at Vn IDriver I

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at me IDriver I
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Fanout for von lov a

whendriver's input is logic 2 High it can

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IproblemI If the value of N No of fan out 5

operate as Rgae.Assumbe is same for

all circuits Assume B Forward 301

93 GU i

t Étggetmin transistors should

3
gg 5XVgE
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IB 111452 08
2 0.767mA
450N
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stored min BE
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saturation proved
Lecture 05: DTL( power dissipation, Noise Margin and Fan-out)

II Iai
is

IRTLINVERETZ

RTL
I Better fan out than
A
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 Festering
BITE all inputs are high then what is magnitude
of noise voltage at one of the input terminals
which will cause the gate to malfunction Assume no

load connected

i
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IRTLINVEREERI

STUN Malfunction s
I prey normal
VA
putt kg bad Malfunction
A O b U ETurntsthe Diode
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all the current flow
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to cutoff
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 Poison
f
ny of the input isnow then what is magnitude
f noise voltage at the low input terminal
rich will cause the gate to malfunction Assume no
oad connected to the output

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é
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caseII ALL input 5V I NO LOAD CONDITION

o 5V

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Lecture 07: TTL( Transistor Transistor Logic ( power dissipation, Noise
Margin and Fan-out)

IC g

11 BTI men
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t
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In isoplanar integrated circuit
technology multiple emittersbase
are fabricated in the same

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IT Requires less silicon Area
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INOUTOFBASICTLNANDGATFÉ
In the totempole circuit the transistorparameters are Bf 25 and
Bp 0 10 foreach input emitter VoH 3.4 V
a calculate Maximum fanout for Vn Vy 5 V IcaoloadI
Fcf
5V v Iv Do
a
KaseIl Input Vu Ivy o

I i

Icp IB tIE t I Ez
f 81 MA IB Tz load
IRE GET 0.8mA
Fez Fez E Bz FIT IBefIÉ Éo
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Note As Ic so if current is given as
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I
VoH T 3 aV

d
t 41 2 61 y
yen XFL
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ICTz Noload 54
ILY FEI TRIB 1541 0.1 0 0675mA

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Maximum Fanout Min 61 5

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 brtd Ed Eddd
In the totempole circuit the transistorparameters are Bf 20 and
Br 0.10 foreach input emitter q.LY

a calculate Maximum fanout for Va Vy 5 V

b Calculate Maximum fanout for Va Vy O IV
Assume No is allowed to decrease by o lov
from no load condition
5V Do
a
KaseIl Input Va Vy

É
i

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i
0.45mA
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a Calculate Maximum fanout for Va Vy O IV
Assume No is allowed to decrease by o lov
from no load condition

VoH No load
Volt Loaded
3 GV
3.6 01010 3 50
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b Calculate power dissipation for driver circuit for

fan out of co
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 Lecture 09 & 10
I 1
ADC Analog to
Digital converter
DAC Digital to
Analog converter

MEET

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i
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totheandogsignal
Icomparatory Compares between two inputs and outputs either logics or
logic
jp 4IiDifvin7Vref
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77Design a 3 bit
Flash ADC Find the resistor and comparator
required by the ADC Given Vin TV and Vref IOU
1501 N 3 Resistor required 2N 23 8

4,7 comparator required 23 1 7

HIEI
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i a litigating
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considering the quantization error

if
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A slightly more sophisticated design known as the
dual-slope, integrating ADC (Figure 1, on the right).
Here, two integrations are performed, one on the input
signal and one on VREF.

Figure 2, illustrates the behaviour for two separate

samples.
• Initially switch S1 is open and S2 is connected to
-va’.The input voltage in this case is assumed to be
negative, so that the output of the inverting
integrator results in a positive slope during the first integration.
• Assuming that the S/H is ideal, the gain of the integrator at the end of the first integration period,
T1, becomes

• The first integration is of fixed length, ( 2^n cycles= N

2^n* 1clock period, should be the duration of T1).
This integration will be dictated by the counter, in
which the sample-and-held signal is integrated,
resulting the first slope.
• The output at the end of T1 is positive since the
input voltage is considered to be negative and the
integrator is inverting.
• After the counter overflows ( once T1 is fully
completed) and is reset, the reference voltage is connected to the input of the integrator.
• This action resets the clock and the discharging commences, with the initial condition defined by
the value of the integrator output at the end of the charging period, or

(2)

• A counter again measures the amount of time for the integrator to discharge, thus generating the
digital output.( the total number of completed clock cycles counted by the counter should be the
time required by T2-> equivalent to D)
• Since vIN was negative and the reference voltage is positive, the inverting integrator output
begins discharging back down to zero at a constant slope.
• Once the value of the integrator output, VC , reaches zero volts, Eq. (2) becomes
(4)
131 Or

• At the end of the conversion, the dependencies on R and C have canceled out. Since we also
know that the counter increments 2^n times at time, T1 , and the counter increments D times at
time, T2, Eq. (4) can be rewritten as
Vin D¢T
= n or
VREF 2 :T
• where D is the counter output that is actually the digital representation of the input voltage. e.g. if
D= 3, variable time T2 will complete 3 clock cycles and the digital output should be 011.
For Fig. 2, a 3-bit ADC is being used. Thus,
the first integration period continues until the
beginning of the eighth (2^3) clock pulse,
which corresponds to the counter’s
overflow bit.

• Note that the integrator’s output

corresponding to VB is twice the value of
the output corresponding to VA.
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 14.4 Dynamic Operation of the CMOS Inverter 1125

14.4 Dynamic Operation of the CMOS Inverter

The speed of operation of a digital system (e.g., a computer) is determined by the propagation
delay of the logic gates used to construct the system. Since the inverter is the basic logic gate of
any digital IC technology, the propagation delay of the inverter is a fundamental parameter in
characterizing the speed of a given technology. We begin our study of the dynamic operation
of CMOS in Section 14.4.1 by considering the propagation delay of a general inverter circuit.
There, we introduce key definitions and analysis methods that are applied in the CMOS case
in Sections 14.4.2 and 14.4.3.

14.4.1 Propagation Delay

The propagation delay is the time the inverter takes to respond to a change at its input. To
be specific, let us consider an inverter fed with the ideal pulse shown in Fig. 14.27(a). The
resulting output signal of the inverter is shown in Fig. 14.27(b). We make the following two
observations.

1. The output signal is no longer an ideal pulse. Rather, it has rounded edges; that is, the
pulse takes some time to fall to its low value and to rise to its high value. We speak of
this as the pulse having finite fall and rise times. We will provide a precise definition
of these shortly.
2. There is a time delay between each edge of the input pulse and the corresponding
change in the output of the inverter. If we define the “switching point” of the output as
the time at which the output pulse passes through the half-point of its excursion, then
we can define the propagation delays of the inverter as indicated in Fig. 14.27(b). Note
that there are two propagation delays, which are not necessarily equal: the propagation
delay for the output going from high to low, tPHL , and the propagation delay for the

vI

VDD

0 t
(a)

tPHL tPLH

VDD

VDD
2 Figure 14.27 An inverter fed with the
t ideal pulse in (a) provides at its output
0
the pulse in (b). Two delay times are
(b) defined as indicated.
1126 Chapter 14 CMOS Digital Logic Circuits

output going from low to high, tPLH . The inverter propagation delay tP is defined as
the average of the two,

1
tP ≡ (tPLH + tPHL ) (14.41)
2

Having defined the inverter propagation delay, we now consider the maximum switching
frequency of the inverter. From Fig. 14.27(b) we can see that the minimum period for each
cycle is

Tmin = tPHL + tPLH = 2tP (14.42)

Thus the maximum switching frequency3 is

1 1
fmax = = (14.43)
Tmin 2tP

At this point the reader is no doubt wondering about the cause of the finite propagation time
of the inverter. It is simply a result of the time needed to charge and discharge the various
capacitances in the circuit. These include the MOSFET capacitances, the wiring capacitance,
and the input capacitances of all the logic gates driven by the inverter. We will have a lot
more to say about these capacitances and about the determination of tP shortly. For the time
being, however, we make two important points:

1. A fundamental relationship in analyzing the dynamic operation of a circuit is

I!t = !Q = C!V (14.44)

That is, a current I flowing through a capacitance C for an interval !t deposits a

charge !Q on the capacitor, which causes the capacitor voltage to increase by !V .
2. A thorough familiarity with the time response of single-time-constant (STC) circuits
is of great help in the analysis of the dynamic operation of digital circuits. A review of
this subject is presented in Appendix E. For our purposes here, we remind the reader
of the key equation in determining the response to a step function:
Consider a step-function input applied to an STC circuit of either the low-pass or
high-pass type, and let the circuit have a time constant τ . The output at any time t is
given by
! "
y(t) = Y∞ − Y∞ − Y0+ e−t/τ (14.45)

where Y∞ is the final value, that is, the value toward which the response is heading,
and Y0+ is the value of the response immediately after t = 0. This equation states that
the output at any time t is equal to the difference between the final value Y∞ and a
gap whose initial value is Y∞ – Y0+ and that is shrinking exponentially.

3
This is a theoretical upper bound; practical circuits are operated at frequencies 10 to 20 times lower.
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Propagation delays and transition time for a logic Inverter

• As shown, an input pulse with finite (nonzero) rise and fall times is applied. The inverted pulse at the
output exhibits finite rise and fall times (labeled tTLH and tTHL, where the subscript T denotes
transition, LH denotes low to high, and HL denotes high to low).

• There is also a delay time between the input and output waveforms. The usual way to specify the
propagation delay is to take the average of the
high-to-low propagation delay, tPHL, and the
low-to-high propagation delay, tPLH .

• As indicated, these delays are measured

between the 50% points of the input and output
waveforms.

• Also note that the transition times ( tf- fall time

and tr- Rise time) are specified using the 10%
and 90% points of the output excursion (VOH-
VOL)
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During the discharge delay tPHL, QN replaced by an equivalent resistance RN . Similarly, during the
charging delay tPLH, replaced by an equivalent resistance RP.

It is easy to show that tPHL = 0.69RN*C and tPLH = 0.69RP*C

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