Semiconductors

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CHAPTER
14
Solids and
Semiconductor
Devices
Solid is a state of matter which has a definite shape and a definite volume. Most Inside
of the solids can be classified in three types as per their electrical conductivity,
i.e. conductors, insulators and semiconductors. 1 Energy bands in solids
Energy band formation in solids
Conductors are those materials through which electric charge can flow easily,
Classification of solids on
while insulators are those through which electric charge is difficult to flow. There the basis of energy bands
are, however, certain solids whose electrical conductivity is intermediate between
2 Types of semiconductors
conductors and insulators. They are called semiconductors. Silicon and germanium
Electrical conduction through
are a few examples of semiconductors. semiconductors
In this chapter, we will discuss basic concepts of semiconductor physics and some Effect of temperature on
semiconductor devices like junction diodes (two electrode device) and bi-polar conductivity of semiconductor
junction transistor (three electrode device). Then, we will explore the basics of 3 p-n junction
logic gates. Semiconductor diode or
p-n junction diode
p-n junction diode as a rectifier
Classification of conductors, Special types of p-n junction diode
semiconductors and insulators 4 Junction transistors

Transistor circuit configurations
On the basis of the relative values of electrical conductivity (σ ) or resistivity Transistor as an amplifier
(ρ = 1/σ ), the solids are broadly classified as Transistor as an oscillator
(i) Conductors or Metals They possess very low resistivity (or high Transistor as a switch
conductivity). 5 Analog and digital circuits

Binary system
ρ ~ 10 −2 - 10 −8 Ωm Decimal and binary
number system
σ ~ 10 2 - 10 8 Sm−1 6 Logic gates
(ii) Semiconductors They have resistivity or conductivity intermediate to Logic system
metals and insulators. Combination of logic gates
NAND and NOR gates as
ρ ~ 10 −5 - 10 6 Ωm digital building blocks
σ ~ 10 5 - 10 − 6 Sm−1
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854 OBJECTIVE Physics Vol. 2
(iii) Insulators They have high resistivity (or low These intervals are called forbidden bands (as shown in
conductivity). the figure). It is also called forbidden energy gap because
ρ ~ 10 11- 10 19 Ωm free electrons cannot exist in this gap.
321
σ ~ 10 −11- 10 −19 Sm−1 Conduction band
The values of ρ and σ given above are indicative of
123
321
Energy Forbidden
magnitude and could well go outside the ranges as well. bands bands
123
321
Valence band
ENERGY BANDS IN SOLIDS Fig. 14.1 Forbidden bands in a solid
According to Bohr model, the energy of electrons in an If however, the adjacent energy bands in a solid overlap,
isolated atom is decided by the orbit in which it revolves. the electrons have a continuous distribution of allowed
When two atoms comes close to each other to form solid, energies as shown in the figure.
their outer orbits of electrons come very close or even Conduction band
overlap. Thus, the motion of electron in a solid is different
321
123
from that in isolated atom. In a crystal, each electron has a Continuous
Overlapping energy
distribution
unique position, i.e. no two electrons can have the same of energies bands
position. So, each electron will have a different energy
level and these different energy levels with continuous
Valence band
energy variation are called energy bands.
Fig. 14.2 Overlapping of energy bands
Valence band and conduction band Note As temperature increases, forbidden energy gap decreases.
The energy band which includes the energy levels of
valence electrons is called valence band and the energy Fermi energy
band above it, is called conduction band. It is the maximum possible energy possessed by free
In isolated condition, i.e. with no external energy, all the electrons of a material at absolute zero temperature (i.e.
valence electrons will reside in valence band. Normally, 0 K). The value of fermi energy is different for different
conduction band is empty but when it overlaps on valence materials.
band, electrons can move freely into it. Example 14.1 The maximum wavelength at which solid begin
to absorb energy is 10000 Å. Calculate the energy gap of a
Energy band gap solid (in eV).
If there is some energy gap between the conduction band hc
Sol. The energy band gap is given by E g = hν =
and the valence band, then electrons in the valence band λ
will remain bound and no free electrons will be available where, h = Planck’s constant, c = speed of light and
in conduction band. λ = wavelength at which solid absorbs energy.
The energy band gap is also defined as the difference On putting the values of h, c and λ, we get
between the highest valence band energy (EV ) and lowest (6.626 × 10−34 )(3 × 108 )
Eg =
conduction band energy (E C ). (10000 × 10−10 )
i.e. E g = E C − EV 1.98 × 10−19
= 1.98 × 10−19 J = eV = 1.24 eV
The energy gap for different materials is different. 1.6 × 10−19
Note If λ is the wavelength of radiation used in shifting the electron

from valence band to conduction band, then energy band gap Energy band formation in solids
(Eg ) is
The electronic configuration of a solid like sodium atom
Eg = hν = hc / λ which has 11 electrons is 1s 2, 2s 2, 2p 6 and 3 s 1. The
where, h is called Planck’s constant and c is the velocity of light. levels 1s, 2s and 2p are completely filled. The level 3s is
half filled and the levels above 3s are empty.
Forbidden bands or Forbidden energy gap Consider a group of N sodium atoms all in ground state
The various energy bands in a solid may or may not separated from each other by large distances such as in
overlap depending upon the structure of solid. If they do sodium vapour. There are total 11N electrons. Each atom
not overlap, then the intervals between them represent has two energy states in 1s energy level, so there are 2N
energies which the electrons in the solid cannot have. identical energy states labelled as 1s and all of them are
Solids and Semiconductor Devices 855
filled from 2N electrons. Similarly, energy level 2p has Conductors (Metals)

6N identical energy states which are also completely
filled. In 3s energy levels, N of the 2N states are filled by In case of metals, either the conduction band is partially
the electrons and the remaining N states are empty. filled and valence band is partially empty or conduction
band and valence band overlap to each other.
These ideas are shown in the table given below
In case of overlaping, electrons from valence band can
Total occupied easily move into conduction band, thus large number of
Energy level Total available energy states
states electrons are available for conduction. In case, when
valence band is empty, electrons from its lower level can
1s 2N 2N
move to higher level making conduction possible.
2s 2N 2N This is the reason why resistance of metals is low or the
2p 6N 6N conductivity is high.
Overlapping
Electron energies
3s 2N N Conduction band
(Eg ≈ 0)
3p 6N 0 EV
EC
Valence
In the above discussion, we have assumed that N sodium band
atoms are widely spread and hence the electrons of one
atom do not interact with others. Fig. 14.4 Energy band gap for conductors
As a result, energy states of different states (e.g. 1s) are
identical. When atoms are drawn closer to one another, Insulators
electron of one atom starts interacting with the electrons In insulators, the valence band is completely filled
of the neighbouring atoms of the same energy states. whereas the conduction band is completely empty.
e.g. 1s electrons of one atom interact with 1s electrons of As there is no electron in conduction band, so no electrical
the other. conduction is possible. The energy gap between
Due to interaction of electrons, the energy states are not conduction band and valence band is so large (E g > 3 eV)
identical, but a sort of energy band is formed. that no electron in valence band can be provided so much
energy from any external source that it can jump this
Thus, the collection of these closely spaced energy levels
energy gap.
are called an energy band. Empty
These bands are shown in figure given below conduction
EC band
Electron energies
Total states = 2N Eg > 3 eV

3s Occupied = N
Empty = N EV
Valence
Total states = 6N band
2p Occupied = 6N
Fig. 14.5 Energy band gap for insulators
2s Total states = 2N
Occupied = 2N Semiconductors
The energy band structure of a semiconductor is shown in
1s Total states = 2N
Occupied = 2N figure. It is similar to that of an insulator but with a
comparatively small energy gap (E g < 3eV ). At absolute
Fig. 14.3 Formation of energy bands in solids zero temperature, the conduction band of semiconductors
is totally empty and valence band is completely filled.
Classification of solids on the basis Therefore, they behave as a insulators at low temperatures.
of energy bands However, at room temperature, some electrons in the
valence band acquire thermal energy greater than energy
Depending on whether the energy band gap is zero, large band gap and jump over to the conduction band where
or small, the solids may be classified into conductors, they are free to move under the influence of a small
insulators and semiconductors, as explained below electric field and acquire small conductivity.
Hence, the resistance of semiconductor is not as high as leaving a vacancy of electron in valence band. This
that of insulators. vacancy is known as hole and carries a positive charge e.
Free electron (This electron goes
Conduction band to conduction band)
Electron energy
EC
Eg < 3 eV
Si Si
EV
Valence band
Fig. 14.6 Energy band gap for semiconductors Hole (Vacancy)

Fig. 14.8 Generation of hole due to thermal agitation
TYPES OF SEMICONDUCTORS
Electron energy
As discussed above, in semiconductors the conduction band EC EC
and the valence band are separated by a relatively small EV
Eg
EV
Eg
energy gap. For silicon, this gap is 1.1 eV and for germanium
it is 0.7 eV. However at 0 K, they behave as an insulator.
On the basis of purity, semiconductors are divided in two T = 0K T > 0K
group Conduction electrons
Holes
1. Intrinsic semiconductors Fig. 14.9 Energy band diagram for an intrinsic

semiconductor at T = 0 K and T > 0 K
A pure (free from impurity) semiconductor which has a
valency 4 is called an intrinsic semiconductor. Pure In intrinsic (or pure) semiconductors, the number of free
germanium and silicon in their natural state are intrinsic electrons per unit volume (n e ) is equal to the number of
semiconductors. holes per unit volume (n h ) and it is also equal to the
number of intrinsic charge carriers per unit volume (n i ).
Si and Ge both have 4 valence electrons. In crystaline
structure, each Si or Ge atom share each of its four Mathematically, we have the relation
valence electrons with four nearest neighbouring atoms ne = nh = ni
and forms covalent bond. Here, (n i ) is also called intrinsic carrier concentration.
At equilibrium, n e n h = n i2
+4 +4 +4 +4 Si or Ge This is known as mass-action law.
Under the action of an electric field, holes move towards
Covalent negative potential giving hole current, I h and electron move
bonds
+4 +4 +4
Bonding
towards positive potential giving electron current I e . The
electrons total current is the sum of the electron current I e and the
hole current I h .
+4 +4 +4 i.e. I = Ie + Ih
Example 14.2 In an intrinsic (pure) semiconductor, the
number of conduction electrons is 7 × 1019 per cubic metre.
Fig. 14.7 Schematic two-dimensional representation of Si or Ge Find the total number of current carriers (electrons and
structure showing covalent bonds at low temperature (all bonds holes) in the same semiconductor of size 1 cm × 1 cm ×
intact). +4 symbol indicates inner cores of Si or Ge. 1mm.
Sol. In an intrinsic semiconductor, n e = n h
At temperature close to zero, all shared electrons are where, n e = number of conduction electrons per unit volume
tightly bound and so no free electrons are available to
and n h = number of holes per unit volume.
conduct electricity through the crystal.
Given, n e = 7 × 1019 per m 3
At room temperature, however a few of the covalent
bonds are broken due to thermal agitation and thus some ∴ n h = n e = 7 × 1019 per m 3
of the valence electrons become free. Thus, we can say So, total current carrier density
that a valence electrons is shifted to conduction band n e + n h = 7 × 1019 + 7 × 1019 = 14 × 1019 per m3
Now, total number of current carrier

= Number density × volume
p-type semiconductors
It is obtained when a trivalent impurity (e.g. boron,
= (14 × 1019 ) × (10−2 × 10−2 × 10−3)
aluminium, gallium or indium) is added to a germanium
= 1.4 × 1013 or silicon crystal.
Example 14.3 Pure Si at 300 K has equal electron (n e ) and The impurity atom has one valence electron less than Si
hole (n h ) concentration of 1.5 × 10 16 m −3 . By some means or Ge, therefore its three valence electrons form covalent
hole concentration increases to 3 × 10 22 m −3 . bonds with neighbouring three Ge (or Si) atoms while the
Now, calculate n e in the Si. fourth valence electron of Ge (or Si) is not able to form
the bond.
Sol. Given, n i = 1.5 × 1016 m−3, n h = 3 × 1022 m−3
So, the bond between the fourth neighbouring Ge (or Si)
For the semiconductor in thermal equilibrium, and the trivalent impurity has a vacancy or hole as
n e n h = n i2 (Law of mass action) shown in Fig. 14.10(a).
n 2 (1.5 × 1016 )2
⇒ ne = i = = 7.5 × 109m−3 This vacancy can be filled by an electron in outer orbit
nh 3 × 1022 in the atom (it may jump to fill the vacancy), leaving a
vacancy or hole at its own site.
Example 14.4 The number of conduction electrons (in per
cubic metre) present in a pure semiconductor is 6.5 × 1019 . With this electron, the trivalent impurity atom becomes
Calculate the number of holes in a sample having dimensions negatively charged.
1 cm × 1 cm × 2 mm . So, the dopant atom of p-type semiconductor can be
Sol. Here, number of conduction electrons, n e = 6.5 × 1019 m−3 considered as core of the negative charge along with its
associated hole.
Volume of the sample,V = 1 cm × 1 cm × 2 mm = 2 × 10−7 m3
Number of holes in the sample (n h ) = Number of electrons in
the sample (n e )
= n e ×V +4 +4 +4
= 6.5 × 1019 × 2 × 10−7 Acceptor core
13
= 1.3 × 10
2. Extrinsic semiconductors +4 +3
Ho
+4
El le –
The conductivity of an intrinsic semiconductor is very ec
tro
poor (unless the temperature is very high). At ordinary n
temperature, only one covalent bond breaks in 10 9 atoms +4 +4 +4
of Ge. It means that, only 1 atom in 10 9 atoms is available
Hole
for conduction. Conductivity of an intrinsic (pure)
semiconductor is significantly increased, if some
pentavalent or trivalent impurity is mixed with it. Such (a) (b)
impure semiconductors are called extrinsic or doped Fig. 14.10 (a) Trivalent acceptor atom (In, Al, B, etc.) doped in
semiconductors. tetravalent Si or Ge lattice giving p-type semiconductor.
(b) Commonly used schematic representation of p-type material
Note When some desirable impurity is added to intrinsic which shows only the fixed core of the substituent acceptor with one
semiconductor deliberately, then this process is called doping effective additional negative charge and its associated hole.
and the impurity atoms are called dopants.
There are two types of dopants used in doping in the The trivalent impurity atoms are called acceptor atoms
tetravalent Si or Ge because they create holes which accept electrons.
(i) Trivalent (valency 3) atoms: e.g. Indium (In), Boron Following points are worthnoting regarding to p-type
(B ), Aluminium (Al), etc. semiconductors
(ii) Pentavalent (valency 5) atoms: e.g. Arsenic (As), (a) Holes are the majority charge carriers and electrons
Antimony (Sb), phosphorus (P), etc. are minority charge carriers in case of p-type
Depending upon the nature of impurity added in intrinsic semiconductors or number of holes are much greater
semiconductor, the extrinsic semiconductors are of two types than the number of electrons. i.e. n h >> n e ; ih > ie .
(i) p-type semiconductor (ii) n-type semiconductor (b) p-type semiconductor is electrically neutral.
(c) Conductivity, σ = n h µ h e (c) Conductivity, σ = n e µ e e

(d) p-type semiconductor can be shown as (d) n-type semiconductor can be shown as
Hole Electron
– – Hole Electron
+ + Hole
or
or + Electron
– + +
– –
Donor ion
Acceptor ion Fig. 14.13 Representation of n-type semiconductor
Fig. 14.11 Representation of p-type semiconductor
Energy band in extrinsic semiconductors
n-type semiconductors Energy band structure of semiconductor is affected due to
It is obtained, when a pentavalent impurity atom (e.g. doping. In extrinsic semiconductors, additional energy
antimony, phosphorus or arsenic) is added to a Ge (or Si) states due to donor impurities (donor energy level E D ) and
crystal. Here, the impurity atom has one valence electron acceptor impurities (acceptor energy level E A ) also exist.
more than Si or Ge, therefore four of the five valence In the energy band diagram of n-type semiconductor, the
electrons of the impurity atom form covalent bonds with donor energy level E D is slightly below the bottom E C of
four neighbouring Ge (or Si) atoms and the fifth valence conduction band and the electrons from this level move
electron becomes free to move inside the crystal lattice. into conduction band with very small supply of energy. So
Thus, by doping pentavalent impurity, number of free the conduction band have most of the electrons coming
electrons increases. from donor impurities.
Unbonded free In p-type semiconductors, the acceptor energy level E A is
electron donated slightly above the top energy level EV of the valence band.
by pentavalent With very small supply of energy, an electron from the
(+5 valency) atom
+4 +4 +4 valence band can jump to the energy level E A and ionise
the acceptor negatively. At room temperature, most of the
Donor core
acceptor atoms get ionised leaving hole in valence band.
Thus, at room temperature, the density of holes in valence
+4 +5 +4
band is mainly due to impurity.
+
+4 +4 +4 EC
Electron energy
{ ED
≈ 0.01 eV Eg
Electron
EV
(a) (b)
Fig. 14.12 (a) Pentavalent donor atom (As, Sb, P, etc.) doped in
tetravalent Si or Ge giving n-type semiconductor and (b) Commonly
used schematic representation of n-type material which shows only
the fixed cores of the substituent donors with one additional effective (a) T > 0 K
positive charge and its associated extra electron.
The impurity (pentavalent) atoms are called donor atoms

EC
because they donate conduction electrons to the crystal.
The number of electrons made available for conduction (by Eg EA
dopant atoms) depend strongly upon the dopant level and }
EV ≈ 0.01 to 0.05 eV
is independent of increase in temperature.
Following points are noteworthy regarding n-type
semiconductors
(a) Electrons are the majority charge carriers and holes
are minority charge carriers or number of electrons (b) T > 0 K
are much greater than the number of holes. i.e. Fig. 14.14 Energy bands of (a) n-type semiconductor at T > 0 K
n e >> n h ; ie >> ih and (b) p-type semiconductor at T > 0 K
(b) n-type semiconductor is also electrically neutral.
more and more charge carriers (electron-hole pairs). This

Electrical conduction through results in increasing conductivity.
semiconductors The temperature dependence of charge carrier density is
When a battery is connected across a semiconductor given by
(whether intrinsic or extrinsic), a potential difference is −E g / 2kT
ni ∝ e
developed across its ends. Due to the potential difference,
an electric field is produced inside the semiconductors. A where, n i is number of electron-hole pair, E g is the energy
current (although very small) starts flowing through the gap of the semiconductor and k is Boltzmann’s constant.
semiconductor. This current may be due to the motion of Thus, the charge carrier density and hence the
(i) free electrons (ie ) and (ii) holes (ih ). Electrons move in conductivity of the semiconductor increases exponentially
opposite direction of electric field, while holes move in the with rise in temperature.
same direction. Example 14.5 A p-type semiconductor has acceptor level
The motion of holes towards right (in the figure) take place 50 meV above the valence band. Find the maximum
because electrons from right hand side come to fill this wavelength of light that can create a hole.
hole creating a new hole in their own position. Thus, we Sol. To create a hole, an electron of valence band has to be
can say that holes are moving from left to right. So, excited into one of the acceptor levels, which are 50 meV
current in a semiconductor can be written as above the valence band. Hence, a minimum of 50 meV
i = ie + ih energy is needed to create a hole.
hc
E
As, E min =
λ max
Si Si Al hc 6.6 × 10−34 × 3 × 108
∴ λ max = =
E min 50 × 1.6 × 10−22
= 2.47 × 10−5 m
i + − i
Example 14.6 A Ge specimen is doped with Al. The
concentration of acceptor atoms is ~ 10 21 atoms/m 3 . Given
that, the intrinsic concentration of electron-hole pairs is
~ 1019 /m 3, then find the concentration of electrons in the
specimen.
i + − i Sol. According to law of mass action, n i2 = n hn e
Fig. 14.15 Conduction through semiconductors Here, n i = intrinsic concentration of electron hole pair = 1019 /m3
But it should be noted that, mobility of holes is less than and n h = concentration of acceptor atoms = 1021 atoms/m 3.
the mobility of electrons. n i2 (1019 )2
∴ ne = = = 1017 /m3
Conductivity of semiconductors is given by nh (1021)
σ = ne e µ e + nh e µ h Example 14.7 A semiconductor has equal electron-hole
where, n e and n h are densities of conducting electrons and concentration of 6 × 10 8 m −3 . On doping with certain
holes, respectively and µ e and µ h are their respective impurity, electron concentration increases to 9 × 1012 m −3 .
mobilities. (i) Identify the new semiconductor obtained after doping.
(ii) Calculate the new hole concentration.
v v
where, µ e = e , µ h = h , here v e and v h are drift (iii) How does the energy gap vary with doping?
E E
velocities. Sol. (i) As, the electron concentration increases after doping, so
the new semiconductor obtained is of n-type.
(ii) As, n e n h = n i2 (Law of mass action)
Effect of temperature on
Here, n i = 6 × 108 m−3, n e = 9 × 1012 m−3
conductivity of semiconductor n i2 (6 × 108 )2
The conductivity of a semiconductor increases (or the ∴ nh = = = 4 × 104 m−3
ne 9 × 1012
resistivity decreases) with rise in temperature. This is
because, as the temperature rises, more and more of the (iii) The energy gap decreases with doping.
covalent bonds in the crystal lattice break, thus creating
Example 14.8 Suppose a pure Si crystal has 5 × 10 28 atoms Sol. In pure semiconductor, electron-hole pair
−3
m . It is doped by 1 ppm concentration of pentavalent As. concentration, n h = n e = 7 × 1015 m−3
Calculate the number of electrons and holes. Total charge carrier,
(Given that, n i = 1.5 × 1016 m −3 )
n total initial = n h + n e = 7 × 1015 + 7 × 1015
16 −3
Sol. Here, n i = 1.5 × 10 m
= 14 × 1015
Doping concentration of pentavalent As atoms
After doping, donor impurity,
= 1 ppm = 1 part per million
∴ Number density of pentavalent as atoms, 5 × 1028
ND = = 5 × 1021
5 × 10 28 107
ND = = 5 × 1022 atom m−3
106 and n e′ =
ND
= 2.5 × 1021
Now, the thermally generated electrons (n i ∝ 10 m ) are 16 −3 2
negligibly small as compared to those produced by doping, so So, n final = n h + n e′
n e −~ N D = 5 × 1022 m−3 ⇒ n final ≈ n e′ ≈ 2.5 × 1021 (Q n e′ >> n h )
Also, ne nh = n i2 (Law of mass action) n final − n initial
Factor =
n i2 1.5 × 1016 × 1.5 × 1016 n initial
∴ nh = = = 4.5 × 109 m−3
ne 5 × 1022
2.5 × 1021 − 14 × 1015
=
Example 14.9 What will be the conductivity of pure silicon 14 × 1015
3
crystal at 300K temperature? If electron hole pairs per cm
2.5 × 1021
is 1.072 × 1010 at this temperature and mobilities are ≈ = 1.8 × 105
µ h = 1350 cm 2 /V-s and µ e = 480 cm 2 /V-s. 14 × 1015
Sol. Conductivity of pure silicon,
Example 14.12 The number of silicon atoms per m 3 is
σ = n i eµ e + n i e µ h = n i e (µ e + µ h ) 5 × 10 28 . This is doped simultaneously with 5 × 10 22 atoms
where, n i is the total number of charge carrier, µ e and µ h are per m 3 of arsenic and 5 × 10 20 per m 3 atoms of indium.
the mobility of electrons and holes, respectively. Calculate the number of electrons and holes. Given that,
Here, n i = 1.072 × 1010 per cm3 n i = 1.5 × 1016 /m 3 . Is the material n-type or p-type?
µ h = 1350 cm2 /V- s Sol. We know that for each atom doped of arsenic, one free
electron is received. Similarly, for each atom doped of indium,
µ c = 480 cm2 /V-s a vacancy is created.
⇒ σ = (1.072 × 1010 )(1.6 × 10−19 )(1350 + 480) So, the number of free electrons introduced by pentavalent
impurity added, n e = N As = 5 × 1022 m−3 …(i)
. × 10−6 mho/cm
= 314
The number of holes introduced by trivalent impurity added,
Example 14.10 An intrinsic germanium semiconductor is n h = N In = 5 × 1020 m −3
to be made n-type semiconductor of conductivity 6 mho/cm.
Calculate the number density of donor atoms required, if Now, n e − n h = 5 × 1022 − 5 × 1020
the mobility of electrons in n-type semiconductor is = 4.95 × 1022 …(ii)
3850 cm 2 /V-s.
So, (n e + n h )2 = (n e − n h )2 + 4n e n h
Sol. In n-type semiconductor, n e >> n h
Let number density of donor atoms, N 0 = n e n e + n h = (4.95 × 1022 )2 + 4(1.5 × 1016 )2 …(iii)
Conductivity of semiconductor is given by σ = n ee µ e (Qn e n h = n i2 )
On putting the values, we get
Adding Eqs. (iii) and (ii), we get
6 × 102 = n e × 1.6 × 10–19 × 3850 × 10−4
2n e = 4.95 × 1022 + (4.95 × 1022 )2 + 4(1.5 × 1016 )2
⇒ n e = 9.7 × 1021 /m3
1
Example 14.11 The concentration of hole-electron pairs in ne = [4.95 × 1022 + (4.95 × 1022 )2 ]
2
pure germanium at T = 300 K is 7 × 1015 per cubic metre.
Antimony is doped into germanium in a proportion of 1 atom = 4.95 × 1022 /m3
per 10 7 Ge atoms. Assuming that, half of the impurity atoms Now, n i2 = n h × n e
contribute electron in the conduction band, calculate the
factor by which the number of charge carriers increases due n i2 (1.5 × 1016 )2
or nh = =
to doping . The number of germanium atoms per cubic metre ne 4.95 × 1022
is 5 × 10 28 .
= 4.54 × 109 / m3 Sol. Conductivity of semiconductor is given by

22
As, number of electrons n e (= 4.95 × 10 ) is greater than σ = n ee µ e + n he µ h
number of holes n h (= 4.5 × 109 ). Since semiconductor is intrinsic, so n e = n h = n i
Conductivity, σ = n i e (µ e + µ h )
So, the material is n-type semiconductor.
= 1.6 × 106 × 1.6 × 10−19 (0.4 + 0.2)
Example 14.13 Find the resistivity of a sample in which
= 1.536 × 10−13 Ω −1m−1
1019 atoms of phosphorous are added per m 3 . Take the
resistivity of pure silicon as 3000 Ω-m and the mobilities of Current flowing, I = JA
electrons and holes as 0.15 m 2 /V-s and 0.030 m 2 /V-s, V 
where, J = current density = σE = σ  
respectively. d
Sol. The conductivity of a pure silicon is given by V 
∴ I = JA = σ   ⋅ A
σi = n i e (µ e + µ h ) d
Also, the resistivity is reciprocal of conductivity.
 5 
1 1 = 1.536 × 10−13  −4
 (3.5 × 10 )
∴ ρi = = 1.5 × 10−3 
σi n i e (µ e + µ h )
1 = 1.79 × 10−13 A
⇒ ni =
ρi e (µ e + µ h ) Heat produced, H = VIt = 5 × 1.79 × 10−13 × 120
1 = 10.74 × 10−11 J
= −19
3000 × 1.6 × 10 (0.15 + 0.030)
Example 14.15 The energy gap of pure Si is 1.12 eV. The
= 1.157 × 1016 /m3 mobilities of electrons and holes are respectively
19
When10 atoms of phosphorus (donor atoms) are added per m , 3 0.140 m 2V −1s −1 and 0.050 m 2V −1s −1. They are
we have independent of temperature. The intrinsic carrier
n e >> n i
concentration is given by
−E / 2kT
or n e >> n h ni = n 0 e g
⇒ n e = 1019 where, n 0 is a constant, E g is the gap width and k is the
1 Boltzmann’s constant whose value is 1.38 × 10 −23 JK −1.
∴ ρ= Find the ratio of the electrical conductivities of Si at 400 K
ne e µe
and 200 K.
1
= 19 Sol. Conductivity of semiconductor is given by
10 × 1.6 × 10−19 × 0.15
σ = n ee µ e + n he µ h
= 4.17 Ω-m
Here, n e = n h = n i (pure semiconductor)
Example 14.14 A pure germanium plate of area σ = n i e (µ e + µ h ) = e (µ e + µ h ) n i
3.5 × 10 −4 m 2 and of thickness 1.5 × 10 −3 m is connected −E g / 2 kT
across a battery of potential 5 V. Find the amount of current = e (µ e + µ h ) n 0e
produced at room temperature in the germanium sample. Also, −E g
find the amount of heat generated in the plate in 120 s. Given σ 400 e 2 k × 400
E / 800 k
that, the concentration of carriers in germanium at room ∴ = −E =e g
σ 200 g
temperature is 1.6 × 10 6 per cubic metre. The mobilities of
e 2k × 200
electrons and holes are 0.4 m 2V −1s −1 and 0.2 m 2 V −1s −1,
−19
/ 800 × 1.38 × 10 − 23
respectively. = e 1.12 × 1.6 × 10 = e16.23
CHECK POINT 14.1

1. The expected energy of the electrons at absolute zero is 8. A p-type semiconductor can be obtained by adding
called (a) arsenic to pure silicon
(a) fermi energy (b) gallium to pure silicon
(b) emission energy (c) antimony to pure germanium
(c) work function (d) phosphorous to pure germanium
(d) potential energy
9. To obtain p-type semiconductor, we need to dope pure
2. The conduction band in a solid is partially filled at 0 K. The Si with
solid sample is a (a) aluminium (b) phosphorous
(a) conductor (b) semiconductor (c) oxygen (d) germanium
(c) insulator (d) None of these
10. In p-type semiconductor, the majority and minority charge
3. The valence band and conduction band of a solid overlap at carriers are respectively.
low temperature, the solid may be
(a) Protons and electrons (b) Electrons and protons
(a) a metal (b) a semiconductor
(c) Electrons and holes (d) Holes and electrons
(c) an insulator (d) None of these
11. The charge on a hole is equal to the charge of
4. In an insulator, forbidden energy gap between the valence (a) zero (b) proton (c) neutron (d) electron
band and conduction band is of the order of
(a) 1 MeV (b) 0-1 MeV (c) 1 eV (d) 5 eV 12. If ne and nh represent the number of free electrons density
and holes density respectively in a semiconducting material,
5. The forbidden energy band gap in conductors, then for n-type semiconducting material
semiconductors and insulators are E g1 , E g2 and E g3 (a) ne << nh (b) ne >> nh (c) ne = nh (d) ne = nh = 0
respectively. The relations among them is
(a) E g1 = E g 2 = E g 3 13. Which statement is correct?
(b) E g1 < E g 2 < E g 3 (a) n-type germanium is negatively charged and p-type
(c) E g1 > E g 2 > E g 3 germanium is positively charged.
(d) E g1 < E g 2 > E g 3 (b) Both n-type and p-type germanium are neutral.
(c) n-type germanium is positively charged and p-type
6. Doping of intrinsic semiconductor is done germanium is negatively charged.
(a) to neutralise charge carries (d) Both n-type and p-type germanium are negatively charged.
(b) to increase the concentration of majority charge carriers
(c) to make it neutral before disposal
14. When a semiconductor is heated, its resistance
(a) decreases (b) increases
(d) to carry out further purification
(c) remains unchanged (d) Nothing is definite
7. The majority charge carriers in p-type semiconductor are
15. Which of the following has negative temperature coefficient
(a) electrons (b) protons of resistance?
(c) holes (d) neutrons (a) Copper (b) Aluminium (c) Iron (d) Germanium
p-n JUNCTION
A p-type or n-type silicon crystal can be made by adding Formation of depletion region in
appropriate impurity as discussed above. Separately p- and p-n junction
n-type semiconductors have limited use. When the two
types are combined, a number of new characteristic appears, In an n-type semiconductor, the concentration of electrons
which make the combination a very useful device. So, is more than the concentration of holes. Similarly, in a
when a p-type semiconductor is suitably joined to an p-type semiconductor, the concentration of holes is more
n-type semiconductor, then resulting arrangement is called than the concentration of electrons.
p-n junction. During formation of p-n junction and due to the
A p-n junction is formed either when a p-type concentration gradient across p and n-sides, holes diffuse
semiconductor is grown on n-type semiconductor or n-type from p-side to n-side (p → n ) and electrons diffuse from
is grown on p-type semiconductor as given below n-side to p-side (n → p ).
Junction The diffused charge carriers combine with their counterparts
p-region n-region in the immediate vicinity of the junction and neutralise each
other.
Fig. 14.16 A p-n junction
Thus, near the junction positive charge is built on n-side V 0.5

Electric field, EB = = = 106 Vm −1
and negative charge on p-side as shown in the figure d 5 × 10−7
Electron diffusion
Electron drift E =V
d
p n p n
Depletion region (ii) According to work-energy theorem,

Hole diffusion
Hole drift 1 1
m evi2 = eV + m ev f2
Fig. 14.17 p-n junction formation process 2 2
This set up a potential difference across the junction and m evi2 − 2 eV

Speed, v f =
an internal electric field E i directed from n-side to p-side. me
The equilibrium is established when the field E i becomes 9 × 10−31 × (5 × 105 )2 − 2 × 1.6 × 10−19 × (0.5)
strong enough to stop further diffusion of the majority =
charge carriers (however it helps the minority charge 9 × 10−31
carriers to diffuse across the junction). = 2.7 × 105 ms −1
The region on either side of the junction which becomes
depleted (free) from the mobile charge carriers is called Current flow across a p-n junction
depletion region or depletion layer. The width of
There are two types of current flow across a p -n junction,
depletion region is of the order of 10 −6 m or 1 µm. which are discussed below
The potential difference developed across the depletion
region is called the potential barrier. Potential barrier 1. Diffusion current
depends on dopant concentration in the semiconductor and Because of concentration difference, holes try to diffuse
temperature of the junction. from the p-side to the n-side and electrons from n-side to
On the average, the potential barrier in p-n junction is p-side at the p-n junction. However, only those holes/
V electrons cross the junction which have high kinetic
~ 0.5 V and is given by E B = B ⇒ VB = E B d energy. The diffusion give rise to a current from p-side to
d
n-side called diffusion current.
where, E B = barrier electric field
and d = width of depletion region. 2. Drift current
For Ge,VB = 0.3 V and for siliconVB = 0.7 V. Because of thermal collisions, electron-hole pairs are
Given below are the graphs of potential versus distance, created at every part of a p-n junction. However, if an
charge density versus distance and electric field versus electron-hole pair is created in the depletion region, the
distance across the depletion region. electron is pushed by the electric field towards the n-side
and the hole towards the p-side.
Potential Charge density
Electric field
This gives rise to a current from n-side to p-side called the
p n drift current.
p n p n
+
– Thus, we have, diffusion current,
Distance Distance Distance
(a) (b) (c)
I df → from p-side to n-side
Fig. 14.18 (a) Potential versus distance, (b) charge density and drift current, I dr → from n-side to p-side
versus distance, (c) Electric field versus distance across the In steady state, I df = I dr or I net = 0
depletion region
Example 14.16 A potential barrier of 0.5 V exists across a Semiconductor diode or p-n
p-n junction (i) If the depletion region is 5 × 10 −7 m wide, junction diode
what is the intensity of the electric field in the region (ii) An
electron with speed 5 × 10 5 ms −1 approaches the p-n junction A semiconductor diode [Fig. (a)] is basically a p-n junction
from the n-side, with what speed will it enter the p-side? with metallic contacts provided at the ends for the
Sol. (i) Width of depletion layer, d = 5 × 10−7 m
application of an external voltage. It is a two terminal
device. A p-n junction diode is represented by the symbol Thus, a current called forward current, is constituted by
as shown in Fig. (b). the motion of majority charge carriers across the junction.
In forward bias, the junction diode offers low resistance
p
ssrr n (ideally zero). Also, I df > I dr or I net is from p-side to n-side.
p ssrr
ssrr n
ssrr Anode Cathode
ssrr
Metallic contact Metallic contact 2. Reverse biasing
(a) (b) A junction diode is said to be reverse biased when the
Fig. 14.19 (a) Semiconductor diode positive terminal of the external battery is connected to
(b) Symbol for p-n junction diode the n-side and negative terminal to the p-side of the diode.
The direction of arrow indicates the conventional direction Flow of current in reverse biasing
of current.
In this situation, the reverse voltage supports the potential
barrier, due to which the potential barrier increases and
Biasing of junction diode hence width of depletion layer increases.
Biasing is the method of connecting external battery or Under the effect of external electric field, holes in the
emf source to a p-n junction diode. The junction diode can p-region and electrons in the n-region are pushed away from
be connected to an external battery in two ways, called the junction, i.e. they cannot be combined at the junction.
forward biasing and reverse biasing of the junction.
So, there is almost no flow of current due to majority
charge carriers.
1. Forward biasing
Junction
A junction is said to be forward biased when the positive
terminal of the external battery is connected to the p-side Hole p-region n-region Electron
and negative terminal to the n-side of the diode.
– Ei +
Flow of current in forward biasing
In this situation, the forward voltage opposes the potential
barrier, due to which the potential barrier decreases and E Inet
hence width of depletion layer decreases. Inet EB
Under the effect of external electric field, holes in the – +
p-region and electrons in n-region, both move towards the
V
junction. Battery (Reverse biased)
Hole Junction Fig. 14.21 Reverse biased p-n junction diode
p-region n-region Electron
However, a very small current due to minority charge
+ Ei – carriers, flows across the junction. This current is called
Inet
reverse saturation current. Here, I dr > I df or I net is from
n-side to p-side.
E Inet
Note The p-n junction allows a much larger current flow in forward
biasing than in reverse biasing. This is crudely, the basis of the
+ – action of a p-n junction as a rectifier.
V
Battery (Forward biased) Example 14.17 Find the net resistance of the network shown in
Fig. 14.20 Forward biased p-n junction diode
the figure between the points P and Q, if (i)VP > VQ , (ii)VP < VQ .
12 Ω
These holes and electrons mutually combine just near the
junction and cease to exist. For each electron-hole
combination, a covalent bond breaks up in the p-region P Q
near the positive terminal of the battery.
4Ω
Of the hole and electron so produced, the hole moves
towards the junction, while the electron enters the positive Sol. (i) WhenVP > VQ , the diode is in forward biased. Let, the
terminal of the battery through the connecting wire. resistance of diode will be taken as zero. Hence, 4 Ω
resistance is ineffective. So, the net resistance is
Just at this moment, an electron is released from the negative
4 × 12
terminal of the battery which enters the n-region to replace = 3Ω.
4 + 12
the electron lost by combining with a hole at the junction.
(ii) WhenVP < VQ , the diode is reverse biased. Let, there Diode is in reverse biased condition, so it will not conduct.
will be no current in the diode branch, hence 4 Ω Hence, ammeter A1 will not show any reading. Now, the value
resistance is ineffective. So, the net resistance is12 Ω. of I 2 will be
Example 14.18 The diode used in the circuit shown in the V 5
I2 = = = 0.25 A
figure has a constant voltage drop of 0.5 V at all current R 20
and a maximum power rating of 200 mW. What should be
Example 14.21 Find the net resistance between two points P
the value of the resistor R, connected in series with the
and Q, if the value of each resistance shown in the figure is
diode, for obtaining maximum current?
10 Ω.
R
I
P Q
2V
Power
Sol. Current through diode (or circuit), I = Sol. The given circuit is in the form of a Wheatstone bridge,
Voltage
RS
200 × 10−3W
∴ I= = 0.4 A
0.5 V 10 Ω 10 Ω
A B
Net voltage 2 − 0.5 P Q
and resistance, R = = = 3.75 Ω C D
Current 0.4 10 Ω 10 Ω
Example 14.19 Find current passing through 4 Ω and 8 Ω R ′S

resistance in the circuit shown in figure.
D1 4Ω A C
i.e. =
B D
D2 8Ω Hence no current will from through diode, i.e. it will not offer
any resistance. Hence, net resistance will be
R × R S′
RN = S
R S + R S′
12 V where R S and R S′ = (10 + 10) = 20 Ω
Sol. In the given circuit, diode D1 is in forward biased and D 2 is ⇒ R N = 10 Ω
in reverse biased. Hence, D1 will conduct but D 2 will not. Example 14.22 (i) Calculate the value ofV 0 and i, if the
Therefore, current through 8 Ω resistance will be zero while silicon and germanium diode start conducting at 0.7 V and
12 0.3 V, respectively.
through 4 Ω resistance will be = 3 A.
4 Ge
Example 14.20 Consider the circuit diagram shown alongside. i
Two ammeters A1 and A2 are connected across a diode and V0
Si
resistor, respectively. Find the amount of current flowing RL 5 kΩ
12 V
through these two ammeters. Neglect, the resistances of the
ammeters.
20 Ω
A2
(ii) If the Ge diode connection is now reversed, what will be the
new values ofV0 and i?
5V
20 Ω Sol. (i) Ge diode will start conducting before the silicon diode
A1
s
does so. The effective forward voltage across Ge diode is
(12 − 0.3) V =11.7 V. This will appear as the output
Sol. Let the current I1 flows across diode and I 2 flows across A2 voltage across the load, i.e.
as shown below Vo = 11.7 V
I2 20 Ω The current through RL ,
A2
11.7
5V i= A
5 × 103
I1 20 Ω = 2.34 mA
A1
(ii) On reversing the connection of Ge diode, it will be

reverse biased and conduct no current. Only Si diode
2. Reverse biased characteristics
will conduct. Therefore, The circuit diagram for studying reverse biased
Vo = (12 − 0.7) V = 11.3 V characteristics is shown in the figure
11.3
and current, i = A = 2.26 mA p n Reverse voltage (V)
5 × 103 –10 –8 –6 –4 –2 0
– +
Voltage-current characteristic
Reverse current (µA)

+ V C 2
mA Breakdown
– voltage
curve of a p-n junction diode 4
The voltage-current characteristic curves of a p-n junction 6

diode are graphs showing the change in current flowing
Battery 8
through the junction with change in a applied voltage, – + D
when the junction is in forward biased and in reverse
biased. (a) (b)
Fig. 14.23 Reverse biased characteristics of a diode
1. Forward biased characteristics In reverse biased, the applied voltage supports the flow of
When the diode is in forward biased, i.e. p-side is kept at minority charge carriers across the junction. So, a very
higher potential, the current in the diode changes with the small current flows across the junction due to minority
voltage applied across the diode. charge carriers.
A graph is plotted between voltage and current. The curve Motion of minority charge carriers is also supported by
so obtained is the forward characteristic of the diode. At internal potential barrier, so all the minority carriers cross
the start when applied voltage is low, the current through over the junction.
diode is almost zero. It is because of potential barrier,
Therefore, the small reverse current remains almost
which opposes the applied voltage.
constant over a sufficiently long range of reverse bias
Till the applied voltage exceeds the potential barrier, the voltage, increasing very little with increasing voltage (OC
current increases very slowly with increase in applied portion of the graph).
voltage (OA portion of the graph).
This reverse current is voltage independent upto certain
p n voltage known as breakdown voltage and this voltage
7
B
independent current is called reverse saturation current.
Forward current (mA)
– – 6 This reverse saturation current depends only on

+
mA V 5
+
temperature of the junction. If is found that for every 1°
4 Ge rise in temperature, the reverse saturation current
3 increases by about 7%. So for every 10°C rise, the I 0
2 becomes nearly double.
1 A If the reverse biased voltage is too high, then p-n junction
+ –
O
0.1 0.2 0.3 0.4 0.5
breaks.
Battery Forward voltage (V) It is of following two types
Fig. 14.22 Forward biased characteristics of a diode (a) Zener breakdown
When reverse bias voltage is increased, the electric field
After this voltage, the diode current increases rapidly (AB
across the junction also increases. At some stage, the
portion of the graph), even for very small increase in the
electric field becomes so high, that it breaks the covalent
diode voltage. In this situation, the diode behaves like a
bonds creating electron-hole pairs. Thus, a large number of
conductor. The forward voltage beyond which the current
carriers are generated. So, this causes a large current to
through the junction starts increasing rapidly with voltage
flow. This mechanism is known as Zener breakdown.
is called the threshold voltage or cut-off voltage or knee
voltage. (b) Avalanche breakdown
If line AB is extended back, it cuts the voltage axis at At high reverse voltage, due to high electric field, the
potential barrier voltage. minority charge carriers, while crossing the junction
The value of the cut in voltage is about 0.3 V for a acquire very high velocities. These by collision breaks
germanium diode and 0.7 V for a silicon diode. down the covalent bonds generating more carriers. A
chain reaction is established giving rise to high current. (ii) If diode is assumed ideal, then what will be
This mechanism is called Avalanche breakdown. (a) output voltage
(b) and output current in diode?
Note Zener breakdown occurs in a highly doped p-n junction
whereas Avalanche breakdown occurs in a lightly doped p-n Sol. (i) (a) As,Vout = Vin − VB
junction. where,VB = barrier voltage
∴ Vout = 10 − 0.7 = 9.3 V
Dynamic resistance (b) As diode is in forward biased state, so it will conduct
The complete V-I characteristic of a junction diode is V 9.3
∴ I = out = = 0.9 mA
shown in figure. It is clear from the graph that, both the RL 10 × 103
forward-reverse bias characteristics of the p-n junction do (c) Forward resistance,
not obey Ohm’s law. So, the resistance offered by junction V 0.7
diode will depend on the applied voltage. rf = B =
I 0.9 × 10− 3
I = 777 Ω
(ii) For ideal diode, rf = 0,VB = 0
Breakdown voltage (a)Vout = Vin = 10 V
Knee voltage
V 10
V (b) I = out = = 1 mA
(Forward bias) RL 10 × 103
(Reverse
bias)
p-n Junction diode as a rectifier
Fig. 14.24 Complete V -I characteristic A rectifier is a device which converts an alternating
of a junction diode current (or voltage) into a direct (or unidirectional) current
(or voltage).
Here, we will take the dynamic resistance which is Principle A p-n junction diode can work as an excellent
defined as the ratio of small change in voltage to the small rectifier because it permits current in one direction only.
change in current produced. It is also called dynamic It offers a low resistance for the current to flow when it is
resistance of the junction diode and is denoted by r d . forward biased, but a very high resistance when reverse biased.
∆V Thus, it allows current to flow through it in only one direction
Thus, rd = and acts as a rectifier.
∆I
The junction diode can be used either as a half-wave
The region of the characteristic curve, where dynamic rectifier or as a full-wave rectifier.
resistance is almost independent of the applied voltage is
called the linear region of junction diode. 1. p-n junction diode as half-wave
Example 14.23 A silicon diode is connected to a load rectifier
resistance R L as shown in the figure. LetVin = 10 V and A simple rectifier circuit called the half-wave rectifier,
R L = 10 k Ω. using only one diode is shown in figure. The AC voltage to
(i) If barrier voltage,VB = 0.7 V, then calculate be rectified is connected to the primary coil of a step-down
(a) output voltage across RL , transformer. Secondary coil is connected to the diode
(b) current in diode through resistor R L across which, output is obtained.
(c) and forward resistance.
Transformer
VB A X
AC
Primary Secondary R L Output
input
+
B Y
Vin RL Vout
– Fig. 14.25 Circuit diagram of a half-wave rectifier
Working (v) Efficiency It is given by

During positive half cycle of the input AC (i.e.VA > 0), the P 40.6%
η = out × 100% =
p-n junction is in forward biased. Thus, the resistance in Pin 1 + r f /R L
p-n junction becomes low and current flows. Hence, we
get output in the load. If R L > > r f , then η = 40.6% and if R L = r f , then
η = 20.3%.
(vi) The ratio of irms and i DC is known as form factor.
Voltage at A
Input AC
I π
Form factor = rms = = 1.57
+ + 3π 4π I DC 2
ωt
0 π 2π
– – (vii) The ripple frequency (ω ) for half wave rectifier is
Voltage across RL
same as that of AC.

Output AC
Example 14.24 The applied input AC to a half wave rectifier
+ + is 60 W and the DC output is 20 W. Find the rectification
ωt efficiency. Also, calculate the value of power efficiency.
0 π 2π 3π 4π
Fig. 14.26 Input and output waveform Sol. Rectification efficiency is the ratio of DC output power to
the AC input power, i.e.
During negative half cycle of the input AC (i.e.VA < 0), the DC output power
η= × 100
p-n junction is in reverse biased. Thus, the resistance of p-n AC input power
junction is high and current does not flow. Hence, no output Here, DC output power = 20 W
is obtained across the load. AC input power = 60 W
20
Important points related to half-wave rectifier ∴ Rectification efficiency, η = × 100 = 33.3%
60
(i) Average output in one cycle
Also, power efficiency is given by
I V V0 DC output power
I DC = 0 and VDC = 0 ; I 0 = , PE = × 100 %
π π rf + RL AC input power for half cycle
V0 20
VDC = = × 100 % = 66.67%
 rf  30
π 1 + 
 RL  Example 14.25 A semiconductor diode is used as a half-wave
rectifier having internal resistance 200 Ω. The voltage
 r f = forward biased resistance  applied is given byV = 50 sin ωt volt and load resistance is
  650 Ω. Calculate (i) maximum output current, (ii) DC
 and R L = load resistance 
output current, (iii) DC output power (iv) and DC output
I0 V voltage.
(ii) rms output I rms = , Vrms = 0
2 2 Sol. Here, V = (50 sin ωt ) volt
(iii) The ratio of the effective alternating component of Comparing it with general equationV = V0 sin ωt, we get
the output voltage (or current) to the DC component V0 = 50 volt, RL = 650 Ω, rf = 200 Ω
is known as ripple factor. (i) Maximum output current, I 0 =
V0
1/ 2 rf + RL
I  I  2 
r = AC =   rms  − 1 = 1.21 =
50
= 58 mA
I DC   I DC   (200 + 650)

I 58
The smaller the ripple factor, more effective will be (ii) DC output current, I DC = 0 = = 18.5 mA
π π
rectifier.
(iii) DC output power,
(iv) Peak inverse voltage (PIV) The maximum reverse 2
= I DC ⋅ RL = (18.5 × 10−3 )2 ⋅ 650 = 0.22 W
biased voltage that can be applied before
commencement of breakdown region is called the (iv) DC output voltage,
peak inverse voltage. When diode is not conducting, = I DC ⋅ RL = 18.5 × 10−3 × 650 = 12.02 W
PIV across it =V0 .
A
2. p-n junction diode as full wave rectifier D2
Secondary
D1
Primary
The full wave rectifiers are of two types Input X
D4
(i) Centre tap full wave rectifier D3
B RL Output
(ii) Full wave bridge rectifier
These are described in detail below (a) Y
D2 and D4 conducting
(i) Centre tap full wave rectifier D1 and D3 conducting
Output
Figure shows a circuit which is used in full wave waveform
rectification. Two diodes are used for this purpose.
O ωt
0 π 2π 3π
Centre tap (b)
transformer Fig. 14.29 (a) Bridge rectifier (b) and output
Diode 1(D1)
A
waveforms for a bridge rectifier
Centre
tap For one-half cycle, diodes D 1 and D 3 are forward biased and
X D 2 and D 4 are reverse biased. So, D 1 and D 3 conduct but
B
D 2 and D 4 don’t. Current through R L flows from X to Y.
Diode 2(D2) RL Output
In another half cycle, D 2 and D 4 are forward biased and
Y D 1 and D 3 are reverse biased. So, in this half cycle, D 2 and
D 4 conduct but D 1 and D 3 do not. Current again flows
Fig. 14.27 Circuit diagram of full wave rectifier from X to Y through R L . Thus, we see that current
through R L always flows in one direction from X to Y.
Working
During the positive half cycle of the input AC, the diode Important points related to full wave rectifier
D 1 is in forward biased and the diode D 2 is in reverse (i) Output voltage is obtained across the load resistance
biased. The forward current flows through diode D 1. R L . It is not constant but pulsating in nature.
(ii) Average output
waveform at A
2V 2I 2V0
V av = 0 , I av = 0 , VDC =
π π
Input
2π 3π 4π
ωt  rf 
O
0 π π 1 + 
(i)  RL 
where, r f = forward biased resistance
waveform at B
3π and R L = load resistance.

π 2π 4π
Input
O ωt V I
(ii) (iii) rms output Vrms = 0 , I rms = 0
2 2
Due to Due to Due to Due to
D1 D2 D1 D2
(iv) Ripple factor r = 0.48 = 48%
Output waveform
(v) Ripple frequency The ripple frequency of full wave

(across RL)
ωt
rectifier
O π 2π 3π 4π = 2 × frequency of input AC
(vi) Peak inverse voltage (PIV) Its value is 2V0 .
812.
Fig. 14.28 Input and output waveforms of a full-wave rectifier (vii) Efficiency η % = for r f << R L , η = 812
. %
rf
1+
During the negative half cycle, the diode D 1 is reverse RL
biased and diode D 2 is forward biased. Thus, current flows I rms π
through diode D 2 . Thus, we find that during both the (viii) Form factor, f = =
I DC 2 2
halves, current flows in the same direction.
Note
(ii) Full wave bridge rectifier (i) The output signal frequency in full wave rectification is double
that of input signal frequency but in half-wave rectification, the
Another full wave rectifier called the bridge rectifier uses input and output signal frequency is same.
four diodes as shown in figure (ii) From rectifier, we get pulsating DC, which consists of AC ripples.
To remove these unwanted ripples, filter circuits are used.
Example 14.26 In a full wave rectifier circuit operating from side of the junction boundary, which recombines with
100 Hz mains frequency, what is the fundamental frequency majority carriers near the junction.
in the ripple?
On recombination of electron and hole, the energy is given
Sol. In full wave rectification, output signal (ripple) frequency out in the form of heat and light.
is double that of input frequency. So, output frequency is
200 Hz.
Example 14.27 In a centre tap full wave rectifier, the value

of the load resistance is 2k Ω. The voltage applied across p p R
the half of the secondary winding is given by
V = 220 sin 314t. Assume that, the each diode has a forward +
n
bias dynamic resistance of 20 Ω. Calculate (i) the peak value −V
of current, (ii) the DC value of current (iii) and the rms value
of current. Fig. 14.31 A forward biased LED
Sol. ComparingV = 220 sin 314 t with general equation
V = V0 sin ωt, we get
(iii) V-I characteristics
V0 = 220 V and ω = 314 rads −1
V-I characteristics of LED are given below, which is
Also, it is given that RL = 2 kΩ = 2000 Ω , rf = 20 Ω similar to that of a simple junction diode. But the
(i) Peak value of current, threshold voltages are much higher and slightly different
V0 220 for each colour. The reverse breakdown voltages of LEDs
I0 = = ≈ 109 mA
(rf + RL ) 20 + 2000 are very low. The colour of light emitted by a given LED,
(ii) DC value of current, depends on its band gap energy. The photon emitted by an
2I 0 2 × 109 LED is of energy equal to or slightly less than the band
I DC = = = 69.4 mA
π 314
. gap energy. Forward current conducted by the junction
I
(iii) rms value of current, I rms = 0 = 0.707 × 109 determines the intensity of light emitted by LED.
2 A low voltage DC supply is required to operate an LED.
= 77.06 mA
Current drawn by LED is of the order of milliampere. So,
in practice, a resistor of suitable value is joined in series
Special types of p-n junction diode with the LED to limit the current upto the safe value
The junction diodes are of many types required.
1. Light emitting diode (LED) I (mA)

Silicon
30
It is an important light source used in optical
communication and it converts electrical energy into light
20
energy. It is a forward biased p-n junction which emits
15
light spontaneously. 10
(i) Symbol –10V
V (volt)
It is represented by the symbol shown below. In actual, it 0 0.5 0.8
has two leads, the shorter lead represents n or cathode side 1 µA
while the longer lead represents p or anode side.
Fig. 14.32 V-I characteristics of LED
hν
Anode p n
Cathode (iv) Advantages
Cathode
Anode (a) Fast action and no warm up time is required.
Fig. 14.30 LED symbol (b) The bandwidth of emitted light is 100 Å to 500 Å, so
(ii) Working its nearly (not exactly) monochromatic.
When p-n junction is forward biased, electrons and holes (c) Long-life and ruggedness.
move towards opposite sides of junction through it. (d) Low operational voltage and less power consumed.
Therefore, there are excess minority carriers on the either (e) Fast ON-OFF switching capability.
Example 14.28 A voltage drop of 2V occurs across a light (iv) V-I Characteristics
emitting diode (LED) and a current of 10 µA is passed
through it when it is operated with a 6 V battery having a
Its V-I characteristics are shown in the figure given below.
limiting resistor R. What is the value of R? We observe from the figure that, current in photodiode
changes with the change in light intensity (I ) when reverse
V V
Sol. Current, I = or R = bias is applied.
R I
(6 − 2)V
Resistance of limiting resistor, R = = 400 kΩ (mA)
10 × 10−6A
2. Photodiode Reverse bias

(volt )
A photodiode is a special type of junction diode used for I1
current
Reverse
detecting optical signals. It is a reverse biased p-n junction I2
I3
made from a photosensitive material. In photodiode, current I4
carriers are generated by photons through photo-excitation. I4 > I3 > I2 > I1 (µA)
(i) Symbol Fig. 14.35 V-I characteristics of photodiode at different intensites

The symbol of a photodiode is
(v) Uses
hν The p-n photodiode can operate at frequencies of the order
of 1MHz, in contrast to the slow and bulk type photo-
Anode p n Cathode conductor which is limited to a frequency range from 100 to
Fig. 14.33 Symbol of a photodiode 5000 Hz. Hence, the photodiodes are extensively used in
high speed reading of computer punched cards,
(ii) Construction light-detection systems, light-operated switches, counting of
A photodiode is fabricated with a transparent cover to objects interrupting a light-beam, etc.
allow light to fall on the diode and is operated under Example 14.29 A p-n photodiode is made of a material with a
reverse bias. band gap of 1.5 eV. What is the minimum wavelength of
radiation that can be absorbed by the material?
(hν > Eg ) hc
Sol Use, energy, E = hν =
λ
The minimum wavelength of radiation,
µA hc (6.4 × 10−34 ) × (3 × 108 )
λ= =
p-side n-side E 1.5 × 1.6 × 10−19
= 8 × 10−7 m
R
– + = 800 nm
V
Fig. 14.34 A reverse biased photodiode illuminated with light 3. Solar cell
Solar cell is a p-n junction diode, which converts solar
(iii) Working energy into electrical energy. It is based on photovoltaic
When the photodiode is illuminated with light (photons), effect.
having energy greater than the energy gap of the
semiconductor, then electron-hole pairs are generated due (i) Symbol
to the absorption of photons. These charge carriers Its symbol is
contribute to the reverse current. They increase the +
hν
conductivity of the semiconductor.
Larger the intensity of the incident light, larger will be the
conductivity of the semiconductor. The value of reverse
saturation current increases with the increase in intensity
of incident light.
Hence, a measurement of the change in the reverse –
saturation current on illumination can give the values of Fig. 14.36 Symbol of a solar cell
light intensity.
(ii) Construction (v) Uses

It consists of a silicon or gallium-arsenide p-n junction Solar cells are used in space vehicles for charging batteries
diode packed in a can with glass window on the top. Here, in day time and then taking electrical power from them
a thin layer of n-type is grown on a p-type semiconductor. during night.
The top of the n-layer has few finger electrodes for the
light to reach it. The bottom of the p-layer is provided 4. Zener diode
with a current collecting electrode. It is a reverse biased heavily doped p-n junction diode. It is
hν
operated in breakdown region.
Zener diode is designed to operate in the reverse
breakdown voltage continuously without being damaged.
Top Metallised
surface finger electrode This can be achieved by changing the thickness of the
depletion layer to which the voltage is applied. Current
through the Zener diode is controlled by an external
resistance. Zener diode is represented by the symbol
n
n shown below
p p
Back contact p n
Fig. 14.37 p-n junction of solar cell Fig. 14.40 Symbol of Zener diode
(iii) Working
(i) V-I Characteristics
When photons of light (of energy hν > Eg ) falls at the
junction, electron-hole pairs are generated near the The V-I characteristics of Zener diode is shown below and
junction and they move in opposite directions due to we observe that when the applied reverse voltage (V )
junction field. reaches the breakdown voltage (VZ ) of the Zener diode,
They will be collected at the two sides of the junction, there is a large change in the current.
giving rise to a photovoltage between the top and bottom I (mA)
metal electrodes. The top metal contact acts as negative
electrode and bottom metal contact acts as positive
electrode. When an external load is connected across Reverse bias Forward bias
metal electrodes, a photocurrent flows. VZ
RL O V
IL
hn
I (µA)
p n Fig. 14.41 V-I characteristics of a Zener diode
Depletion region
But after the breakdown voltageVZ , a large change in the
Fig. 14.38 Flow of photocurrent in a solar cell
current can be produced by almost insignificant change in
the reverse bias voltage.
(iv) I-V characteristics
(ii) Uses
The I-V characteristics of solar cell are shown in the figure.
Though zener diode finds numerous applications in
We can see in the figure that, it is drawn in the fourth
electronics but mainly it is used as a voltage stabilizer
quadrant of the coordinate axes, because a solar cell does
(voltage regulator) and as a fixed reference voltage for
not draw current but supplies the same to the load.
I
calibrating voltmeters.
Open circuit voltage (Voc) (iii) Zener diode as a voltage regulator
V This is the most important application of a Zener diode.
O
(a) Principle
Isc
Short circuit current When the applied reverse voltage V reaches the
Fig. 14.39 I-V characteristic of a solar cell breakdown voltage VZ of the Zener diode, there is a large
change in the current. So, after the breakdown voltageVZ , Hence, the output voltage remains constant in both
a large change in the current can be produced by almost conditions. Figure shows the graph of output voltageVo
insignificant change in the reverse bias voltage, i.e. Zener versus input voltageVin of a Zener diode. Clearly, the
voltage remains constant even though the current through output voltage remains constant after the reverse
the Zener diode varies over a wide range. breakdown voltageVZ .
Zener diode is joined in reverse bias to the fluctuating DC Regulated output
input voltage through a resistance R. VZ voltage
Output voltage (Vo )

The constant output voltage is taken across a load
resistance connected in parallel with Zener diode.
I VZ
Input voltage (Vin)
RS
Fig. 14.43 Graph of Vo versus V in for a Zener diode
Unregulated IL
voltage
Example 14.30 The breakdown voltage of a Zener diode is
IZ
Load Regulated 12 V. It is used in a voltage regulator circuit shown in
RL voltage, VZ figure. Find the current through the diode.
250Ω
Fig. 14.42 Circuit diagram of Zener diode as a voltage regulator +
20 V 1 kΩ
–
(b) Working
Here, when input DC voltage increases beyond a certain
limit, the current through the circuit rises sharply, causing Sol. Current through 250 Ω resistor,
a sufficient increase in the voltage drop across the resistor Net voltage (20 − 12)
I1 = = = 32 × 10−3A = 32 mA
R S . Thus, the voltage across the Zener diode remains Resistance 250
constant and also the output voltage remains constant atVZ . Current through 1 kΩ resistor,
When the input DC voltage decreases, the current through 12
the circuit goes down sharply causing sufficient decrease I2 = = 12 × 10−3A = 12 mA
1 × 103
in the voltage drop across the resistance. Thus, the voltage
across the Zener diode remains constant and also the So, current through the Zener diode,
output voltage across R L remains constant atVZ . I Z = I1 − I 2 = 32 mA − 12 mA = 20 mA
CHECK POINT 14.2

1. In the depletion region of an unbiased p-n junction diode, (b) the p-end is connected to the positive terminal of the battery
there are (c) the direction of current is from n-end to p-end in the diode
(a) only electrons (b) only holes (d) the p-end is connected to the negative terminal of battery
(c) Both electrons and holes (d) only fixed ions
6. In forward bias, the width of potential barrier in a p-n junction
2. The cause of the potential barrier in a p-n diode is diode
(a) depletion of positive charges near the junction (a) increases (b) decreases
(b) concentration of positive charges near the junction (c) remains content (d) first increases then decreases
(c) depletion of negative charge near the junction
7. On adjusting the p-n junction diode in forward biased,
(d) concentration of positive and negative charges near the (a) depletion layer increases
junction.
(b) resistance increases
3. Barrier potential of a p-n junction diode does not depend on (c) Both decreases
(a) temperature (b) forward bias (d) None of the above
(c) doping density (d) diode design
8. If the two ends p and n of a p-n junction diode are joined by
4. What control the conduction of p-n junction? a wire, then
(a) Majority carriers (b) Minority carriers (a) there will not be a steady current in the circuit
(c) Holes (d) Electron (b) there will be a steady current from n-side to p-side
5. In the forward bias arrangement of a p-n junction diode, (c) there will be a steady current from p-side to n-side
(a) the n-end is connected to the positive terminal of the battery (d) there may or may not be a current depending upon the
resistance of the connecting wire
9. The reverse biasing in a p-n junction diode 12. In p-n junction, avalanche current flows in circuit when biasing
(a) decreases the width of potential barrier is
(b) increases the width of potential barrier (a) forward (b) reverse
(c) increases the number of minority charge carriers (c) zero (d) excess
(d) increases the number of majority change carriers
10. A reverse-biased diode is 13. The p-n junction diode is used as
(a) an amplifier (b) a rectifier
−6V −3V
(a) (c) an oscillator (d) a modulator
3V 14. In a p-n junction photocell, the value of photo-electromotive
(b)
force produced by monochromatic light is proportional to
(a) the voltage applied at the p-n junction
0V −2V
(c) (b) the barrier voltage at the p-n junction
2V −3V (c) the intensity of the light falling on the cell
(d)
(d) the frequency of the light falling on the cell
11. On increasing the reverse bias to a large value in a p-n 15. What is the order of the reverse saturation current before
junction diode, current breakdown in a Zener diode?
(a) increases slowly (a) Ampere
(b) remains fixed (b) Milliampere
(c) suddenly increases (c) It depends on the applied voltage
(d) decreases slowly (d) Microampere
JUNCTION TRANSISTORS
A junction transistor is a three terminal device which is The arrowhead in the symbol points inwards, i.e. towards
formed by sandwiching a thin wafer of one type of the base.
semiconductors between two layers of another type.
E p p C
The n-p-n transistor has a p-type wafer between two n
n-type layers. Similarly, the p-n-p transistor has a n-type B

wafer between two p-type layers. E C
Type of junction transistors B

p-n-p transistor
There are two types of junction transistors
Fig. 14.45 p-n-p transistor and its circuit symbol
n-p-n transistor
A n-p-n transistor is formed by sandwiching a thin layer Terminals of a transistor
of p-type semiconductor between two n-type A transistor is basically a three terminal device. Terminals
semiconductors as shown in figure. come out from the emitter, base and the collector for
Arrow indicates the direction of conventional current. In external connections.
n-p-n transistor, it will always point outwards, i.e. Emitter (E )
towards the emitter.
It is heavily doped and of moderate size as it emits the
majority charge carriers into the base by which current flows
E n p n C in the transistor.
B Base (B )
E C The base region is very lightly doped and thin. Most of the
charge carriers emitted by the emitter pass through it to the
B
n-p-n transistor collector.
Fig. 14.44 n-p-n transistor and its circuit symbol Collector (C )
The doping level of collector is neither very high nor very
p-n-p transistor low, however it lies between the doping levels of emitter
A p-n-p transistor is formed by sandwiching a thin layer and base. The size of the collector region is larger than the
of n-type semiconductor between two p-type other two regions because it collects the charge carriers from
semiconductors as shown in figure. the base.
Important points related to transistor

(i) In normal operation of a transistor, the emitter-base
Working of a transistor
junction is always forward biased and collector-base 1. p-n-p transistor
junction is reverse biased. From figure, it is clear that emitter-base junction is
(ii) The arrow on the emitter-base line shows the forward biased and collector-base junction is reverse
direction of current between emitter and base. biased.
(iii) In a n-p-n transistor, there are a large number of n-Base
p-Emitter Region p-Collector
conduction electrons in the emitter and a large
number of holes in the base. Similarly, in p-n-p p n p
IE
transistor, there are a large number of holes in the
E C
emitter and large number of electrons in the base.
(iv) If the junction is forward biased in n-p-n transistor, B
VEB VCB IC
the electrons will diffuse from emitter to the base IB
and holes will diffuse from the base to the emitter. + − + −
IE IC
(v) The direction of electric current at this junction is VEE VCC
therefore from the base to the emitter in n-p-n p–n–p
transistor. E C
(vi) In the connecting wires, electrons are always IE IC

responsible for current flow, but inside the transistor IE B IC
holes are mainly responsible for current flow in
IB
p-n-p transistor and electrons in case of n-p-n + − + −
transistor. VEB VCB
Fig. 14.46 Action of p-n-p transistor and its biasing
Biasing of transistor
Biasing of a transistor is defined as the process of applying The resistance of emitter-base junction is very low. So, the
external voltages or potential difference to it. voltage ofVEB is quite small whereas the resistance of
collector-base junction is very high, so the voltage ofVCB
The biasing of the two p-n junction in a transistor, i.e. is very high. The forward biasing of the emitter-base circuit
emitter junction and collector junction depends on the repels the holes of emitter towards the base and electrons of
four modes, i.e. active mode, saturation mode, cut-off base towards the emitter. As the base is very thin and
mode and inverse mode. lightly doped, most of the holes
Active mode is also known as linear mode operation. A (> 95%) entering it pass on to collector, while a very few of
transistor is mostly used in the active region of operation, them (< 5%) recombine with the electrons of the base region.
i.e. emitter-base junction is in forward biased and As soon as a hole combines with an electron, an electron
collector-base junction is in reverse biased. from the negative terminal of the batteryVEB enters the
In saturation mode, maximum collector current flows and base. This sets up a small base current I B .
transistor acts as a closed switch from collector to emitter Each hole entering the collector region combines with an
terminal. In cut-off mode, the circuit behaves as open electron from the negative terminal of the batteryVCB and
switch, where only leakage current flows. gets neutralised. This creates collector current I C . Both the
The emitter and collector are interchanged in inverse base current I B and collector current I C combine to form
mode. emitter current I E .
Different modes of operation of a transistor is given below ∴ IE = IB + IC
Operating mode Emitter-base bias Collector-base bias Thus inside the p-n-p transistor, the current conduction is
due to holes while electrons are the charge carriers in the
Active Forward Reverse external circuit.
Saturation Forward Forward
2. n-p-n transistor
Cut off Reverse Reverse
In this transistor, the emitter-base junction is forward biased
Inverse Reverse Forward and its resistance is very low. So, the voltage ofVEB is quite
small.
The collector-base junction is reverse biased. The resistance Now, IE = IC + IB

of this junction is very high, so the voltage ofVCB is quite ∴ Base current, IB = IE − IC
large. = 10.53 − 10
p-Base = 0.53 mA
n-Emitter Region n-Collector
p
Transistor circuit configurations
E n n C A transistor is a three terminal device. One terminal out of
the three serves as a reference point for the entire circuit.
IE This terminal should be common to the input and output
B
VEB VCB IC
circuits and is connected to ground.
IB So, a transistor can be used in the following three
− + − + configurations
IE IC
VEB VCB 1. Common emitter (CE) configuration
n–p–n
E C
2. Common base (CB) configuration
IE IC 3. Common collector (CC) configuration
The figure given below shows the three types of circuit
IE B IC
arrangements for an n-p-n transistor
IB
− + − + IE E C IC
VEB VCB
Fig. 14.47 Action of n-p-n transistor and its biasing B Output
Input VBE VCB
The forward bias of the emitter-base circuit repels the
electrons of emitter towards the base, setting up emitter VBB VCC
current I E . As the base is very thin and lightly doped, a

very few electrons (< 5%) from the emitter combine with (a) Common base configuration
the holes of base, giving rise to base current I B and the C IC
IB
remaining electrons (> 95%) are pulled by the collector B
which is at high positive potential. The electrons are Output
finally collected by the positive terminal of batteryVCB , E VCE
Input VBE
giving rise to collector current I C .
VBB VCC
As soon as an electron from the emitter combines with a
hole in the base region, an electron leaves the negative
terminal of the batteryVEB and at the same time, the positive (b) Common emitter configuration
E IE
terminal of batteryVEB receives an electron from the base. IB
This sets a base current I B . Similarly, corresponding to B
each electron that goes from collector to positive terminal Output
C VCE
ofVCB , an electron enters the emitter from negative Input VBC
terminal ofVCB . VCC
VBB
Hence, emitter current = base current + collector current
or IE = IB + IC (I B << I C )
(c) Common collector configuration
Here, I B is a small fraction of I C depending on the shape of
Fig. 14.48 Configurations for n-p-n transistor
transistor, thickness of base, doping levels, bias voltages, etc.
Example 14.31 In n-p-n transistor circuit, the collector current
is 10 mA. If 95% of the electrons emitted reach the collector,
Common emitter characteristics
what is the base current? The graphs drawn between voltages and currents, when
Sol. IC = 95% IE emitter of a transistor is common to input and output
⇒ IC = 0.95 IE circuits are known as CE characteristics of a transistor.
I 100 The circuit diagram for studying CE characteristics of a
⇒ IE = C = × 10 mA = 10.53 mA
0.95 95 n-p-n transistor is given below.
Here, base-emitter circuit is forward biased with battery ∆I B at constant collector-emitter voltageVCE . It is
VBB and emitter-collector circuit is reverse biased with reciprocal of slope of I B -VBE curve.
batteryVCC .  ∆V 
IC Input resistance, R i =  BE 
 ∆I B  V = constant
− + CE
C mA
IB
B + 2. Collector or output characteristics
+ µA − VCE −
+ E +
A graphical relation between the collector-emitter voltage
VBE
− −
VCC VCE and collector current I C by keeping base current
+ VBB IE
− IB IC constant is called output characteristics of the transistor.
To study the output characteristics of transistor, we keep
value of base current I B fixed (say at 10 µA) with the help
Fig. 14.49
ofVBE . Now, gradually change the value ofVCE and note
Three types of characteristic curves are obtained the values of collector current I C . Plot I C -VCE graph.
Repeat the process for different constant values of I B .
1. Emitter or Input characteristics The value ofVCE upto which the I C changes withVCE is
A graphical relation between the base-emitter voltage called knee voltage. The transistors are operated in the
(VBE ) and the base-emitter current (I BE ) by keeping region above knee voltage. The output characteristics are
collector-emitter voltage (VCE ) constant is called input shown as
characteristics of the transistor. Adjust collector-emitter
voltage at a suitable high valueVCE (say = +10 V ). Base current (IB)
10
It is necessary so as to make the base-collector junction Collector current (IC) in mA
reverse biased. 60 µA
8
50 µA
Now, with the help of rheostat, gradually increase the 6 40 µA
value of base-emitter voltageVBE in small steps and note 30 µA
the corresponding values of base current I B . Similarly, 4
20 µA
take the readings forVCE = 4 V. 10 µA
2
100 VCE = 4 V 0 2 4 6 8 10 12 14 16
VCE = 10 V Collector to emitter voltage (VCE) in volt
80
Fig. 14.51 Output characteristics of a CE n-p-n transistor
Base current
60
∆IB
(IB )
40 Observation from the graph

From the graph, it can be concluded
20
∆VBE (i) For a given value of base current, the collector current is
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 not zero even when collector voltage is zero.
Base to emitter voltage (VBE ) in volts (ii) For a given base current, there is a rapid increase in
Fig. 14.50 Input characteristics of a CE n-p-n transistor collector current for a small increase of collector
voltage. It is the region of low collector resistance,
Observations from the graph transistor is never operated in this region.
From the graph, it can be concluded that (iii) For a given base current, the collector current
(i) For a given collector voltage, the base current become saturated for a certain collector voltage.
increases rapidly with increase in emitter-base Beyond which there is no increase in collector
voltage. It means that, input resistance is very small. current for further increase in collector voltage. It is
(ii) For a higher negative collector voltage, the base the region of high collector resistance.
current increases more rapidly with the collector Output resistance
voltage.
From the output characteristics, we define output
Input resistance resistance of transistor as the ratio of change in
It is defined as the ratio of small change in base-emitter collector-emitter voltage to the resulting change in
voltage ∆VBE to the resulting change in the base current collector current at constant base current. Thus,
 ∆V  Relation between α and β

Output resistance, r o =  CE 
 ∆I C  I β α
B = constant α= and β=
1+ β 1− α
= Reciprocal of slope of I C -VCE curve
Note
3. Transfer characteristics (i) α and β are independent of current, if the emitter-base junction is in
The graph between the collector current I C and the base forward biased and the collector-base junction is in reverse biased.
current I B at constant values of collector-emitter (ii) The value of current gain β is from 15 to 50 which is much greater
than α.
voltageVCE .
The transfer characteristic of a transistor is almost a Example 14.32 The current gain for common base transistor
straight line. is 0.98. Find the current amplification factor, if the
transistor is used in common emitter configuration.
IC (mA) Sol. It is given that, α = 0.98
α
Transfer VCE = 4.5 V As we know, β=
10 1− α
where, α = current amplification factor for common base
transistor and
5
β = current amplification factor for common emitter transistor.
0.98
⇒ β= = 49
0 100 200 IB (µA) (1 − 0.98)
Fig. 14.52 Transfer characteristics of CE n-p-n transistor Example 14.33 The current factor of a transistor in a
common base arrangement is 0.98. Find the change in
Current amplification factors for collector current corresponding to a change of 5.0 mA in
emitter current. What would be the change in base current?
different configurations of a transistor Sol. Given, α = 0.98 and ∆iE = 5.0 mA
There are two types of current amplification factors in a ∆i
From the definition, α = C
transistor ∆iE
Change in collector current,
Common base current ∆iC = (α )(∆iE ) = (0.98) (5.0) mA = 4.9 mA
amplification factor Further, change in base current,
It is the ratio of small change in the collector current to the ∆iB = ∆iE − ∆iC = 5 − 4.9 = 01 . mA
small change in the emitter current at constant collector Example 14.34 The current amplification factor for common
base voltage. It is denoted by α and is given by emitter arrangement is 59. If the emitter current is 5 mA,
find the value of collector current.
 ∆I  Sol. Current amplification factor for common emitter
α= C
 ∆I E VCB = constant transistor, β = 59
Emitter current, IE = 5 mA
β
Common emitter current As, α=
1+ β
amplification factor IC
It is the ratio of small change in the collector current to the Also, α=
IE
small change in the base current at constant
collector-emitter voltage. It is denoted by β and is given by IC β  β 
∴ = ⇒ IC =   IE
IE 1 + β 1 + β 
 ∆I   59 
β= C IC =   × 5 = 4.92 mA
 ∆I B VCE = constant 1 + 59
Example 14.35 In a n-p-n transistor (in common emitter The collector-emitter circuit is reverse biased by a high
mode), 1010 electrons enter the emitter in 10 −6 s . Only 2% of
voltage batteryVCC , that means the resistance of output
the electrons are lots in the base. Calculate the base current
circuit is high. R L is a load resistance connected in
and the current amplification factor.Charge on electron is collector-emitter circuit. The weak input AC signal is
. × 10 −19 C.
16 applied across the base-emitter circuit and amplified
q 1010 × 1.6 × 10−19 output signal is obtained across collector-emitter circuit.
Sol. Current, iE = = −6
= 1.6 mA
t 10 When no AC voltage is applied to the input circuit,
 2  we have IE = IB + IC …(i)
Base current, iB = 2% of iE =   × 1.6 mA = 0.032 mA
100 Due to collector current I C , the voltage drop across load
∴ iC = iE − iB = 1.568 mA resistance R L is I C R L . Therefore, the collector-emitter
voltageVCE is given by
Therefore, current amplification factor,
i 1.568 VCE = VCC − I C R L …(ii)
β= C = = 49 When the input AC voltage signal is applied across
iB 0.032
base-emitter circuit, it changes base-emitter voltage and
hence, emitter current I E changes, which in turn changes
Transistor as an amplifier the collector current I C . So, the collector-emitter voltage
An amplifier is a device which is used for increasing the VCE varies in accordance with Eq. (ii). This variation in
amplitude of input signal. A transistor can be used for VCE appears as an amplified output.
amplifying a weak signal. For a transistor to be operated as Note The output voltage signal is 180° out of phase with the input
amplifier, three different basic circuits can be used. These voltage signal in the common emitter amplifier.
are common base, common emitter and common collector.
Gains in common emitter amplifier
Principle DC current gain
In a transistor, there are two p-n junctions; one is forward It is defined as the ratio of the collector current to the base
biased (low resistance) and other is reverse biased (high current (VCE = constant ) and is denoted by β DC . Thus,
resistance). The weak input signal is applied across the
I 
forward biased junction and output signal is taken across β DC =  C 
the reverse biased junction. Since, the input and output  I B  V = constant
CE
currents are almost equal, the output signal appears with a
much higher voltage, because of high output resistance. AC current gain
The emitter is always forward biased whereas the collector It is defined as the ratio of the small change in the collector
is always reverse biased no matter which configuration has current to the small change in the base current at a
to be used. constant collector-to-emitter voltage and is denoted by β AC .
 ∆I 
Common emitter amplifier using a n-p-n Thus, β AC =  C 
 ∆I B  V = constant
transistor CE
Note Since, I C increases with IB almost linearly and I C = 0 when

The circuit diagram for n-p-n transistor as an amplifier is
IB = 0, therefore the values of both β AC and β DC are nearly equal.
shown in the figure given below
C IC AC voltage gain
IB B It is defined as the ratio of the change in the output
n-p-n RL voltage to the change in the input voltage and is denoted
VBE
E
VCE IC by AV . Suppose, on applying an AC input voltage signal,
+ the input base current changes by ∆I B and
IE
Input VCC correspondingly the output collector current changes by
–
AC´ + – Amplified ∆I C . If R in and R out are the resistances of the input and
Signal RB IB IC Output the output circuits respectively, then
VBB AC Signal
∆I × R out ∆I C R out
Fig. 14.53 Circuit diagram of transistor as an amplifier AV = C = ×
∆I B × R in ∆I B R in
The emitter-base circuit is in forward biased by a low voltage
batteryVBB , that means the resistance of input circuit is small. Note The voltage gain in common-emitter amplifier is large compared
to that in common base amplifier.
The base emitter voltage is given byVBE = VBB − I B R B .
Now, ∆I C / ∆I B is the AC current gain β AC and R out /R in Example 14.36 In a transistor connected in common emitter
is the resistance gain, then mode R 0 = 4 k Ω, R i = 1k Ω, i c = 1 mA and i b = 20 µA.
Find the voltage gain.
AV = β AC × Resistance gain
ic 1 × 10−3
Sol. Current gain, β = = = 50
i.e. Voltage gain = Current gain × Resistance gain ib 20 × 10−6
R   4
AC power gain ∴ Voltage gain, AV = β  0  = (50)   = 200
 Ri   1
It is defined as the ratio of the change in the output power
to the change in the input power. Since, Example 14.37 A load of 3 k Ω is connected in the collector
branch of an amplifier circuit using a transistor in common
Power = Current × Voltage emitter mode. The current gain β = 40. The input resistance
We have, AC power gain = AC current gain of the transistor is 0.40 kΩ. If the input current is changed
× AC voltage gain by 40 µA, then
(i) calculate the change in output voltage.
= β AC × AV = β AC × ( β AC × Resistance gain)
(ii) also find the change in the input voltage.
= β 2AC × Resistance gain (iii) calculate the power gain.
Note As β 2AC >> α 2AC , the AC power gain of a common emitter Sol. Given, load resistance, RL = 3 kΩ = 3 × 103 Ω, β = 40,
amplifier is much larger than that of a common base amplifier.
ri = 0.40 k Ω = 0.4 × 103 Ω
Transconductance (g m ) Base current, ∆IB = 40 µA = 40 × 10−6 A
It is defined as the ratio of the change in the collector (i) Output voltage,
current to the change in the base-to-emitter voltage at Vo = ∆IC RL = β∆IBRL = 40 × 40 × 10−6 × 3 × 103 = 4.8 V
constant collector-to-emitter voltage and is (ii) ∆VBE = ∆IBri = 40 × 10−6 × 0.4 × 103 = 16 × 10−3 V
denoted by gm .
 ∆I C  β 2RL  3 × 103 
(iii) Power gain, AP = = (40)2   = 12000
Thus, gm =   ri  0.4 × 103 
 ∆VBE  V
CE = constant
We can express it in terms of β AC , Example 14.38 A transistor is used in common emitter mode
in an amplifier circuit. When a signal of 40 mV is added to
∆I ∆I the base-emitter voltage, the base current changes by 40 µA
gm = C × B (QVBE = Vi )
∆I B ∆Vi and the collector current changes by 4 mA. The load
resistance is 5 kΩ. Calculate
∆I C ∆V (i) β,
Now, = β AC and i = R in
∆I B ∆I B (ii) the input resistance Ri ,
(a resistance of the input circuit) (iii) the transconductance g m
β (iv) and the voltage gain.
∴ gm = AC
R in Sol. (i) Given, ∆ib = 40 µA and ∆ic = 4 mA
The unit if gm is Ω −1
(ohm −1
) or S (siemen). ∆ ic 4 × 10−3
β= = = 100
∆ib 40 × 10−6
Note Common emitter amplifier using n-p-n transistor is same as
common emitter amplifier using p-n-p transistor.
(ii) ∆Vi = (∆ib ) × Ri
∆Vi 40 × 10−3
∴ Ri = =
Important points in common base amplifier ∆ ib 40 × 10−6
(i) The output voltage signal is in phase with the input = 1000 Ω = 1 kΩ
voltage signal. ∆ ic 4 × 10−3
(iii) Transconductance, g m = = = 0.1 Ω −1
(ii) The common base amplifier is used to amplify high ∆Vi 40 × 10−3
(radio)-frequency signals and to match a very low R   5
source impedence (~20 Ω) to a high load impedence (iv) Voltage gain, AV = β  out  = (100)   = 500
 R in   1
(~100 kΩ).
25
Example 14.39 In a common emitter amplifier, the load Current gain factor, α =
resistance of the output circuit is 500 times the resistance of 26
the input circuit. If α = 0.98, then find the (i) voltage gain α 25 /26
⇒ β= = = 25
and (ii) power gain. 1 − α 1 − 25 /26
R out α 0.98
Sol. Given, α = 0.98 and = 500, β = = = 49 ∆IC 10−3
R in 1 − α 1 − 0.98 Base current, ∆IB = = = 4 × 10−5A = 40 µA
β 25
R  R 800
(i) Voltage gain = (β)  out  = (49)(500) = 24500 Voltage gain, AV = β L = 25 × = 100
 Rin  ri 200
R  R
(ii) Power gain = (β 2)  out  = (49)2 (500) = 1200500 Power gain, AP = β 2 L = βAV = 25 × 100 = 2500
 Rin  ri
Example 14.40 A transistor is connected in common emitter Example 14.42 An n-p-n transistor in a common-emitter mode
(CE) configuration. The collector supply is 8 V and the is used as a simple voltage amplifier with a collector current
voltage drop across a resistor of 800 Ω in the collector of 4 mA. The terminal of 8 V battery is connected to the
circuit is 0.5V. If the current gain factor α is 0.96, find the collector through a load resistance R L and to the base through
base current. a resistance R B . The collector-emitter voltageVCE = 4 V,
Sol. Given, VCC = 8 V,V0 = 0.5V, RL = 800 Ω base-emitter voltageVBE = 0.6 V and base current
amplification factor β DC = 100. Calculate the values of R L
and α = 0.96 and R B .
α 0.96 Sol. IB IC
Current gain, β = = = 24
1 − α 1 − 0.96 RB RL
We have, V0 = ∆IC RL B C VCC = VBB = 8 V
∴ 0.5 = ∆IC × 800 E VCE

0.5 VBE
Collector current, ∆IC = A
800
∆IC Given,VCE = 4 V,VBE = 0.6 V, β = 100
Current amplification factor, β =
∆IB
and ∆IC = 4 mA = 4 × 10−3A
∆IC 0.5/800
Base current, ∆IB = = = 26 × 10−6A = 26 µA we have,VCE + ∆IC RL = VCC
β 24
4 × 10−3RL = 8 − 4 = 4
Example 14.41 An n-p-n transistor is connected in common
emitter configuration in which collector supply is 8 V and Load resistance, RL = 1000 Ω
the voltage drop across the load resistance of 800 Ω 4 × 10−3
Base current, IB = IC / β = = 4 × 10−5A
connected in the collector circuit is 0.8 V. If current gain 100
factor is (25/26), determine the collector-emitter voltage and
We have,VBB = IBRB + VBE
base current. If the internal resistance of the transistor is
200 Ω, calculate the voltage gain and power gain. 8 = IBRB + 0.6
Sol. IC ∴ IB RB = 7.4 V
−5
IB C 4 × 10 RB = 7.4
B
Resistance connected to the base,
E RL = 800 Ω V0 = 0.8 V 7.4
RB RB = × 105 = 1.85 × 105 Ω = 185 kΩ
4
Example 14.43 In the following circuit, the value of β is 200.

VBB VCC = 8 V Find IB ,VCE ,VBE andVBC , when IC = 2.5 mA. Find whether
transistor is in active, cut-off or saturation state.
We have,V0 = ∆IC RL ; 0.8 = ∆IC × 800
+20 V
⇒ ∆IC = 10−3A 5.0 kΩ
120 kΩ
VCC = VCE + ∆IC RL C
⇒ 8 = VCE + 10−3 × 800
B
Collector emitter voltage,VCE = 8 − 0.8 = 7.2 V E
IC (ii) Base current amplification factor,

Sol. Here, β =
IB ∆IC 3 × 10−3
β= = = 66.67
⇒
I
IB = C =
2.5
= 0.0125 mA ∆IB 45 × 10−6
β 200
(iii) Voltage gain of the amplifier,
As we know, RL 66.67 × 7 × 103
−3 3 AV = β = = 424.27
VCE = VCC − IC RC = 20 − (2.5 × 10 ) × (5 × 10 ) = 7.5 V ri . × 103
11
Also,VBE = 20 − IBRB = 20 − (0.0125 × 10−3 ) × (120 × 103 ) Note Kirchhoff’s laws can be applied in a transistor circuit in the
similar manner as is done in normal circuits.
= 18.5 V
∴ VBC = (VBE − VCE ) = (18.5 − 7.5) = 11 V
The transistor is in active state because EB region is forward
Transistor as an oscillator
biased and CB region is reverse biased. An oscillator is an electronic device which produces electric
oscillation of constant frequency and amplitude, without
Example 14.44 In the following common emitter any externally applied input signal. It converts DC energy
configuration, a n-p-n transistor with current gain β = 95 is obtained from a battery into AC energy.
used. What is the output voltage of the amplifier?
1. Principle of an oscillator
Figure shows the block diagram of an oscillator. An
B C n-p-n
100 kΩ oscillator may be regarded as amplifier which provides its
E Vout own input signal.
Input 2 kΩ
voltage Input
1 mV
Transistor
L C amplifier Output
V 1 mV
Sol. Input current, I in = in = = 0.5 × 10−6 A
R in 2 kΩ
I out
Q β= (Q RBE ≈ 0) Feedback
I in circuit
∴ Output current,
Fig. 14.54 Principle for an oscillator
I out = β ⋅ I in = (95 × 0.5 × 10−6 ) A
= 0.47 × 10−4 A Essential parts of a transistor oscillator are
∴ Output voltage, Vout = I out ⋅ R out (i) Tank circuit It is a parallel combination of an
inductance L and a capacitance C . The frequency of
= (0.47 × 10−4 A)(100 kΩ )
electric oscillations in the tank circuit is
= 4.7mV 1
f =
Example 14.45 A p-n-p transistor is used in common emitter 2π LC
mode in an amplifier circuit. A change of 45 µA in the base
current brings a change of 3 mA in collector current and (ii) Transistor amplifier The amplifier receives the
0.05 V in base-emitter voltage. oscillations from the tank circuit and amplifies it.
Find the (iii) Feedback circuit It returns a part of the output
(i) input resistance ri and power of the transistor amplifier to the tank circuit
(ii) the base current amplification factor (β ). and produces undamped oscillations. This process is
(iii) If a load of 7k Ω is used, then also find the voltage gain of called positive feedback.
the amplifier.
Amplifier Output
Sol. Given,
∆IB = 45 µA = 45 × 10−6A, ∆IC = 3mA = 3 × 10−3A
∆VBE = 0.05 V and RL = 7kΩ = 7 × 103 Ω
(i) Input resistance, LC network
∆VBE 0.05
ri = = . × 103 Ω
= 11 Fig. 14.55 Feedback circuit
∆IB 45 × 10−6
2. Construction Transistor as a switch

A basic circuit using a common emitter n-p-n transistor as
Transistor has an ability to turn things ON and OFF, so
an oscillator is given below. A tank circuit (L-C circuit) is
the most common use of transistor in an electronic circuit
connected in the emitter-base circuit. A small coil L ′ called
is as a simple switch.
feedback or tickler coil is connected in the
emitter-collector circuit. The coil L ′ is inductively coupled A transistor can be used as a switch because its collector
with the coil L of the tank circuit. current is directly controlled by the base current.
To understand it properly, let us consider a basic circuit
using a common emitter n-p-n transistor as a switch which
L′
is given below
Inductive C
coupling B B2 IC
n-p-n RB B C n-p-n
E IB RC
Output L C
E Vo Output
B1 S Vi voltage
VBE
Input IE VCC
voltage
Fig. 14.56 Transistor as an oscillator
Collector supply
voltage
3. Working
When the switch S is closed, electrical oscillations are Fig. 14.57 Common emitter n-p-n transistor as a switch
developed in the tank circuit. The circuit containing n-p-n
transistor amplifies these oscillations. A part of the Apply Kirchhoff’s voltage rule to the input and output
amplified signal in the collector circuit is fedback in the sides of this circuit, we get
base circuit by the coupling between L and L′ . This cycle Vi = I B ⋅ R B +VBE (Vi = DC input voltage)
repeats again and again to give electric oscillations of
and Vo = VCC − I C ⋅ R C (V0 = DC output voltage)
constant amplitude and of constant frequency
1 In case of silicon transistor, ifVi < 0.6 V, I B will be zero,
f = hence I C will be zero and transistor will operate in cut-off
2π LC state, andVo = VCC .
The oscillations of the desired frequency can be obtained
WhenVi > 0.6 V, some I B flows, so some I C flows and
by changing the value of capacitance C of the variable
transistor will now operate in active state and hence output
capacitor. The oscillations can be transferred to an external
Vo decreases as the term I C R C increases. With increase in
circuit by mutual induction in coil connected in that circuit.
Vi , the I C increases almost linearly and henceVo decreases
4. Need for positive feedback linearly till its value becomes less than about 1 volt.
The oscillations are damped due to the presence of some Cut-off
inherent electrical resistance in the circuit. Hence, the Vo region
Active
amplitude of oscillations decreases rapidly and ultimately region
Saturation
stops. To have oscillations of constant amplitude, a region
positive feedback is necessary from the output circuit to
the input circuit so that the losses in the circuit can be
compensated.
Note Vi
(i) Gain of the amplifier is given by
V Fig. 14.58 Transfer characteristic
A = o (Gain without feedback)
Vi
Beyond this, the change becomes non-linear and transistor
Vo
(ii) A = (Gain with positive feedback) now goes into the saturation state. WhenVi is further
Vi + mVo
increased,Vo is found to decrease towards zero ( however,
where, m = feedback fraction.
it may never become to zero).
Now the operation of transistor as a switch can be

understood in the following way. WhenVi is low (in Effect of temperature on the
cut-off region),Vo is high. IfVi is high (in saturation working of transistor
region), thenVo is low, almost zero. A transistor is a temperature-sensitive device. In the transistor,
If we define low and high states as below and above conduction is due to the movement of charge carriers, i.e.
certain voltage levels corresponding to cut-off and electrons and holes. When temperature of the transistor
saturation of the transistor, then we can say that a low increases, many covalent bonds may break up, resulting in the
input switches the transistor OFF and high input switches formation of more electrons and holes. Due to which current
it ON. Alternatively, we can say that, a low input to the will increase in the transistor and this current gives rise to the
transistor gives a high output and a high input gives a low production of more heat energy. The excess heat so produced
output. The switching circuits are designed in such a way causes complete breakdown of the transistor.
that the transistor does not remain in active state.
CHECK POINT 14.3

1. In a p-n-p transistor, the base is the n-region. Its width 8. In the CB mode of a transistor when the collector
relative to the p- region is voltage is changed by 0.5 V. The collector current changes
(a) smaller (b) larger by 0.05 mA. The output resistance will be
(c) same (d) not related (a) 10 kΩ (b) 20 kΩ
(c) 5 kΩ (d) 2.5 kΩ
2. The heavily and lightly doped region of a bipolar junction
transistor are respectively. 9. While a collector to emitter voltage is constant in a
(a) base and emitter (b) base and collector transistor, the collector current changes by 8.2 mA when
(c) collector and base (d) emitter and base the emitter current changes by 8.3 mA. The value of
forward current ratio β is
3. The concentrations of impurities in a transistor are (a) 82 (b) 83
(a) equal for the emitter, base and collector region (c) 8.2 (d) 8.3
(b) least for the emitter region
(c) largest for the emitter region 10. In a common base mode of a transistor, the collector
current is 5.488 mA for an emitter current of 5.60 mA. The
(d) largest for the base region
value of the base current amplification factor (β) will be
4. An n-p-n transistor conducts when (a) 50 (b) 51
(a) both collector and emitter are positive with respect to the (c) 48 (d) 49
base
11. Consider an n-p-n transistor amplifier in common emitter
(b) collector is positive and emitter is negative with respect to
configuration. The current gain of the transistor is 100. If
the base
the collector current changes by 1mA, what will be the
(c) collector is positive and emitter is at same potential as the change in emitter current?
base
(a) 1.1 mA (b) 1.01 mA
(d) both collector and emitter are negative with respect to the
base. (c) 0.01 mA (d) 10 mA
5. When p-n-p transistor is used as an amplifier 12. A common emitter amplifier gives an output of 3 V for an
input of 0.01V. If β of the transistor is 100 and the input
(a) electrons move from base to emitter
resistance is 1kΩ, then the collector resistance is
(b) holes move from emitter to base
(a) 1 kΩ (b) 3 kΩ
(c) electrons move from base to emitter
(c) 30 kΩ (d) 30 Ω
(d) holes move from base to emitter
13. An amplifier has a voltage gain A V = 1000. The voltage gain
6. When n-p-n transistor is used as an amplifier (in dB) is
(a) electrons move from base to collector (a) 30 (b) 60
(b) holes move from emitter to base (c) 3 (d) 20
(c) electron move from collector to base
(d) holes move from base to emitter 14. Which of the following is used to produce radio waves of
constant amplitude?
7. For a transistor, in a common emitter arrangement, the (a) Oscillator (b) Diode (c) Rectifier (d) Amplifier
alternating current gain β is given by
 ∆I   ∆I  15. An oscillator is nothing but an amplifier with
(a) β =  C  (b) β =  B  (a) positive feedback
 ∆I B  VC  ∆I C  VC (b) large gain
 ∆I   ∆I  (c) no feedback
(c) β =  C  (d) β =  E 
 ∆I E  VC  ∆I C  VC (d) negative feedback
ANALOG AND DIGITAL CIRCUITS

All electronic circuits are broadly divided into two These values may be represented by two symbols 0 and 1.
categories, which are discussed below In a number system in which, we have only two digits is
called a binary system.
1. Analog circuits In binary system, usually we write 1 for positive response
A continuous time-varying voltage or current signal is (e.g. when a switch is ON) and 0 for negative (when
called analog signal. switch is OFF).
Current/ voltage
Analog signal
Decimal and binary number
t systems
Time
1. Decimal number system
Fig. 14.59 Analog signal In decimal number system, ten digits are used, i.e. 0, 1, 2,
The electronic circuits which process analog signals are 3, 4, 5, 6, 7, 8, 9. The base of the decimal number system
called analog circuits. is 10.
The place values are found by raising the base 10 to the
The devices like amplifiers, radio, television, oscillators
power of the place.
etc. make use of analog signals.
Also, powers are numbered to the left of the decimal point
2. Digital circuits starting with 0 and to the right of the decimal point
A signal that can take only two discrete values of current starting with –1.
or voltage is called digital signal. e.g. 2876 = 2000 + 800 + 70 + 6
A digital signal can take only two values, i.e. 0 and 1, MSD LSD
which are marked as low and high values respectively. = 2 × 10 3 + 8 × 10 2 + 7 × 10 1 + 6 × 10 0
In the square wave shown in Fig 14.60, a signal of 0 V
represents binary 0 and a signal of 5V represents binary 1. where, LSD = least significant digit
and MSD = most significant digit.
Voltage (V)
level 1
5V
level Digital
2. Binary number system
0 signal In binary number system, only two digits 0 and 1 are used.
0V In binary system, the base is 2. The two binary digits 0
Time (t)
and 1 are called bits and a group of bits is known
Fig. 14.60 Digital signal
as a byte. [1 byte = 8 bits]
The electrical circuits which process digital signals are In a binary number, the place value of each bit
called digital circuits. e.g. Pocket calculators, burglar corresponds to some power of 2. e.g.
alarms, modern computers, etc.
1101.011 = 1 × 2 3 + 1 × 2 2 + 0 × 21 + 1 × 2 0 + 0 × 2 −1
Advantages of digital circuits
+ 1 × 2 −2 + 1 × 2 −3
(i) It has high accuracy and precision.
(ii) It is easier to design. = 8 + 4 + 0 + 1 + 0 + 0.25 + 0125
. = 13.375
(iii) Information can be stored easily.
(iv) Digital circuits are less affected by the noise. 3. Conversion of a decimal number into
(v) They typically uses less bandwidth. its equivalent binary number
(vi) It enables long distance transmission. A decimal number can be converted into binary number
by using divide by 2 rule. We go on dividing the given
Binary System decimal number by 2, until the quotient is zero and write
There are number of questions which have only two down the remainder after each division. These remainders
answers Yes or No. A statement can be either True or when taken in reverse order form the required binary
False. A switch can be either ON or OFF. number. Let us convert 23 into its binary equivalent.
Divide by 2 23 Remainder
4. Conversion of a binary number into its
Divide by 2 11 1 LSD equivalent decimal number
Divide by 2 5 1 In binary number system, base is 2. Therefore, the least
Divide by 2 2 1 significant digit in the binary number is the coefficient of
Divide by 2 1 0
2 with power zero. As, we move towards the left side of
LSD, the power of 2 goes on increasing.
0 1 MSD
e.g. ( 1 00110 1 ) 2
↓ ↓
The remainders in reverse order are 10111. Hence, the MSD LSD
binary equivalent of 23 is 10111. Symbolically, we write = 1× 2 6 + 0 × 2 5 + 0 × 2 4 + 1 × 2 3
(23 ) 10 = (10111) 2
The conversion of a decimal fraction into binary fraction is + 1 × 2 2 + 0 × 21 + 1 × 2 0 = 77
performed by multiply by 2 rule. Let us convert 0.125 into Note that, while finding the decimal equivalent of a
its binary equivalent. fractional binary number, the multipliers will be
Binary 2 −1, 2 −2, 2 −3 … starting from MSD, till LSD is reached.
0.125 × 2 = 0.250 0 e.g. (0. 101 1 )
↓ ↓
MSD LS D
0.250 × 2 = 0.500 0
0.500 × 2 = 1.000 1 = 1 × 2 −1 + 0 × 2 −2 + 1 × 2 −3 + 1 × 2 −4
0.000 × 2 = 0.000 1 1 1
0 = +0+ + = 0.6875
2 8 16
The recovered binaries taken from top to bottom form the
(01011
. ) 2 = (0.6875) 10
required binary fraction. The binary equivalent of 0.125 is
therefore written as 0.0010. Example 14.47 Convert the binary number 101011.1101
Note If a decimal number contains both the integral and the fractional into equivalent decimal number.
part, such as 23.125, then after determining the binary Sol. 101011.1101 = 1 × 25 + 0 × 24 + 1 × 23 + 0 × 22
equivalent of each part separately, the two parts are combined.
Thus, binary equivalent of 23.125 is 10111.0010. + 1 × 21 + 1 × 20 + 1 × 2−1 + 1 × 2−2 + 0 × 2−3 + 1 × 2−4
Example 14.46 Convert the decimal number 10.625 into its = 32 + 0 + 8 + 0 + 2 + 1 + 0.5 + 0.25 + 0 + 0.0625 = 43.8125
binary equivalent. ∴ (101011.1101)2 = (43.8125)10
Sol. Integral part is 10. It can be converted into its binary part
by using divide by 2 rule. 5. Sum of binary numbers
Divide by 2 10 Remainder The sum of digits 0 and 1 with themselves and with each
other are given by the following laws
Divide by 2 5 0
(i) 0 + 0 = 0 (ii) 1 + 0 = 1
Divide by 2 2 1
(iii) 0 + 1 = 1 (iv) 1 + 1 = 10
Divide by 2 1 0 Now, let us take few examples of different types. Through
0 1 these examples, we can easily understand the method of
adding two binary numbers.
Thus, (10)10 = (1010)2
Fractional part is 0.625. It can be converted into its binary Example 14.48 Add the binary numbers 101 and 11.
part by using multiply by 2 rule. Sol. We first write these numbers in columns as below
101
Binary
+11
0.625 × 2 = 1.250 1 1000
0.250 × 2 = 0.500 0 Rule Starting from right, in the first column, we get
1 + 1 = 10. The 0 is written below this column and 1 is carried
0.500 × 2 = 1.000 1
in the next column. In the second column,
0.000 × 2 = 0.000 0 1 + (0 + 1) = 1 + 1 = 10. From the value, 0 is written below this
column and 1 is carried in the third column. Now, in the third
Thus, (0.625)10 = (0.1010)2 column 1 + 1 = 10 is obtained. Thus, 101 + 11 = 1000.
∴ (10.625)10 = (1010.1010)2
Example 14.49 Add the binary numbers 101 and 110. giving 1 to the third column) we carry 1 from the fifth
Sol. Rewriting the numbers in columns as below column. Thus, 10 − 1 = 1 is obtained.
101 Thus, 11011 − 1110 = 1101
+110
10 1 1 LOGIC GATES
The sum is in accordance with the four laws given in the Logic gates are the building blocks of digital circuit that
beginning. Thus, 101 + 110 = 1011. makes use of diodes and transistors to perform switching
Example 14.50 Add the binary numbers 1101 and 1110. function. It is used for performing a particular logical
operation. In other words, a gate is a digital circuit that
Sol. Writing the numbers in columns, we get
1101 follows certain logical relationship between the input and
+1110 output voltages.
11011 A logic gate has one output but one or more inputs. There
Here, in the last column we get1 + (1 + 1) which we wrote 11. are three basic gates named as OR gate, AND gate and
This is because, 1 + (1 + 1) = 1 + 10 ⇒ 1 0 NOT gate.
+1 Each basic logic gate is indicated by a logic symbol and its
11 function is defined and described either by a truth table or
Example 14.51 Add the binary numbers 111, 101 and 110. by a boolean expression.
Sol. For adding more than two binary numbers the above 1. Truth table
method is repeated again and again. If we want to add 111,
101 and 110. First we will add 111 and 101 by the method It is a table that shows all possible input combinations and the
discussed above, then add 110 with the sum of 111 and 101. corresponding output combinations for a logic gate. To
111 understand the concept of truth table, let us take an example.
A bulb is connected to an AC source via two switches S 1
101
and S 2 .
1100
Now, add 1100 and 110
1100 Bulb
+ 110
10010 S1
S2
6. Difference of binary numbers
The four laws of difference (in binary system) are as below Source
(i) 0 − 0 = 0 (ii) 1 − 0 = 1 (iii) 1 − 1 = 0 (iv) 10 − 1 = 1 Fig. 14.61 A bulb is connected via two switches
Now, let us take an example in support of the above four laws. In binary system, we will write 0, if the switch (or bulb) is
Example 14.52 Subtract the binary number 100 from the OFF and write 1 if it is ON. Further, let us write
binary number 101. A for state of switch S 1,
Sol. Let us write the given numbers in columns as below B for state of switch S 2
101 and C for state of the bulb.
−100
Now, let us make a table (called truth table).
001
Thus, 101 − 100 = 001 or simply 1. Switch S1 Switch S2 Bulb A B C
Example 14.53 Subtract the binary number 1110 from the OFF ON OFF 0 1 0
binary number 11011.
ON OFF OFF 1 0 0
Sol. Rewriting the given numbers in columns as below.
OFF OFF OFF 0 0 0
11011
−1110 ON ON ON 1 1 1
1101
Here, A and B represents the input combination and C
In this example, first and second columns were subtracted in
accordance with the four laws given in the starting. In the
represents the output for this particular circuit. This table
third column, for subtracting 1 from 0 we carry 1 from the is called truth table and is used to define or decribe the
fourth column. Thus, 10 − 1 = 1 is obtained. In the fourth function of a particular logic gate. Now, let us discuss one
column, for subtracting 1 from 0 (which remains 0 after example based on this
Example 14.54 Make a truth table corresponding to the (vi) Associative laws
circuit shown in figure. (a) A + (B + C ) = (A + B ) + C
S1
(b) A ⋅ (B ⋅ C ) = (A ⋅ B ) ⋅ C
(vii) Distributive laws
S2
Source (a) A ⋅ (B + C ) = A ⋅ B + A ⋅ C
Bulb (b) (A + B ) ⋅ (A + C ) = A + BC
(viii) Absorption laws
Sol. Here, the two switches can be operated in different (a) A + A ⋅ B = A (b) A ⋅ (A + B ) = A
combinations. Note that the two switches are connected in
parallel. So, if one switch is OFF, the bulb will still glow. We
(c) A ⋅ (A + A ) = A (d) A ⋅ (A + B ) = A ⋅ B
will write 0, if the switch is OFF and write 1 if it is ON. (ix) Boolean identities
Further, A stands for state of switch S1 and B stands for state (a) A + AB = A + B (b) A(A + B ) = AB
of switch S 2 and C for state of bulb. Now, let us make a truth
table based on this. (c) A + BC = (A + B )(A + C )
Switch S1 Switch S2 Bulb A B C Logic system

ON OFF ON 1 0 1 Let us now study the three types of logic gates in detail
OFF ON ON 0 1 1 1. OR gate
OFF OFF OFF 0 0 0 An OR gate has two or more inputs and one output. In this
ON ON ON 1 1 1 gate, if any of the input or all the inputs are 1, then output is 1.
OR operation Consider the circuit given below
2. Boolean expression S1
Boolean algebra is a different kind of algebra in which
S2
only two states of variables (0 and 1) called boolean
variables are allowed. Hence, to describe the functioning
Bulb
of a logic gate in terms of an equation, we use boolean
expression. It is defined as the expression showing the Fig. 14.62 Circuit of OR operation
combination of two boolean variables resulting into a new
boolean variable known as boolean expression. The two switches are connected in parallel, so when S1 or
S 2 is closed, the bulb is ON, i.e. it glows. So, it represents
Some useful postulates and laws of boolean algebra
OR operation.
(i) Boolean postulates
(a) 0 + A = A (b) 1 + A = 1 Boolean expression
(c) 0 ⋅ A = 0 (d) 1⋅ A = A Let the two input of OR gate be A and B respectively and
(e) A + A = 1 its output be Y.
(ii) Identity law Y =A+B
(a) A + A = A (b) A ⋅ A = A Logic symbol
(iii) Negation law A = A A
Y=A+B
B
(iv) De-Morgan’s theorem It states that, the complement Fig. 14.63 Logic symbol of OR gate
of the whole sum is equal to the product of individual
complements and vice-versa. i.e. Truth table
(a) A + B = A ⋅ B (b) A ⋅ B = A + B Input Output
De-Morgan’s theorem also states that, A B Y =A+ B
(a) A + B = A ⋅ B = A ⋅ B 0 0 0
(b) A ⋅ B = A + B = A + B 0 1 1
(v) Commutative laws 1 0 1

(a) A + B = B + A (b) A ⋅ B = B ⋅ A 1 1 1
OR Gate using diodes 2. AND gate

As shown in figure, a two input OR gate can be realised by It has two or more inputs and one output. In AND gate,
using two ideal diodes D 1 and D 2 and a resistor R. The output is 1 only when all the inputs are 1.
negative terminal of the battery is grounded (i.e. it is at zero
volt) and corresponds to the 0 state, and the positive AND operation
terminal (which is at say 5V) corresponds to the 1 state. Consider the circuit given below
S1 S2
A
D1 C Y
1 D2 R
Bulb
+ B
− 5V
Fig. 14.66 Circuit of AND operation
0 Now, the two switches are connected in series. If any
Fig. 14.64 Realisation of OR gate using one switch is open, the current will now flow and hence
two p-n junction diodes bulb will not glow. So, when S1 and S 2 are closed, bulb
is ON, i.e. it glow. So, it represents AND operation.
The following four cases are possible
Boolean expression
(a) When A = 0 and B = 0, both the diodes are connected
to earth (0V). They do not conduct. Output across R is Let the inputs of AND gate be A and B respectively and
zero, i.e.Y = 0. its output be Y.
Y = A ⋅B
(b) When A = 0 and B = 1, D 1 is connected to earth. It
does not conduct and D 2 is connected to 5V, it gets Logic symbol
forward biased and conducts. Voltage drop across D 2 is A
Y=A.B
zero and the full voltage of 5V appears across R, so B
Y = 1. Fig. 14.67 Logic symbol of AND gate
(c) When A = 1and B = 0, D 1 gets forward biased and D 2
(reverse biased) does not conduct. Voltage drop across Truth table
R is again 5V, soY = 1. Input Output
(d) When A = 1and B = 1, both D 1 and D 2 get forward A B Y = A⋅B
biased and conduct current. But D 1 and D 2 are in 0 0 0
parallel. Voltage drop across R is still 5V, soY = 1.
0 1 0
Hence, the circuit shown in figure above satisfies the
1 0 0
truth-table of OR gate.
1 1 1
Input and output waveforms for an OR gate
The output of an OR gate is high when either A or B or both AND gate using diodes
the inputs are high. Therefore, the output waveform Y will As shown in figure, two inputs AND gate can be realised
be as shown in Fig. 14.65. by using two ideal junction diodes D 1 and D 2 . Here the
resistance R is kept permanently connected to the
t1 t2 t3 t5 t6 positive terminal of 5V battery.
t4 A
A
(Input) D1 C Y
1 D2 R
B 5V
(Input) B
5V
Y
(Output) 0
Fig. 14.65 Input and output waveforms of an OR gate Fig. 14.68 Realisation of an AND gate
The following four cases are possible Logic symbol

(a) When A = 0 and B = 0, the input terminals A and B
are earthed (0V). The two diodes get forward biased A
–
Y=A
and conduct current. But both diodes are shorted.
Fig. 14.71 Logic symbol of NOT gate
The pointY also gets earthed through the shorted
diodes, hence outputY = 0.
Truth table
(b) When A = 0 and B = 1, diode D 1 is forward biased
but shorted. Diode D 2 is not forward biased and Input Output
hence does not conduct. Hence, outputY = 0. A Y=A
(c) When A = 1and B = 0, D 1 does not conduct, D 2 is 0 1
forward biased but shorted. Hence, outputY = 0.
1 0
(d) When A = 1and B = 1, both D 1 and D 2 do not
conduct as they are not forward biased. The output NOT gate using transistor
voltage is equal to the battery voltage of 5V. Hence,
Y = 1. As shown in figure, a NOT gate can be obtained by using
an n-p-n transistor.
Hence, the circuit shown in figure above satisfies the
truth table of AND gate.
Input and output waveforms for an AND gate
The output of an AND gate is high when both the inputs are
high, otherwise the output is low. Therefore, the output 5 V = VCC
RC
waveform Y for AND gate will be as shown in Fig 14.69. Y
t1 t2 t3 t5 t6 A B C
1 n-p-n
t4 RB E
A +
(Input) 5V
−
B
(Input) 0
Fig. 14.72 Realisation of NOT gate
Y
(Output)
The base resistor R B and the collector resistance R C are so
Fig. 14.69 Input and output waveforms of an AND gate
chosen that when a voltage of 5V is applied at the base of
the transistor, a large collector current flow, the voltage at
3. NOT gate Y drops and the base-collector junction is forward biased.
It has only one input and one output. The following two cases are possible
It gives an inverted version of its input, i.e. if input is 1, (i) When input A = 0, the base of the transistor is
then output is 0 and vice-versa. earthed, the base-emitter junction is not forward
NOT operation biased and the collector-base junction is reverse
biased.
Consider the circuit given below
Hence, the base current and the collector current are
R
both zero. The transistor is in the cut-off mode. No
S voltage drop occurs across R C .
The voltage atY is 5 V, hence outputY = 1.
Fig. 14.70 Circuit of NOT operation (ii) When input A = 1, the input terminal A is at 5 V,
Here, only one switch is used and it is connected in both emitter and collector are forward biased. A
parallel with bulb. So, when S is open, bulb is ON, i.e. it large collector current flows.
glows. It represents inverted or NOT operation. The transistor is in the saturation mode. The voltage
Boolean expression drop across R C is almost 5 V, hence outputY = 0.
Let the input of NOT gate be A and its output be Y. Thus, the circuit of given figure satisfies the truth
table of a NOT gate.
Y =A
Input and output waveforms for NOT gate 2. NOR gate

The output of a NOT gate is high when the input is low and It has two or more inputs and one output. When a
vice-versa. Therefore, the output waveform Y for NOT gate is NOT operation is applied after OR gate, then it is
as shown in Fig 14.73 called NOR gate.
t1 t2 t3 t4 t5 t6
A
In this gate, if all the inputs are 0, then only output
(Inputs) will be 1, otherwise it is 0. Let the two inputs be A
and B respectively and its output be Y.
Y
(Output) Boolean expression
Y = A +B
Fig. 14.73 Input and output waveforms of NOT gate
Logic symbol
Combination of logic gates A Y ′ = A+B NOT
Various combinations of three basic gates (i.e. OR, AND and OR Y=A+B
B
NOT) give rise to complicated digital circuits. Let us now discuss
a few combinations of these basic gates using their symbols. A
Y=A+B
B
1. NAND gate Fig. 14.76 Logic symbol of NOR gate
It has two or more inputs and one output. This is an AND gate Truth table
followed by a NOT gate. In this gate, if all the inputs are 1,
then output will be 0. Let the two inputs of NAND gate be A Input Output
and B, respectively and its output be Y. A B Y′ = A + B Y =A+ B
Boolean expression 0 0 0 1
Y = A ⋅ B or Y = AB
0 1 1 0
Logic symbol NOT 1 0 1 0
A AND Y=AB
B 1 1 1 0
Y ′ = A.B
A Input and output waveforms of NOR gate
Y=AB
B
Fig. 14.74 Logic symbol of NAND gate The output waveform for NOR gate will be as shown
in Fig. 14.77
Truth table
Input Output t1 t2 t3 t4 t5 t6 t7
A
A B Y′ = A ⋅ B Y = AB (Inputs)
0 0 0 1 B
0 1 0 1
1 0 0 1
Y
1 1 1 0 (Output)
Input and output waveforms for NAND gate Fig. 14.77 Input and output waveforms of NOR gate
The output waveform for NAND gate will be as shown in
Fig. 14.75. 3. XOR gate
t1 t2 t3 t4 t5 t6
A It is also called the exclusive OR function. It is a
(Inputs) function of two logical variables A and B which
B evaluates to 1, if one of two variables is 0 and the
other is 1. The output is zero, if both the variables are
0 or 1.
Y
(Output)
Boolean expression
Fig. 14.75 Input and output waveforms of NAND gate
Y = A ⊕ B = A XOR B orY = A ⊕ B orY = AB + AB
Logic symbol Input and output waveforms of XNOR gate

A
Y = A·B + B·A The output waveform Y for XNOR gate is as shown in
B Fig. 14.81
Fig. 14.78 Logic symbol of XOR gate t1 t2 t3 t4 t5 t6 t7 t8
Truth table A
(Inputs)
Input Output
B
A B A B A⋅B A⋅B A = A⋅B + A⋅B Y
(Output)
0 0 1 1 0 0 0
Fig. 14.81 Input and output waveforms of XNOR gate
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 1 0 0 0 0 0
NAND and NOR gates as digital
building blocks
Input and output waveforms of XOR gate The repeated use of the OR, AND or the NOT gates alone
The output waveform for XOR gate will be as shown in cannot give a different gate. But the repeated use of the
Fig. 14.79. NAND or the NOR gates alone can give all basic gates like
t0 t1 t2 t3 t4 t5 OR, AND and NOT gates. Hence, the NAND and the NOR
gates are also called universal gates. In digital circuits,
A these gates serve as digital building blocks. Now, let us
(Inputs)
derive the basic logic gates one by one from NAND and
B
NOR gates
Y
(Output)
1. Logic gates using NAND gate
Fig. 14.79 Input and output waveforms of XOR gate
Using NAND gate we can realise different gates as follows
4. XNOR gate
It is also called exclusive NOR function. It is a function
NOT gate from NAND gate
of two logical variables A and B which evaluates to 0, if To obtain NOT gate from NAND gate, the two inputs of
one of two variable is 0 and the other is 1. The output is the NAND gate are joined together.
one, if both the variables are 0 or 1. Boolean expression
Boolean expression The boolean expression for a NAND gate is given by
Y = A ⊕ B = A u B or Y = A B + AB Y = A ⋅B
Logic symbol When B = A,

A
Y = A·B = AB + AB Y = A ⋅A
B
=A (Q A ⋅ A = A)
A
B
Y = AB + AB It is the boolean expression for NOT gate.
Fig. 14.80 Logic symbol of XNOR gate Logic symbol
Truth table A Y=A
Input Output Fig. 14.82 Realisation of NOT gate using NAND gate
A B Y = A B + AB Truth table
0 0 1 Input Output
0 1 0 A=B Y =A
1 0 0 0 1
1 1 1 1 0
AND gate from NAND gate Truth table

To obtain AND gate form NAND gate, one NOT gate Input Output
(made from NAND gate) is used. The output of the NAND
A B A B Y =A+ B
gate is given to the input of the NOT gate. The logic
circuit so obtained will work as AND gate. 0 0 1 1 0
Boolean expression 0 1 1 0 1
The output of the NAND gate is given by 1 0 0 1 1
Y ′ = AB
1 1 0 0 1
This output will form the input of the NOT gate.
∴ Final output is given by
2. Logic gates using NOR gate
Y = AB
Using NOR gate we can realise different gates as follows
= A ⋅ B (boolean expression for AND gate)
Logic symbol NOT gate from NOR gate
Y′=AB To obtain NOT gate from NOR gate, two inputs of NOR
A
B
Y = AB gate are joined together.
Fig. 14.83 Realisation of AND gate using NAND gate Boolean expression
Truth table The boolean expression for NOR gate is given by
Y =A+B
A B Y′ Y = AB
0 0 1 0
Putting B = A,Y = A + A = A (Q A + A = A)
0 1 1 0 This is same as boolean expression for NOT gate.
1 0 1 0 Logic symbol
1 1 0 1
A Y=A
OR gate from NAND gate Fig. 14.85 Realisation of NOT gate using NOR gate
To obtain OR gate from NAND gate, two NOT gates are
used. The outputs of two NOT gate (obtain from NAND Truth table
gate) is given to the inputs of the NAND gate. The logic A Y =A
circuit so obtained will work as OR gate. 0 1
Boolean expression 1 0
The boolean expression for a NAND gate having A and B
as its two inputs is AND gate from NOR gate
Y = (A ⋅ B ) To obtain AND gate from NOR gate, two NOT gates (made
=A+B (applying De Morgan’s theorem) from NOR gates) are connected to a NOR gate. The logic
circuit so obtained will work as AND gate.
=A+B (boolean expression for OR gate)
Boolean expression
Logic symbol
The boolean expression for a NOR gate having A and B as
A
A two inputs is given by
Y = (A + B )
Y=A+B
= A ⋅B (applying De Morgan’s theorem)
B
B = A ⋅B (boolean expression for AND gate)
Fig. 14.84 Logic symbol of OR gate obtained from NAND gate
Logic symbol Sol. The output X in terms of the inputs A and B can be written
as
A
A X = A ⋅ (A + B ).
Let us make the truth table corresponding to this function
Y = AB
Truth table
B
Input Output
B
A B A+ B X = A ⋅ (A + B )
Fig. 14.86 Realisation of AND gate using NOR gate
0 0 0 0
Truth table 0 1 1 0
A B A B Y = A⋅B 1 0 1 1
0 0 1 1 0 1 1 1 1
1 0 0 1 0
Example 14.56 Write the truth table for the following circuit.
0 1 1 0 0
Name the equivalent gate that this circuit represents.
1 1 0 0 1
A
Y
B
OR gate from NOR gate Sol. The given combination consists of NOR gate and NOT gate,
To obtain OR gate from NOR gate, we connect NOR gate so equivalent gate is OR gate.
to the NOT gate (made from NOR gate). The logic circuit Truth table
obtained will work as OR gate.
A B Y =A+ B
Boolean expression
0 0 0
The output of the NOR gate is given by Y ′ = A + B
0 1 1
This output of the NOR gate forms the input of the NOT
1 0 1
gate.
∴ The final output is given by 1 1 1
Y =Y ′ = A + B From the truth table, it is clear that the output is 1 only when
atleast one of the inputs is at the high state (i.e. 1).
=A+B (boolean expression for OR gate)
Example 14.57 Let X = A ⋅ BC . Evaluate X for
Logic symbol (i) A = 1, B = 0, C = 1,
Y ′=A + B (ii) A = B = C = 1
A
Y=A+B (iii) and A = B = C = 0.
B
Sol. (i) When A = 1, B = 0 and C = 1
Fig. 14.87 Realisation of OR gate using NOR gate
BC = 0
Truth table ∴ BC = 1 or ABC = 1
A B Y′ Y =A+ B (ii) When A = B = C = 1
0 0 1 0
Then, BC = 1 or BC = 0 ∴ ABC = 0
1 0 0 1 (iii) When A = B = C = 0
Then, BC = 0
0 1 0 1
∴ BC = 1 or ABC = 0
1 1 0 1
Example 14.55 Draw the truth table for the function X of A Example 14.58 Write the truth table for the logical function
and B for the following logic gate. D = (A OR B ) AND B.
Sol. A OR B is a logical function, say it is equal to X, i.e.
A X X = A OR B = A + B
B Now, D = X AND B = X ⋅ B
The corresponding truth table is as under Sol. The circuit can be redrawn as
A B X = A OR B D = (A OR B ) AND B A A
AND
NOT AB
1 0 1 0 B
OR X=AB + BA
0 1 1 1 NOT A
0 0 0 0 BA
AND
B
1 1 1 1 B
The corresponding truth table is shown below

Note The given function can also be written as D = ( A + B ) ⋅ B
A B A B AB BA AB + BA = X
Example 14.59 Write down truth tables for
0 0 1 1 0 0 0
(i) X = A ⋅ B + A ⋅ B (ii) X = (A + B ) + A ⋅ B
0 1 1 0 0 1 1
Sol. (i) The corresponding truth table is as under 1 0 0 1 1 0 1
A B A B A ⋅B A ⋅B X =A ⋅B +A ⋅B 1 1 0 0 0 0 0
0 0 1 1 1 0 1
Example 14.62 Construct truth table for the function X of A
0 1 1 0 0 1 1 and B as shown in the figure.
1 0 0 1 0 0 0 (i)
A
1 1 0 0 0 0 0 X
B
(ii) The corresponding truth table is as under (ii) A
B
A B B A+ B A⋅B A⋅B X = (A + B ) + (A ⋅ B )
X
0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 1 0 1 1 Sol. First write the boolean expression for the figure and then
construct truth table.
1 1 0 1 1 0 1
(i)
Example 14.60 LetY = ABC + BCA + CAB. Find the output A A+B
X = (A) . (A + B)
Y, if following inputs are given B
(i) A = 1, B = 0, C = 1 (ii) A = B = C = 1 A B A+ B X = A ⋅ (A + B )
(iii) A = B = C = 0
0 0 1 0
Sol.
0 1 0 0
A B C AB BC CA A BC BCA C AB Y 1 0 0 0
0 0 0 1 1 1 0 0 0 0 1 1 0 0
1 1 1 0 0 0 0 0 0 0 (ii) A A+B
B
1 0 1 1 1 0 1 0 1 1
X = (A + B) + (A + B)
(i) Y = 1 (ii) Y = 0 (iii) Y = 0
Example 14.61 Write the truth table for the circuit

given in figure. A+B
A A B A B A + B A+ B X = (A + B ) + (A + B )
0 0 1 1 1 1 0
X 0 1 1 0 1 0 0
1 0 0 1 0 1 0
B
1 1 0 0 1 1 0
CHECK POINT 14.4

1. The binary number 10111 is equivalent to the decimal 9. The truth table given below is for
number
A B Y
(a) 19 (b) 31 (c) 23 (d) 22
0 0 1
2. Sum of the two binary numbers (100010)2 and (11011)2 is
0 1 1
(a) (111101)2 (b) (111111)2
(c) (101111)2 (d) (111001)2 1 0 1
3. The output of OR gate is 1 1 1 0
(a) if both inputs are zero
(A and B are the inputs, Y is the output)
(b) if either or both inputs are 1
(a) NOR (b) AND
(c) only if both input are 1 (c) XOR (d) NAND
(d) if either input is zero
10. The boolean equation of NOR gate is
4. If A and B are two inputs in AND gate, then AND gate has (a) Y = A + B (b) Y = A + B
an output of 1 when the values of A and B are
(a) A = 0, B = 0 (b) A = 1, B = 1 (c) Y = A ⋅ B (d) Y = A ⋅ B
(c) A = 1, B = 0 (d) A = 0, B = 1 11. Any digital circuit can be realised by repetitive use of only
5. A gate has the following truth table (a) NOT gates (b) OR gates
(c) AND gates (d) NOR gates
P Q R
12. The logic gates behind NOR gate is that it gives
1 1 1 (a) high output when both the inputs are low
(b) low output when both the inputs are low
1 0 0 (c) high output when both the inputs are high
0 1 0 (d) None of the above
13. The logic gates having output 1 for the inputs of 1 and 0 are
0 0 0
(a) AND and OR (b) OR and NOR
The gate is (c) NAND and NOR (d) NAND and OR
(a) NOR (b) OR 14. If the two inputs of a NAND gate are shorted, the gate is
(c) NAND (d) AND equivalent to
6. If A and B are two inputs in AND gate, then AND gate has (a) XOR (b) OR
(c) NOR (d) NOT
an output of 0 when the value of A and B are
(a) A = 0, B = 0 (b) A = 0, B = 1 15. Which logic gate is represented by the following
(c) A = 1, B = 0 (d) All are correct combination of logic gates?
7. A gate in which all the inputs must be low to get a high
output is called
(a) NAND gate (b) an inverter
(c) NOR gate (d) AND gate Y
8. The output of a NAND gate is 0,
(a) if both inputs are 0
(b) if one input is 0 and the other input is 1
(c) if both inputs are 1
(a) OR (b) NAND
(d) either if both inputs are 1 or if one of the inputs is 1 and (c) AND (d) NOR
the other 0
Chapter Exercises
(A) Taking it together
Assorted questions of the chapter for advanced level practice
1 Number of electrons in the valence shell of a 9 The forbidden energy gap in the energy bands of
semiconductor is germanium at room temperature is about
(a) 1 (b) 2 (c) 3 (d) 4 (a) 1.1 eV (b) 0.1 eV
2 Hole is [NCERT Exemplar]
(c) 0.67 eV (d) 6.7 eV
(a) an anti-particle of electron 10 The energy band gap of Si is
(b) a vacancy created when an electron leaves a covalent (a) 0.70 eV
bond (b) 1.1 eV
(c) absence of free electrons (c) between 0.70 eV to 1.1 eV
(d) an artificially created particle (d) 5 eV
3 A piece of copper and the other of germanium are 11 What enables Ge to behave as semiconductor even
cooled from the room temperature to 80 K, then though all electrons in the valence band form
which of the following would be a correct covalent bonds? It is due to the small width of
statement? (a) valence band (b) conduction band
(a) Resistance of each increases. (c) forbidden energy gap (d) None of these
(b) Resistance of each decreases.
(c) Resistance of copper increases while that of germanium 12 E g for silicon is 1.12 eV and that for germanium is
decreases. 0.72 eV. Therefore, it can be concluded that
(d) Resistance of copper decreases while that of (a) more number of electron-hole pairs will be generated
germanium increases. in silicon than in germanium at room temperature
4 The valence band and conduction band of a solid, (b) less number of electron-hole pairs will be generated in
overlap at low temperature, the solid may be silicon than in germanium at room temperature
(a) a metal (b) a semiconductor (c) equal number of electron-hole pairs will be generated
in both at lower temperatures
(c) an insulator (d) None of these
(d) equal number of electron-hole pairs will be generated
5 In a semiconductor, the separation between in both at higher temperatures
conduction band and valence band is of the order of 13 When the electrical conductivity of a semiconductor
(a) 100 eV (b) 10 eV
is due to the breaking of its covalent bonds, then the
(c) 1 eV (d) zero
semiconductor is said to be
6 In a good conductor, the energy gap between the (a) donor (b) acceptor
conduction band and the valence band is (c) intrinsic (d) extrinsic
(a) infinite (b) wide (c) narrow (d) zero
14 The majority charge carriers in p-type semiconductor
7 In semiconductors, at room temperature the are
(a) valence band is partially empty and the conduction (a) electrons (b) protons
band is partially filled (c) holes (d) neutrons
(b) valence band is completely filled and the conduction
band is partially filled 15 A p-n junction has a thickness of the order of
(c) valence band is completely filled (a) 1 cm (b) 1 mm
(d) conduction band is completely empty (c) 10−6 m (d) 10−12 cm
8 A piece of semiconductor is connected in series in an 16 A p-type semiconductor can be obtained by adding
electric circuit. On increasing the temperature, the (a) arsenic to pure silicon
current in the circuit will (b) gallium to pure silicon
(a) decrease (b) remain unchanged (c) antimony to pure germanium
(c) increase (d) stop flowing (d) phosphorous to pure germanium
17 p-type semiconductor is formed when 26 The symbol given in figure represents

I. As impurity is mixed in Si E C
II. Al impurity is mixed in Si
III. B impurity is mixed in Ge
IV. P impurity is mixed in Ge
B
(a) Both I and III (b) Both I and IV
(c) Both II and III (d) Both II and IV (a) n-p-n transistor (b) p-n-p transistor
(c) forward biased p-n junction diode
18 At room temperature, a p-type semiconductor has (d) reverse biased n-p junction diode
(a) large number of holes and few electrons 27 The part of a transistor which is heavily doped to
(b) large number of free electrons and few holes produce a large number of majority carriers, is
(c) equal number of free electrons and holes (a) base (b) emitter (c) collector (d) None of these
(d) no electrons or holes
28 In comparison to half-wave rectifier, full wave
19 Which of the following statements is not true? rectifier gives lower
(a) The resistance of intrinsic semiconductor decreases (a) efficiency (b) average DC
with increase of temperature. (c) average output voltage (d) None of these
(b) Doping pure Si with trivalent impurities give p-type
semiconductors. 29 Zener diode is used as
(c) The majority carriers in n-type semiconductors are holes. (a) half-wave rectifier (b) full wave rectifier
(d) A p-n junction can act as a semiconductor diode. (c) AC voltage stabiliser (d) DC voltage stabiliser
30 Serious drawback of the semiconductor device is
20 n-type semiconductor is formed
that they
(a) when a germanium crystal is doped with an impurity
(a) cannot be used with high voltage
containing three valence electrons
(b) from pure germanium (b) pollute the environment
(c) from pure silicon (c) are costly
(d) when a germanium crystal are doped with an impurity (d) do not last for long time
containing five valence electrons 31 Least doped region in a transistor is
(a) either emitter or collector
21 An n-type semiconductor is
(b) base
(a) negatively charged
(c) emitter
(b) positively charged
(d) collector
(c) neutral
(d) negatively or positively charged depending upon the 32 Intrinsic semiconductor is electrically neutral.
amount of impurity Extrinsic semiconductor having large number of
current carriers would be
22 Electrical conductivity of intrinsic and p-type
(a) positively charged
semiconductor increases with increase in
(b) negatively charged
(a) pressure (b) volume
(c) positively charged or negatively charged depending
(c) density (d) temperature
upon the type of impurity that has been added
23 The valency of the impurity atom that is to be added (d) electrically neutral
to germanium crystal, so as to make it a n-type 33 When a forward bias is applied to p-n junction,
semiconductor, is then it
(a) 6 (b) 5 (a) raises the potential barrier
(c) 4 (d) 3 (b) reduces the majority carrier current to zero
24 An n-type and a p-type silicon can be obtained by (c) lowers the potential barrier
doping pure silicon with (d) None of the above
(a) sodium and magnesium respectively 34 The conductivity of a semiconductor increases with
(b) phosphorus and boron respectively increase in temperature, because [NCERT Exemplar]
(c) boron and phosphorus respectively (a) number density of free current carries increases
(d) indium and sodium respectively (b) relaxation time increases
(c) both number density of carries and relaxation time
25 The potential barrier for silicon diode is increase
approximately (d) number density of carriers increases, relaxation time
(a) 0.2 V (b) 0.6 V decreases but effect of decrease in relaxation time is
(c) 1.1 V (d) 1.4 V much less than increase in number density
35 The drift current in a p-n junction is 43 In an unbiased p-n junction, holes diffuse from the
(a) from the n-side to the p-side p-region to n-region because
(b) from the p-side to the n-side (a) free electrons in the n-region attract them
(c) from the n-side to the p-side, if the junction is forward (b) they move across the junction by the potential difference
biased and in the opposite direction, if it is reverse (c) hole concentration in p-region is more as compared to
biased n-region
(d) from the p-side to the n-side, if the junction is forward (d) All of the above
biased and in the opposite direction, if it is reverse
biased 44 In a transistor,
(a) both the emitter and the collector are equally doped
36 The diffusion current in a p-n junction is (b) base is more heavily doped than the collector
(a) from the n-side to the p-side (c) collector is more heavily doped than the emitter
(b) from the p-side to the n-side (d) the base is made very thin and is lightly doped
(c) from the n-side to the p-side, if the junction is forward
biased and in the opposite direction, if it is reverse 45 A transistor has three impurity regions. All the three
biased regions have different doping levels. In order of
(d) from the p-side to the n-side, if the junction is forward increasing doping level, the regions are
biased and in the opposite direction, if it is reverse biased (a) emitter, base and collector
(b) collector, base and emitter
37 Diffusion current in a p-n junction is greater than
(c) base, emitter and collector
the drift current in magnitude, (d) base, collector and emitter
(a) if the junction is forward biased
(b) if the junction is reverse biased 46 n-p-n transistor is more useful than a p-n-p transistor
(c) if the junction is unbiased because
(d) None of the above (a) n-p-n transistor offers less resistance to the flow of current
(b) charge carriers in n-p-n move more easily than the
38 In the forward bias arrangement of a p-n junction charge carriers in p-n-p
diode, the (c) p-n-p transistor is very costly compared to an n-p-n
(a) n-end is connected to the positive terminal of the battery transistor
(b) p-end is connected to the positive terminal of the (d) None of the above
battery 47 In case of n-p-n transistor, the collector current is
(c) direction of current is from n-end to p-end in the
diode always less than the emitter current because
(d) p-end is connected to the negative terminal of battery (a) collector side is reverse biased and emitter side forward
biased
39 Potential barrier developed in a junction diode (b) few electrons are lost in the base and only the
opposes remaining ones reach the collector
(a) minority carrier in both regions only (c) collector side is forward biased and emitter side is
(b) majority carrier only reverse biased
(c) electrons in n-region (d) collector being reverse biased attracts less electrons
(d) holes in p-region
48 In a p-n-p transistor with normal bias
40 If n e and v d be the number of electrons and drift (a) only holes cross the collector junction
velocity in a semiconductor. When the temperature (b) only majority carriers cross the collector junction
is increased, (c) the collector junction has a low resistance
(a) n e increases and v d decreases (d) the emitter-base junction is forward biased and the
(b) n e decreases and v d increases collector-base junction is reverse biased
(c) Both n e and v d increases 49 The transistors provide good power amplification
(d) Both n e and v d decreases when they are used in
41 The dominant mechanisms for motion of charge (a) common collector configuration
carriers in forward and reverse biased silicon (b) common emitter configuration
p-n junctions are (c) common base configuration
(a) drift in forward bias, diffusion in reverse bias (d) None of the above
(b) diffusion in forward bias, drift in reverse bias 50 When the p-end of the p-n junction is connected to
(c) diffusion in both forward and reverse bias the negative terminal of the battery and the n-end to
(d) drift in both forward and reverse bias
the positive terminal of the battery, then the
42 In p-n junction, avalanche current flows in circuit p-n junction behaves like
when biasing is (a) a conductor (b) an insulator
(a) forward (b) reverse (c) zero (d) excess (c) a super conductor (d) a semiconductor
51 Select the correct statement. 60 To use a transistor as an amplifier,

(a) In a full wave rectifier, two diodes work alternately. (a) Both junctions are forward biased
(b) In a full wave rectifier, two diodes work simultaneously. (b) Both junctions are reverse biased
(c) The efficiency of full wave and half wave rectifiers is same. (c) the emitter-base junction is forward biased and the
(d) The full wave rectifier is bi-directional. collector-base junction is reverse biased
(d) no biasing voltages are required
52 Temperature coefficient of resistance of
semiconductor is 61 In the case of constants α and β of a transistor
(a) zero (b) constant (c) positive (d) negative (a) α = β (b) β < 1, α > 1 (c) αβ = 1 (d) β > 1, α < 1
53 A semiconducting device is connected in a series 62 The base of transistor is made very thin compared to
circuit with a battery and a resistance. A current is emitter and collector. By doing this, which one of
found to pass through the circuit. If the polarity of the following is achieved?
the battery is reversed, then the current drops to (a) High emitter current (b) Low power gain
almost zero, the device may be (c) Low emitter current (d) High power gain
(a) extrinsic semiconductor (b) intrinsic semiconductor 63 In an n-p-n transistor, the collector current is 10 mA.
(c) p-n junction (d) p-n-p transistor If 90% of the electrons emitted reach the collector,
54 GaAs (with a band gap = 1.5 eV) as an LED can emit then the emitter current will be about
(a) blue light (b) green light (a) 9 mA (b) 11 mA
(c) infrared rays (d) X-rays (c) 1 mA (d) 0.1 mA
55 If no external voltage is applied across p-n junction, 64 In a transistor, α is related to β by the relation
then there would be α +1 α −1
(a) β = (b) β =
(a) no electric field across the junction α α
(b) an electric field pointing from n-type to p-type side α α
across the junction (c) β = (d) β =
1− α α +1
(c) an electric field pointing from p-type to n-type side
across the junction 65 The maximum efficiency of full wave rectifier is
(d) a temporary electric field during formation of (a) 100% (b) 25.20%
p-n junction that would subsequently disappear (c) 40.2% (d) 81.2%
56 Carbon, silicon and germanium have four valence 66 Given below are symbols for some logic gates.
electrons each. These are characterised by valence
and conduction bands separated by energy band gap
respectively equal to (E g ) C , (E g ) Si and (E g ) Ge .
I. II.
Which of the following statement(s) is/are true?
(a) (E g ) Si < (E g )Ge < (E g )C
(b) (E g )C < (E g )Ge < (E g ) Si
(c) (E g )C < (E g ) Si < (E g )Ge III. IV.
(d) (E g )Ge < (E g ) Si < (E g )C
57 When a diode is heavily doped, then The XOR gate and NOR gates respectively are
(a) the Zener voltage will be low (a) I and II (b) II and III
(b) the avalanche voltage will be high (c) III and IV (d) I and IV
(c) the depletion region will be thin 67 In the Boolean algebra, which of the following is not
(d) the leakage current will be low equal to A?
58 For a transistor amplifier, the voltage gain (a) A ⋅ A (b) A + A
(a) remains constant for all frequencies (c) A ⋅ A (d) A + A
(b) is high at high and low frequencies and constant in the 68 In given figure,V0 is the potential barrier across a
middle frequency range
(c) is low at high and low frequencies and constant at mid p-n junction, when no battery is connected across
frequencies the junction [NCERT Exemplar]
(d) None of the above 1
2
59 The electrical circuit used to get smooth DC output 3
from a rectifier circuit is called V0
(a) oscillator (b) filter
(c) amplifier (d) logic gates
(a) 1 and 3 both correspond to forward bias of junction 6 × 10 5 Vm–1 is also found to exist. The height of
(b) 3 corresponds to forward bias of junction and 1 potential barrier is
corresponds to reverse bias of junction
(a) 0.30 V (b) 0.40 V (c) 3 V (d) 4 V
(c) 1 corresponds to forward bias and 3 corresponds to
reverse bias of junction 76 Mobilities of electrons and holes in a sample of
(d) 3 and 1 both correspond to reverse bias of junction intrinsic germanium at room temperature are
69 If a full wave rectifier, circuit is operating in 50 Hz 0.36 m2 / Vs and 0.17 m2 / Vs. The electron and hole
mains, then the fundamental frequency in the ripple densities are each equal to 2.5 × 10 19 m−3 . The
will be electrical conductivity of germanium is
(a) 50 Hz (b) 70.7 Hz (c) 100 Hz (d) 25 Hz (a) 0.47 Sm −1 (b) 5.18 Sm −1
70 With an AC input from 50 Hz power line, the ripple (c) 2.12 Sm −1 (d) 1.09 Sm −1
frequency is 77 In a semiconductor, the concentration of electrons is
(a) 50 Hz in the DC output of half-wave as well as full 8 × 10 14 / cm3 and that of the holes is 5 × 10 12 /cm3 .
wave rectifier
(b) 100 Hz in the DC output of half-wave as well as full The semiconductor is
wave rectifier (a) p-type (b) n-type
(c) 50 Hz in the DC output of half-wave and 100 Hz in DC (c) Intrinsic (d) p-n-p-type
output of full wave rectifier 78 In figure given below, assuming the diodes to be
(d) 100 Hz in the DC output of half-wave and 50 Hz in the ideal [NCERT Exemplar]
DC output of full wave rectifier D1
A R
71 The given symbol represents −10V
A D2
Y
B
B
(a) NAND gate (b) OR gate
(c) AND gate (d) NOR gate (a) D1 is forward biased and D 2 is reverse biased and hence
72 The boolean expression of NOR gate is current flows from A to B
(b) D 2 is forward biased and D1 is reverse biased and hence
(a) Y = A + B (b) Y = A + B no current flows from B to A and vice-versa
(c) Y = A ⋅ B (d) Y = A ⋅ B (c) D1 and D 2 are both forward biased and hence current
flows from A to B
73 The temperature (T ) dependence on resistivity (ρ) of (d) D1 and D 2 are both reverse biased and hence no current
a semiconductor is represented by flows from A to B and vice-versa
ρ ρ 79 An n-p-n transistor circuit is arranged as shown in
figure. It is
(a) (b)
n
O T O T p RL
n Vout
ρ ρ Vin
(c) (d)
(a) a common base amplifier circuit
O T O T (b) a common emitter amplifier circuit
74 Under which of the following conditions, does an (c) a common collector amplifier circuit
avalanche breakdown in a semiconductor diode occur? (d) None of the above
(a) When potential barrier is reduced to zero 80 A Si specimen is made into p-type semiconductor by
(b) When reverse bias exceeds a certain value doping on an average one indium atom per 6 × 10 7
(c) When forward bias exceeds a certain value silicon atoms. If the number density of atoms in Si
(d) When forward current exceeds a certain value
be 6 × 10 28 m−3 , then what is the indium atom per
75 The width of depletion region in a p-n junction diode cm3 ?
is 500 nm and an intense electric field of (a) 1012 (b) 1015 (c) 1018 (d) 1020
81 A 220 V AC supply is connected between points A 87 Which represents NAND gate?

and B (figure). What will be the potential difference
V across the capacitor? [NCERT Exemplar] (a) (b)
A
(c) (d)
200 AC C V
88 What is the current in the circuit shown below?

B _ p-n 300 Ω _
4V 1V
(a) 220V (b) 110 V (c) 0 V (d) 220 2V
82 In the diagram, the input is across the terminals A (a) Zero (b) 10−2 A
(c) 1 A (d) 0.10 A
and C and the output is across B and D. Then, the
output is 89 The diode shown in the circuit is a silicon diode. The
B potential difference between the points A and B will be
2Ω A S B
A C
D
(a) zero (b) same as the input 6V
(c) full wave rectifier (d) half wave rectifier (a) 6 V (b) 0.6 V
83 When forward bias is applied to a p-n junction, then (c) 0.7 V (d) zero
what happens to the potential barrierVB and the 90 The value of DC voltage in half-wave rectifier in
width of charge depleted region x ? converting AC voltageV = 100 sin(314t ) into DC is
(a)VB increases, x decreases (b)VB decreases, x increases (a) 100 V (b) 50 V
(c) VB increases, x increases (d)VB decreases, x decreases (c) 30.3 V (d) 0 V
84 The following truth table corresponds to the logic 91 Below we give four entries for the truth table of two
gate point input OR gate. Which two are wrong?
A
A B X Y
B
0 0 0
0 1 1 A B Y
1 0 1 i 1 0 1
1 1 1 ii 1 1 0
iii 0 0 1
(a) NAND (b) OR iv 0 1 1
(c) AND (d) XOR
(a) i, ii (b) ii, iii (c) iii, iv (d) iv, i
85 The transfer ratio β of a transistor is 50. The input
resistance of the transistor when used in the 92 Input signal to a common emitter amplifier having a
common emitter configuration is 1 k Ω. The peak voltage gain of 1000 is given by
value of the collector AC current for a peak value of Vi = (0.004 V ) sin(ωt + π/2). The corresponding
AC input voltage of 0.01 V is output signal is
(a) 100 µA (b) 0.01 µA (a) (40 V ) sin(ω t + π/2) (b) (0.004 V ) cos(ω t + π/2)
(c) 0.25 µA (d) 500 µA (c) (4 V ) cos(ω t − π/2) (d) (4 V ) sin(ω t − π/2)
86 The voltage gain of an amplifier with 9% negative 93 In a common base transistor circuit, the current gain
feedback is 10. The voltage gain without feedback is 0.98. On changing the emitter current by 5 mA,
will be the change in collector current is
(a) 90 (b) 10 (a) 0.196 mA (b) 2.45 mA
(c) 1.25 (d) 100 (c) 4.9 mA (d) 5.1 mA
94 The forbidden energy gap in Ge is 0.72 eV. Given, 102 Given below are four logic gate symbols (figure).
hc = 12400 eV-Å. The maximum wavelength of Those for OR, NOR and NAND are respectively
radiation that will generate electron-hole pair is A Y A Y
(a) 172220 Å (b) 172.2 Å (c) 17222 Å (d) 1722 Å B B
95 When the emitter current of a transistor is changed (1) (2)
by 1 mA, then its collector current changes by A Y A Y
0.990 mA. In the common base circuit, current gain
B B
for the transistor is
(3) (4)
(a) 0.099 (b) 1.01 (c) 1.001 (d) 0.990
(a) 1, 4, 3 (b) 4, 1, 2 (c) 1, 3, 4 (d) 4, 2, 1
96 What will be the input of A and B for the boolean
103 The decimal equivalent of the binary number
expression (A + B ) ⋅ (A ⋅ B ) = 1?
(11010.101) 2 is
(a) 0, 0 (b) 0, 1 (c) 1, 0 (d) 1, 1 (a) 9.625 (b) 25.265 (c) 26.625 (d) 26.265
97 In a transistor, the current amplification factor α 104 Which of the following gates will have an output
is 0.9. The transistor is connected in common base of 1?
configuration. The change in collector current when
1 0
emitter current changes by 4 mA is (a) (b)
0 1
(a) 4 mA (b) 12 mA (c) 24 mA (d) 3.6 mA
98 For the given circuit of p-n junction diode, which of 0 0
the following statement is correct? (c) (d)
1 1
R
105 When the inputs of two input logic gates are 0 and
0, then the output is 1. When the inputs are 1 and 0,
then the output is zero. The logic gate is of the type
(a) XOR (b) NAND (c) NOR (d) OR
V
106 For the given combination of gates, if the logic states
(a) In forward biasing, the voltage across R is V. of inputs A, B and C are as follows A = B = C = 0
(b) In forward biasing, the voltage across R is 2V.
and A = B = 1, C = 0, then the logic states of output
(c) In reverse biasing, the voltage across R is V.
D are
(d) In reverse biasing, the voltage across R is 2V.
A
99 A p-type semiconductor has acceptor level 57 meV B
above the valence band. The maximum wavelength
D
of light required to create hole is
–3 C
(a) 57 Å (b) 57 × 10 Å
(c) 217100 Å (d) 11.61 × 10–33 Å (a) 0, 0 (b) 0, 1 (c) 1,0 (d) 1, 1
107 The combination of NAND gates shown here are
100 The given truth table is of
equivalent to an
A X
0 1 A
1 0
C
(a) OR gate (b) AND gate
(c) NOT gate (d) None of these B
101 The below truth table corresponds to
A B Y
A C
0 0 1
B
1 0 1
0 1 1
(a) OR gate and an AND gate, respectively
1 1 0
(b) AND gate and a NOT gate, respectively
(a) NAND gate (b) XOR gate (c) AND gate and an OR gate, respectively
(c) OR gate (d) NOR gate (d) OR gate and a NOT gate, respectively
108 The boolean expression for the circuit given in the 114 Which circuit will not show current in ammeter?
figure is
A
Y (a) (b)
B
(a) Y = A + B (b) Y = A + B + – + –
(c) Y = A + B (d) Y = A + B
109 In the circuit given below, the value of the current is
+4V
p-n 300 Ω +1V
(c) (d)
+ – + –
(a) zero (b) 10−2 A (c) 102 A (d) 10−3 A
110 A potential barrier of 0.50 V exists across a p-n 115 In the given figure, which of the diodes are forward
junction.If the depletion region is 5.0 × 10 −7 m wide, biased?
then the intensity of the electric field in this region is +5V R
−1 5 −1
+10V
(a) 1 × 10 Vm6
(b) 1 × 10 Vm R
I. II. III. −5V
(c) 2 × 105 Vm −1 (d) 2 × 106 Vm −1 +5V
111 The output of the given circuit in figure given
below, is [NCERT Exemplar] IV. −12V V.
R R
−5V
−10V
Vm sin ωt (a) I, II, III (b) II, IV, V

(c) I, III, IV (d) II, III, IV
116 The equivalent resistance of the circuit across AB is
given by
2W 4W
(a) would be zero at all times
(b) would be like a half wave rectifier with positive cycles
in output
A 5W B
(c) would be like a half wave rectifier with negative cycles
in output
(d) would be like that of a full wave rectifier
4W 8W
112 In the network shown, (a) 4 Ω (b) 13 Ω
D1 (c) 4 Ω or 13 Ω (d) 4 Ω or zero
4W
117 In the circuit shown in figure given below, if the
D2 diode forward voltage drop is 0.3 V, the voltage
difference between A and B is [NCERT Exemplar]
+ –
5V A
0.2 mA
(a) the potential difference across D 2 is 5 V
(b) current through resistor equals 2.25 A 5 kΩ
(c) current through diode D1 is 1.25 A
(d) current through diode D 2 is 1.25 A
113 The current in the circuit will be
20 W D1
5 kΩ
D2 30 Ω
B
20 W 5V (a) 1.3 V (b) 2.3 V
(c) 0 (d) 0.5 V
(a) (5/40) A (b) (5/50) A (c) (5/10) A (d) (5/20) A
118 Truth table for the given circuit is [NCERT Exemplar] 122 The logic circuit shown below has the input
waveforms A and B as shown. Pick out the correct
A C output waveform.
A
E
Y
B D B
Input A
(a) A B E (b) A B E
0 0 1 0 0 1
0 1 0 0 1 0 Input B
1 0 1 1 0 0
1 1 0 1 1 0
(c) A B E (d) A B E (a)
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0 (b)
119 The input resistance of a common emitter amplifier
is 2kΩ and AC current gain is 20. If the load resistor
used is 5kΩ, then calculate the transconductance of
the transistor used.
(c)
(a) 0.01 Ω −1 (b) 0.03 Ω −1
(c) 0.04 Ω −1 (d) 0.07 Ω −1
(d)
120 In a transistor circuit shown, the base current is
35 µΑ. The value of the resistor R b is
E C 123 A full wave rectifier circuit along with the input and
output voltages is shown in the figure
B D1
Output
Rb RL voltage
D2
+ –
9V Input
voltage
(a) 123.5 kΩ
(b) 257 kΩ
(c) 380.05 kΩ
(d) None of the above Output
voltage
121 A Zener diode, having breakdown voltage equal to A B C D
15 V, is used in a voltage regulator circuit shown in
figure. The current through the diode is The contribution to output voltage from D 2 is
+ +
(a) A, C (b) B, D
250 Ω (c) B, C (d) A, D
20 V 15V 1k Ω 124 A researcher wants an alarm to sound when the

temperature of air in his controlled research chamber
–
– rises above 40°C or falls below 20°C. The alarm can
be triggered by the output of a
(a) 20 mA (b) 5 mA (a) NOT gate (b) AND gate
(c) 10 mA (d) 15 mA (c) NAND gate (d) OR gate
125 The boolean expression for the circuit given in figure 129 The graph given below represents the I -V
is characteristics of a Zener diode. Which part of the
A characteristics curve is most relevant for its
Y
operation as a voltage regulator?
B
I (mA)
C
(a) Y = A ⋅ B + C (b) Y = A ⋅ (B + C ) Reverse bias Forward bias
a
(c) Y = A ⋅ (B + C ) (d) Y = A ⋅ (B + C ) VZ
d c b
V (V)
126 The current through an ideal p-n junction shown in e
the circuit diagram will be Current
p n 100 Ω I (µA)
(a) ab (b) bc (c) cd (d) de

1V 2V 130 A diode having potential difference 0.5 V across its
junction which does not depend on current, is
connected in series with resistance of 20 Ω across
(a) zero (b) 1 mA (c) 10 mA (d) 30 mA source. If 0.1 A passes through resistance, then what
is the voltage of the source?
127 In a forwards biased p-n-junction diode, the potential
(a) 1.5 V (b) 2.0 V (c) 2.5 V (d) 5 V
barrier in the depletion region is of the form
V V 131 If the voltage between the terminals A and B is 17 V
and Zener breakdown voltage is 9 V, then the
potential across R is
(a) (b) A
p n p n R
V V
RL
(c) (d)
B
p n p n (a) 6 V (b) 8 V (c) 9 V (d) 17 V
128 Identify the semiconductor devices whose charact- 132 Assuming the diodes to be of silicon with forward
eristics are given below, in the order I, II, III, IV. resistance zero, the current I in the following circuit
I I
is
I 2 kΩ
I. V II. V
E = 20 V
I Resistance
Dark
(a) zero (b) 9.65 mA (c) 10 mA (d) 10.36 mA
III. V IV. V
133 In the following circuit, the current flowing through
Illunimated
Intensity of 1 k Ω resistor is
light
500 Ω
(a) Zener diode, Simple diode, Light dependent resistance,
Solar cell
(b) Solar cell, Light dependent resistance, Zener diode , 10V 5V 1kΩ
Simple diode
(c) Zener diode, Solar cell, Simple diode, Light dependent
resistance
(d) Simple diode, Zener diode, Solar cell, Light dependent (a) zero (b) 5 mA
resistance (c) 10 mA (d) 15 mA
134 In the given circuit 135 Currents flowing in each of the circuits A and B
D3
5Ω
respectively are
4Ω 4Ω
D1
10 Ω 4Ω 4Ω
20 Ω 5Ω
D2
8V 8V
+ – + –
10 V (Circuit A) (Circuit B)
The current through the battery is
(a) 0.5 A (b) 1 A (c) 1.5 A (d) 2 A (a) 1 A, 2 A (b) 2 A, 1 A
(c) 4 A, 2 A (d) 2 A, 4 A
(B) Medical entrance special format questions

Assertion and reason 5 Assertion The logic gate NOT cannot be built using
diode.
Directions (Q. Nos. 1-5) These questions consists of two
Reason The output voltage and the input voltage of
statements each printed as Assertion and Reason. While
answering these questions you are required to choose any the diode have 180° phase difference.
one of the following four responses.
(a) If both Assertion and Reason are correct and Reason is the Statement based questions
correct explanation of Assertion.
(b) If both Assertion and Reason are correct but Reason is not 1 For transistor action, which of the following
the correct explanation of Assertion. statements are correct?
(c) If Assertion is true but Reason is false. (a) Base, emitter and collector regions should have similar
(d) If Assertion is false but Reason is true. size and doping concentrations.
(b) The base region must be very thick and moderately
1 Assertion If the temperature of a semiconductor is doped.
increased, then its resistance decreases. (c) The emitter junction is forward biased and collector
Reason The energy gap between conduction band junction is reverse biased.
(d) Both the emitter junction as well as the collector
and valence band is very small.
junction are forward biased.
2 Assertion The number of electrons in a p-type silicon
2 In an n-type silicon, which of the following
semiconductor is less than the number of electrons in a
statement is true?
pure silicon semiconductor at room temperature.
(a) Electrons are majority carriers and trivalent atoms are
Reason It is due to law of mass action. the dopants.
3 Assertion When p-n junction is forward biased, (b) Electrons are minority carriers and pentavalent atoms
are the dopants.
then motion of charge carriers at junction is due to
(c) Holes are minority carriers and pentavalent atoms are
diffusion. In reverse biasing, the cause of motion of the dopants.
charge is drifting. (d) Holes are majority carriers and trivalent atoms are the
+1 V dopants.
C 3 I. The resistivity of a semiconductor increases with

0V
B temperature.
E II. The atoms of a semiconductor vibrate with larger
amplitudes at higher temperatures thereby
–2 V increasing its resistivity.
Reason In the following circuit, emitter is reverse Choose the correct statement from the given options.
biased and collector is forward biased. (a) Only I (b) Only II
4 Assertion NAND or NOR gates are called digital (c) Both I and II (d) None of these
building blocks. 4 I. A rectifier converts an alternating current into a
Reason The repeated use of NAND (or NOR) gates direct current.
can produce all the basic or complicated gates. II. A p-n junction diode can work as a rectifier.
III. Zener diode works on a principle of breakdown Column I Column II

voltage.
IV. Current increases suddenly after breakdown voltage.
(B) (q) Zener diode
Which one of the following is correct?
(a) I, II and IV (b) Both I and IV
(c) I, III and IV (d) All of these
(C) (r) Photodiode
5 Read the following statements about transistor and
choose the correct statements(s).
I. A transistor amplifier in common emitter
(D) (s) Solar cells
configuration has a low input impedance. + –
II. The base to emitter region is forward biased.
(a) Only I (b) Only II Codes
(c) Both I and II (d) None of these A B C D A B C D
(a) p r s q (b) q r p s
Match the columns (c) q p r s (d) q r s p
3 Match the boolean expression of gate given in
1 In the circuit shown, the barrier voltage of diode is
0.7 V. Match the physical quantities given in Column I to the gate given in Column II and mark
Column I to the results given in Column II and mark the correct option from the codes given below.
the correct option from the codes given below.
Column I Column II
RF = 10 Ω
(A) Y=A+ B (p) NAND gate
RL 500 Ω (B) Y = A⋅B (q) NOT gate
~ (C) Y=A (r) AND gate

20 V (Peak)
(D) Y = A⋅B (s) OR gate
Column I Column II
(A) Peak current (in mA) in diode (p) 37.8 Codes
A B C D A B C D
(B) Peak voltage (in volts) at the ends of (q) 40.0
(a) s r p q (b) s r q p
load
(c) s q p r (d) q p r s
(C) Peak current (in mA), if diode is ideal (r) 20.0
4 Match the symbol of gate given in Column I to the
(D) Peak voltage (in volts) at the ends of (s) 18.9
gate given in Column II and mark the correct option
load, if diode is ideal
from the codes given below.
(t) Zero
Column I Column II
Codes A
A B C D (A) B
Y (p) NOT
(a) p q s r
(b) q r p r (B) A Y (q) OR
(c) p r s q
(d) p s q r A
(C) B
Y (r) NAND
2 Match the symbol of diode given in Column I to the
result given in Column II and mark the correct A
(D) Y (s) NOR
option from the codes given below. B
Column I Column II Codes

A B C D A B C D
(A) (p) Light emitting diode (a) r p q s (b) r q p s
(c) s p r q (d) s p q r
(C) Medical entrances’ gallery

Collection of questions asked in NEET and various medical entrance exams
1 Out of the following, which one is a forward biased 8 For a p-type semiconductor, which of the following
diode? [NEET 2020] statements is true ? [NEET 2019]
(a) – 4 V –2 V (a) Holes are the majority carriers and trivalent atoms are
the dopants.
(b) 2 V 5V
(b) Holes are the majority carriers and pentavalent atoms
are the dopants.
(c) Electrons are the majority carriers and pentavalent
(c) –2 V +2 V atoms are the dopants.
(d) Electrons are the majority carriers and trivalent atoms
(d) 0 V –3 V are the dopants.
2 A n-p-n transistor is connected in common emitter 9 An LED is constructed from a p-n junction diode
using GaAsP and the energy gap is 1.9 eV. The
configuration (see figure) in which collector voltage
wavelength of the light emitted will be equal to
drop across load resistance 800 Ω connected to the [NEET (Odisha) 2019]
collector circuit is 0.8 V. The collector current is (a) 10.4 × 10−26 m (b) 654 nm
[NEET 2020]
(c) 654 Å (d) 654 × 10−11 m
800 Ω
RB
IC 10 The correct boolean operation represented by the
8V circuit diagram drawn is [NEET 2019]
IB +6 V
R
0
(a) 2 mA (b) 0.1 mA (c) 1 mA (d) 0.2 mA LED
A 1 (Y)
3 Which of the following gate is called universal gate? R
[NEET 2020]
0
(a) OR gate (b) AND gate (c) NAND gate(d) NOT gate
B 1
4 An intrinsic semiconductor is converted into n-type
extrinsic semiconductor by doping it with [NEET 2020] (a) OR (b) NAND (c) NOR (d) AND
(a) phosphorous (b) aluminium 11 The circuit diagram shown here corresponds to the
(c) silver (d) germanium logic gate [NEET (Odisha) 2019]
5 The increase in the width of the depletion region in +6V
a p-n junction diode is due to [NEET 2020]
A 0 R
(a) reverse bias only 1
(b) both forward bias and reverse bias B 0
(c) increase in forward current 1
LED (Y)
(d) forward bias only
6 The solids which have the negative temperature R
coefficient of resistance are [NEET 2020]
(a) insulator only (a) NOR (b) AND (c) OR (d) NAND
(b) semiconductors only
12 If voltage across a zener diode is 6V, then find out
(c) insulators and semiconductors
the value of maximum resistance in this condition.
(d) metals [AIIMS 2019]
1 kΩ i = 6 mA
7 For transistor action, which of the following
statements is correct? [NEET 2020]
– +
(a) Base, emitter and collector regions should have same
size. Vz = 6 V
R
(b) Both emitter junction as well as the collector junction
are forward biased.
(c) The base region must be very thin and lightly doped. 30 V
(d) Base, emitter and collector regions should have same (a) 2 kΩ (b) 2 kΩ (c) 5 kΩ (d) 4 kΩ
dopping concentrations.
13 Assertion Photodiode and solar cell works on same (a) IB = 20 µA, IC = 5 mA and β = 250
mechanism. (b) IB = 25 µA, IC = 5 mA and β = 200
Reason Area is large for solar cell. [AIIMS 2019] (c) IB = 40 µA, IC = 10 mA and β = 250
(a) Both Assertion and Reason are correct and Reason is the (d) IB = 40 µA, IC = 5 mA and β = 125
correct explanation of Assertion. 19 In the combination of the following gates, the output
(b) Both Assertion and Reason are correct but Reason is not Y can be written in terms of inputs A and B as
the correct explanation of Assertion. A
(c) Assertion is correct but Reason is incorrect. B
(d) Both Assertion and Reason are incorrect. Y
14 The given transistor operates in saturation region,
[NEET 2018]
then what should be the value ofVBB ?
(a) A ⋅ B + A ⋅ B (b) A ⋅ B + A ⋅ B
(Take, R out = 200 Ω, R in =100 kΩ,VCC =3 V,
VBE = 0.7 V,VCE = 0 V and β = 200) [AIIMS 2019] (c) A ⋅ B (d) A + B
Rin
p
n 20 The diode used at a constant potential drop of
n Rout 0.5 V at all currents and maximum power rating of
+ 100 mW. What resistance must be connected in
VBB
– IE + series to diode, so that current in circuit is
– VCC maximum? [AIIMS 2018]
R
(a) 4.1 V (b) 7.5 V (c) 8.2 V (d) 6.8 V
15 For CE configuration n-p-n transistor, which of the I
following statement is correct? [JIPMER 2019]
(a) IC = IE + IB (b) IB = IE + IC 1.5 V
(c) IE = IC + IB (d) All of these
(a) 200 Ω (b) 6.67 Ω (c) 5 Ω (d) 15 Ω
16 Following circuit will act as [JIPMER 2019]
21 Which one of the following represents forward bias
A
A′ diode? [NEET 2017]
0V R −2 V − 2V R +2 V
(a) (c)
Y R −3 V
(b) − 4V 3V 5V
Y′ R
(d)
B
B′ 22 In a common emitter transistor amplifier, the audio
(a) NOR gate (b) NAND gate (c) AND gate (d) OR gate signal voltage across the collector is 3 V. The
resistance of collector is 3 kΩ. If current gain is 100
17 In a p-n junction diode, change in temperature due to and the base resistance is 2 kΩ, the voltage and
heating [NEET 2018] power gain of the amplifier is [NEET 2017]
(a) does not affect resistance of p-n junction (a) 200 and 1000 (b) 15 and 200
(b) affects only forward resistance (c) 150 and 15000 (d) 20 and 2000
(c) affects only reverse resistance
(d) affects the overallV-I characteristics of p-n junction 23 The given electrical network is equivalent to
[NEET 2017]
18 In the circuit shown in the figure, the input voltage A Y
Vi is 20 V,VBE = 0 andVCE = 0. The values of I B , I C B
and β are given by [NEET 2018]

(a) AND gate (b) OR gate (c) NOR gate (d) NOT gate
20 V 24 A specimen of silicon is to be made p-type
semiconductor, for this one atom of indium, on an
RC 4 kW
average, is doped in 5 × 10 7 silicon atoms. If the
RB
C number density of silicon is 5 × 10 28 atom/m 3 , then
Vi
500 kW B
the number of acceptor atoms per cm3 will be
E [AIIMS 2017]
30 13
(a) 2 . 5 × 10 (b) 1.0 × 10
(c) 1.0 × 1015 (d) 2.5 × 1036
25 The current gain of a transistor in common emitter 31 The given circuit has two ideal diodes connected as
mode is 49. The change in collector current and shown in the figure below. The current flowing
emitter current corresponding to change in base through the resistance R 1 will be [NEET 2016]
current by 5.0 µA, will be [AIIMS 2017] R1 = 2 Ω
(a) 245 µA and 250 µA
(b) 240 µA and 235 µA
(c) 260 µA and 255 µA D1 D2
(d) None of the above 10 V
R2 = 3 Ω R3 = 2 Ω
26 A proper combination of 3 NOT and 1NAND gates is
shown in figure. If A = 0, B = 1, C = 1, then the
output of this combination is [AIIMS 2017] (a) 2.5 A (b) 10.0 A
(c) 1.43 A (d) 3.13 A
A
32 What is the outputY in the following circuit, when
B all the three inputs A, B, C are first 0 an then 1 ?
C A P
B Q Y
(a) 1 (b) 0 C
(c) Not predictable (d) None of these
(a) 0, 1 (b) 0, 0 [NEET 2016]
27 To get output 1 for the following circuit, the correct (c) 1, 0 (d) 1, 1
choice for the input is [NEET 2016] 33 The boolean expression P + PQ, where P and Q are
A the inputs of the logic circuit, represents [AIIMS 2015]
B Y
(a) AND gate (b) NAND gate
C (c) NOT gate (d) OR gate
(a) A = 0, B = 0, C = 0 (b) A = 1, B = 1, C = 0 34 A semiconductor is having electron and hole
(c) A = 1, B = 0, C = 1 (d) A = 0, B = 1, C = 0 mobilities µ n and µ p , respectively.
28 Consider the junction diode as ideal. The value of If its intrinsic carrier density is n i , then what will be
current flowing through AB is [NEET 2016]
the value of hole concentration P for which the
conductivity will be minimum at a given
A 1kΩ B temperature? [AIIMS 2015]
+4V - 6V µn µn µp µp
(a) n i (b) n h (c) n i (d) n h
(a) 10−2 A (b) 10−1 A µp µp µn µn
(c) 10−3 A (d) 0 A
35 When an input signal 1 is applied to a NOT gate,
29 A n-p-n transistor is connected in common emitter then its output is [UK PMT 2015]
configuration in a given amplifier. A load resistance (a) 1 (b) 0
of 800 Ω is connected in the collector circuit and the (c) either 0 or 1 (d) any positive value
voltage drop across it is 0.8V. If the current
amplification factor is 0.96 and the input resistance 36 The impurity atoms with which pure silicon may be
of the circuits is 192 Ω, then the voltage gain and the doped to make it a p-type semiconductor are those of
[UK PMT 2015]
power gain of the amplifier will respectively be (a) phosphorous (b) antimony
[NEET 2016]
(a) 3.69, 3.84 (b) 4, 4 (c) boron (d) iron
(c) 4, 3.69 (d) 4, 3.84 37 Let n p and n e be the number of holes and
conduction electrons respectively, in an intrinsic
30 For CE transistor amplifier, the audio signal voltage
semiconductor, then [UK PMT 2015]
across the collector resistance of 2 k Ω is 4V. If the
(a) n p > n e (b) n p = n e
current amplification factor of the transistor is 100
(c) n p < n e (d) None of these
and the base resistance is 1 kΩ, then the input signal
voltage is [NEET 2016] 38 Zener diode is used for [UK PMT 2015]
(a) 10 mV (b) 20 mV (a) rectification (b) amplification
(c) 30 mV (d) 15 mV (c) filtration (d) stabilisation
39 In a transistor, the value of β is 100, then the value 48 The p-type semiconductor is [UP CPMT 2015]
of α will be [UK PMT 2015] (a) positively charged
(a) 0.01 (b) 0.1 (c) 0.99 (d) 1 (b) negatively charged
(c) electrically neutral
40 The arrangement shown in figure performs the logic (d) uncharged at 0 K or − 273 ° C but charged at
function of [UK PMT 2015] temperature higher than 0 K
A
Y 49 The current gain of a transistor in common base
B
(a) AND gate (b) NAND gate configuration is 0.96. Corresponding to the change in
(c) OR gate (d) XOR gate emitter current is 10 mA, the change in base current
would be [UP CPMT 2015]
41 A change of 0.04 V takes place between the base and
(a) 0.03 mA (b) 0.2 mA
the emitter when an input signal is connected to the (c) 0.4 mA (d) 0.6 mA
CE transistor amplifier. As a result, 20 µA change
take place in the base current and a change of 2mA 50 The following logic gate circuit in equivalent to an
[UP CPMT 2015]
takes place in the collector current. Find the input
resistance and AC current gain. [Guj. CET 2015] OR
A
AND
(a) 1 k Ω, 100 (b) 2 k Ω, 100 B G1
(c) 2 k Ω, 200 (d) 1 k Ω, 200 NAND Y(output)
42 In a common emitter transistor amplifier, the voltage G3

G2
gain is [UK PMT 2015]
R AC R in R AC R in (a) NAND (b) OR
(a) α (b) α (c) β (d) β
R in R AC R in R AC (c) XOR (d) NOT
43 In a n-p-n transistor about 10 10 electrons enter the 51 A common emitter amplifier is designed with
emitter in 2µs, when it is connected to a battery. n-p-n transistor (α = 0.99). The input impedence is
Then, I E =K µA. [Guj. CET 2015] 1kΩ and load is 10 kΩ. The voltage gain will be
[Manipal 2015]
(a) 400 (b) 200 (c) 800 (d) 1600
(a) 9900 (b) 99
44 Which gate can be obtained by shorting both the (c) 9.9 (d) 990
input terminals of a NOR gate? [Guj. CET 2015]
52 Assume that, each diode as shown in the figure has a
(a) NOT (b) OR (c) AND (d) NAND forward bias resistance of 50 Ω and an infinite
45 An LED is constructed from a p-n junction based on reverse bias resistance. The current through the
a certain semi-conducting material whose energy gap resistance 150 Ω is [WB JEE 2015]
is 1.9 eV. Then, the wavelength of the emitted light 50 Ω
is [KCET 2015]
(a) 6.5 × 10−7 m (b) 2.9 × 10−9 m 100 Ω
(c) 9.1 × 10−5 m (d) 1.6 × 10−8 m
10 V 150 Ω
46 The equivalent circuit is + –
NOR NAND NOT
A
Y (a) 0.66 A (b) 0.05 A
B
(c) zero (d) 0.04 A
The circuit represents [Manipal 2015]
53 The input characteristics of a transistor in CE mode
(a) NAND gate (b) OR gate is the graph obtained by plotting [KCET 2015]
(c) AND gate (d) NOR gate
(a) IB against IC at constantVCE
47 The inputs to the digital circuit are as shown below. (b) IB againstVBE at constantVCE
The outputY is [WB JEE 2015] (c) IB against IC at constantVBE
A (d) IB againstVCE at constantVBE
B
Y
54 In a semiconducting material, the mobilities of
electrons and holes are µ e and µ h , respectively.
C
Which of the following is true? [Manipal 2015]
(a) µ e < µ h (b) µ e = µ h
(a) A + B + C (b) (A + B ) C
(c) µ e < 0, µ h > 0 (d) µ e > µ h
(c) A + B + C (d) A + B + C
55 If in a p-n junction, a square input signal of 10 V is 60 The combination of gates shown below yields is
applied as shown, [UK PMT 2014]
+5 V A
RL
Y
–5 V B
then the output across R L will be [CG PMT 2015]
(a) NAND gate (b) NOR gate
10 V (c) XOR gate (d) OR gate
(a) (b)
−10 V 61 In insulators (CB is Conduction Band and VB is
Valence Band) [MHT CET 2014]
(c) −5 V (d) 5 V (a) VB is partially filled with electrons
(b) CB is partially filled with electrons
56 The circuit has two oppositely connected ideal (c) CB is empty and VB is filled with electrons
diodes in parallel. What is the current flowing in the (d) CB is filled with electrons and VB is empty
circuit? [KCET 2015]
2ΩD 2
62 Identify the wrong statement. [Kerala CEE 2014]
D1 (a) In conductors, the valence and conduction bands
3Ω
overlap.
(b) Substances with energy gap of the order of 10 eV are
+ –
insulators.
4Ω (c) The resistivity of semiconductors is lower than metals.
12 V
(d) The conductivity of metals is high.
(a) 2.31 A (b) 1.71 A (c) 1.33 A (d) 2 A
63 If the band gap between valence band and
57 The conductivity in the intrinsic semiconductor does
conduction band in a material is 5.0 eV, then the
not depend on [CG PMT 2015]
material is [WB JEE 2014]
(a) band gap (b) temperature
(a) semiconductor (b) good conductor
(c) fermi energy (d) effective mass of charge carriers
(c) superconductor (d) insulator
58 The barrier potential of a p -n junction depends on
64 In n-type semiconductor, electrons are majority
I. type of semiconductor material charge carriers but it does not show any negative
II. amount of doping charge. The reason is [KCET 2014]
III. temperature (a) electrons are stationary
Which one of the following is correct? (b) electrons neutralise with holes
[CBSE AIPMT 2014] (c) mobility of electrons is extremely small
(a) Both I and II (b) Only II (d) atom is electrically neutral
(c) Both II and III (d) All of these
65 Identify the wrong statement with reference to solar
59 The given graph representsV-I characteristic for a cell. [Kerala CEE 2014]
semiconductor device. [CBSE AIPMT 2014] (a) It is a p-n junction diode with no external bias.
(b) It uses materials of high optical absorption.
(c) It uses materials with band gap of 5 eV.
I (d) It converts light energy into electrical energy.
A
V 66 In the circuit shown below, assume the diode to be
ideal. WhenVi increases from 2 V to 6 V, then the
B change in the current is (in mA) [WB JEE 2014]
Vi 150 Ω +3 V
Which of the following statement is correct?
(a) It isV-I characteristic for solar cell, where point A (a) zero (b) 20
represents open circuit voltage and point B short circuit (c) 80/3 (d) 40
current
(b) It is for a solar cell and points A and B represent open 67 Zener diode is used for
[UK PMT 2014, Haryana PMT, CG PMT 2010]
circuit voltage and current, respectively
(a) amplification
(c) It is for a photodiode and points A and B represent open
(b) rectification
circuit voltage and current, respectively
(c) voltage regulation
(d) It is for a LED and points A and B represents open
circuit voltage and short circuit current, respectively (d) produce oscillation in an oscillator
68 In common base circuit of a transistor, current 76 Of the diodes shown in the following diagrams,
amplification factor is 0.95. Calculate the emitter which one is reverse biased? [UK PMT 2014 ]
current, if base current is 0.2 mA. [MHT CET 2014]
(a) 2 mA (b) 4 mA − 12 V
R R
(c) 6 mA (d) 8 mA (a) (b)
69 A tuned amplifier circuit is used to generate a −5V − 10 V
carrier frequency of 2 MHz for the amplitude +5 V
+ 10 V
modulation. The value of LC is [KCET 2014]
R
1 1 1 1 (c) (b)
(a) (b) (c) (d) +5V R
2π × 106 2 × 106 3π × 10 6
4π × 106
70 If α (current gain) of transistor is 0.98, then what is
the value of β (current gain) of the transistor? 77 The truth tables of logic gates G1, G 2, G 3 and G 4 are
[KCET 2014] given here. Identify them correctly. [EAMCET 2014]
(a) 0.49 (b) 49
(c) 4.9 (d) 5 G1 G2
71 In a transistor output characteristics commonly used Inputs Output Inputs Output
in common emitter configuration, the base current A B Y A B Y
I B , the collector current I C and the collector-emitter 0 0 0 0 0 0
voltage VCE have values of the following orders of
0 1 1 0 1 0
magnitude in the active region [WB JEE 2014]
1 0 1 1 0 0
(a) IB and IC both are in µ A andVCE in V
1 1 1 1 1 1
(b) IB is in µA, IC is in mA andVCE in V
(c) IB is in mA, IC is in µA andVCE in mV G3 G4
(d) IB is in mA, IC is in mA andVCE in mV Inputs Output Inputs Output
72 For the action of a Common Base (CB) transistor A B Y A B Y
(E = emitter, B = base, C = collector), the required
0 0 1 0 0 1
CB, EB junction bias conditions are [EAMCET 2014]
0 1 0 0 1 1
(a) Both EB and CB junction forward bias 1 0 0 1 0 1
(b) Both EB and CB junction reverse bias 1 1 0 1 1 0
(c) EB junction forward bias, CB junction reverse bias
(d) EB junction reverse bias, CB junction forward bias (a) G1-OR, G 2 -AND, G 3 -NOR, G 4 -NAND
(b) G1-OR, G 2 -NOR, G 3 -AND, G 4 -NAND
73 The minimum number of NAND gates used to
construct an OR gate is [Kerala CEE 2014] (c) G1-AND, G 2 -OR, G 3 -NAND, G 4 -NOR
(a) 4 (b) 6 (c) 5 (d) 3 (d) G1-OR, G 2 -NOR, G 3 -NAND, G 4 -AND
(e) 2 78 In a n-type semiconductor, which of the following
statement is true? [NEET 2013]
74 The outputY of the logic circuit given below is
[J&K CET 2014] (a) Electrons are majority carriers and trivalent atoms are
dopants.
Y (b) Electrons are minority carriers and pentavalent atoms
A
are dopants.
(c) Holes are minority carriers and pentavalent atoms are
B dopants.
(d) Holes are majority carriers and trivalent atoms are dopants.
(a) A + B (b) A (c) (A + B ) ⋅ A (d) (A + B ) ⋅ A
79 In a common emitter (CE) amplifier having a voltage
75 For the given digital circuit, identify the logic gate. gain G, the transistor used has transconductance
0.03 mho and current gain 25. If the above transistor
A is replaced with another one with transconductance
Y 0.02 mho and current gain 20, then the voltage gain
will become [NEET 2013]
B
[KCET 2014] 2 1 5
(a) G (b) 1.5 G (c) G (d) G
(a) OR gate (b) NOR gate (c) NAND gate (d) AND gate 3 3 4
80 The output X of the logic circuit shown in figure 88 The depletion layer in the p-n junction region is
will be caused by [UP CPMT 2013]
A
X
(a) drift of holes
B (b) drift of electrons
[NEET 2013]
(c) diffusion of carriers
(a) X = A ⋅ B (b) X = A ⋅ B (d) migration of impurity ions
(c) X = A ⋅ B (d) X = A + B 89 Out of the following curves, which one represents a
81 The output of an AND gate is connected to both the digital signal? [UP CPMT 2013]
inputs of a NOR gate, then this circuit will act as a
[Kerala CET 2013] v v
(a) (0,0) (b) (0,0)
(a) OR gate (b) NOR gate
t t
(c) AND gate (d) NAND gate
(e) NOT gate
82 The necessary condition in making of a junction v v
(c) (0,0) (d) (0,0)
transistor (E-emitter, B-base and C-collector) t t
[EAMCET 2013]
(a) E and B are lightly doped and C is heavily doped
(b) E is heavily doped, B is thin and lightly doped and C is 90 The circuit has two oppositely connected ideal
moderately doped diodes in parallel as shown in figure. What is the
(c) E and C are lightly doped and B is thick and heavily current flowing in the circuit ? [UP CPMT 2013]
doped
4Ω
(d) E and B are heavily doped and C is lightly doped
83 A p-n-p transistor is used in common emitter mode D1 D2
in an amplifier circuit. When base current is 12 V
changed by an amount ∆I B , then the collector 3Ω 2Ω
current changes by 4 mA. If the current
amplification factor is 60, then the value of ∆I B is (a) 1.33 A (b) 1.71 A
[EAMCET 2013]
(c) 2.00 A (d) 2.31 A
(a) 15 µA (b) 240 mA (c) 66.6 µA (d) 60 µA
91 Transfer characteristic [output voltage (Vo ) versus
84 In p-type semiconductor, the acceptor level lies
[Kerala CET 2013] input voltage (Vi )] for a base biased transistor in CE
(a) near the conduction band configuration is as shown in the figure. For using
(b) halfway between conduction and valence bands transistor as a switch, it is used
(c) within conduction band [CBSE AIPMT (Screening) 2012; BCECE 2012]
(d) near the valence band I II III
(e) within the valence band Vo
85 If the feedback voltage is increased in a negative
feedback amplifier, then [Kerala CET 2013]
(a) both gain and distortion decrease
(b) the distortion increase Vi
(c) the gain decrease and distortion increase (a) Only in region III (b) Both in regions I and III
(d) the gain increase (c) Only in region II (d) Only in region I
(e) both gain and distortion increase 92 Find the current in the circuit.
86 When a p-n junction is reverse biased, then the current [CBSE AIPMT (Screening) 2012]
through the junction is mainly due to [MP PMT 2013] D1 10 Ω
(a) Only diffusion of charges
(b) Only drift of charges D2 20 Ω
(c) Both drift and diffusion of charges
(d) Neither drift nor diffusion of charges 5V
87 What is the value of A + A in the Boolean algebra?
[UP CPMT 2013] (a) 0.75 A (b) Zero
(a) A (b) 0 (c) 1 (d) A (c) 0.25 A (d) 0.5 A
93 In a CE transistor amplifier, the audio signal voltage (a) 0.04 mA (b) 0.03 mA
across the collector resistance of 2 kΩ is 2V. If the (c) 0.02 mA (d) 0.01 mA
base resistance is 1kΩ and the current amplification 98 In a transistor circuit shown in figure, if the base
of the transistor is 100, then the input signal voltage current is 35 µA, then the value of resistor R b is
is [CBSE AIPMT (Screening) 2012] [BCECE (Mains) 2012]
(a) 0.1 V (b) 1.0 V (c) 1 mV (d) 10 mV E C
94 The figure shows a logic circuit with two inputs A

B
and B and the output C . The voltage waveforms RL
across A, B and C are as given. The logic circuit gate Rb
is [CBSE AIPMT (Screening) 2012] + –

9V
(a) 257 kΩ (b) 123.5 kΩ

A (c) 380.05 kΩ (d) None of these
99 In intrinsic semiconductor, at room temperature
number of electrons and holes are [Manipal 2012]
B
(a) equal (b) zero
(c) unequal (d) infinite
C 100 Which of the following is not a rectifier circuit?
t1 t2 t3 t4 t5 t6 [AMU 2012]
(a) OR gate (b) NOR gate
(c) AND gate (d) NAND gate (a) RL (b) RL
95 A diode is connected to 220 V (rms) AC in series

with a capacitor as shown in figure. The voltage
across the capacitor is [JCECE 2012]
(c) (d)
D RL RL
220 V C
AC
101 The following network of gates [AMU 2012]
A
Y
(a) 220 V (b) 110 V B
220
(c) 311.1 V (d) V
2 is equivalent to
96 Which one of the following statements is not correct A
(a) Y
in case of a semiconductor? [BCECE (Mains) 2012] B
(a) Temperature coefficient of resistance is negative. A
(b) Doping increases conductivity. (b) Y
B
(c) At absolute zero temperature, it behaves like an insulator.
(d) Resistivity is in between that of a conductor and insulator. A
(c) Y
B
97 If for the following common emitter circuit, β =100,
VCE = 7 V,VBE is negligible and R C = 2 kΩ, then iB = ? (d) A Y
iB iC
RC 102 If a small amount of antimony is added to
15 V
RB
C
germanium crystal, [CBSE AIPMT 2011]
(a) the antimony becomes an acceptor atom
B (b) there will be more free electrons than holes in the
E semiconductor
(c) its resistance is increased
[BCECE (Mains) 2012]
(d) it becomes a p-type semiconductor
103 Symbolic representation of four logic gates are The current gain is [CBSE AIPMT 2011]
shown as [CBSE AIPMT 2011] (a) 75 (b) 100 (c) 25 (d) 50
105 The device that can act as a complete electronic
(i) (iii)
circuit is [CBSE AIPMT 2011]
(a) junction diode (b) integrated circuit
(ii) (iv) (c) junction transistor (d) zener diode
106 An n -p -n transistor can be consider to be equivalent
Pick out which ones are for AND, NAND and NOT to two diodes connected. Which of the following
gates, respectively. figures is the correct one? [KCET 2011]
(a) (iii), (ii) and (i)
(b) (iii), (ii) and (iv) (a) (b)
E C E C
(c) (ii), (iv) and (iii)
(d) (ii), (iii) and (iv)
104 A transistor is operated in common emitter B B
configuration atVC = 2 V such that a change in the (c) (d) E
E C C
base current from 100 µA to 300 µA produces a
change in the collector current from 10 mA to 20
mA. B B
ANSWERS
CHECK POINT 14.1
1. (a) 2. (a) 3. (a) 4. (d) 5. (b) 6. (b) 7. (c) 8. (b) 9. (a) 10. (d)
11. (b) 12. (b) 13. (b) 14. (a) 15. (d)
CHECK POINT 14.2

1. (d) 2. (d) 3. (d) 4. (a) 5. (b) 6. (b) 7. (c) 8. (a) 9. (b) 10. (a)
11. (c) 12. (b) 13. (b) 14. (c) 15. (d)
CHECK POINT 14.3

1. (a) 2. (d) 3. (c) 4. (b) 5. (b) 6. (a) 7. (a) 8. (a) 9. (a) 10. (d)
11. (b) 12. (b) 13. (a) 14. (a) 15. (a)
CHECK POINT 14.4

1. (c) 2. (a) 3. (b) 4. (b) 5. (d) 6. (d) 7. (b) 8. (c) 9. (d) 10. (b)
11. (d) 12. (a) 13. (d) 14. (d) 15. (c)
(A) Taking it together

1. (d) 2. (b) 3. (d) 4. (a) 5. (c) 6. (d) 7. (a) 8. (c) 9. (c) 10. (b)
11. (c) 12. (b) 13. (c) 14. (c) 15. (c) 16. (b) 17. (c) 18. (a) 19. (c) 20. (d)
21. (c) 22. (d) 23. (b) 24. (b) 25. (b) 26. (a) 27. (b) 28. (d) 29. (c) 30. (a)
31. (b) 32. (d) 33. (c) 34. (d) 35. (a) 36. (b) 37. (a) 38. (b) 39. (b) 40. (a)
41. (b) 42. (b) 43. (c) 44. (d) 45. (d) 46. (b) 47. (b) 48. (d) 49. (b) 50. (b)
51. (a) 52. (d) 53. (c) 54. (c) 55. (b) 56. (d) 57. (c) 58. (c) 59. (b) 60. (c)
61. (d) 62. (d) 63. (b) 64. (c) 65. (d) 66. (b) 67. (c) 68. (b) 69. (c) 70. (c)
71. (a) 72. (b) 73. (c) 74. (b) 75. (a) 76. (c) 77. (b) 78. (b) 79. (b) 80. (b)
81. (d) 82. (a) 83. (d) 84. (b) 85. (d) 86. (d) 87. (a) 88. (a) 89. (a) 90 (c)
91. (b) 92. (d) 93. (c) 94. (c) 95. (d) 96. (a) 97. (d) 98. (a) 99. (c) 100. (c)
101. (a) 102. (c) 103. (c) 104. (c) 105. (c) 106. (d) 107. (a) 108. (c) 109. (b) 110. (a)
111. (c) 112. (c) 113. (b) 114. (a) 115. (b) 116. (c) 117. (b) 118. (c) 119. (a) 120. (b)
121. (b) 122. (a) 123. (b) 124. (d) 125. (d) 126. (a) 127. (b) 128. (d) 129. (d) 130. (c)
131. (b) 132. (c) 133. (b) 134. (c) 135. (c)
(B) Medical entrance special format questions

l Assertion and reason
1. (a) 2. (a) 3. (b) 4. (a) 5. (c)
l Statement based questions

1. (c) 2. (c) 3. (d) 4. (d) 5. (c)
l Match the columns

1. (d) 2. (c) 3. (b) 4. (a)

1. (d) 2. (c) 3. (c) 4. (a) 5. (a) 6. (c) 7. (c) 8. (a) 9. (b) 10. (b)
11. (a) 12. (d) 13. (b) 14. (c) 15. (c) 16. (a) 17. (d) 18. (d) 19. (b) 20. (c)
21. (a) 22. (c) 23. (c) 24. (c) 25. (a) 26. (a) 27. (c) 28. (a) 29. (d) 30. (b)
31. (a) 32. (c) 33. (d) 34. (a) 35. (b) 36. (c) 37. (b) 38. (d) 39. (c) 40. (b)
41. (b) 42. (c) 43. (c) 44. (a) 45. (a) 46. (d) 47. (c) 48. (c) 49. (c) 50. (c)
51. (d) 52. (b) 53. (b) 54. (d) 55. (d) 56. (b) 57. (c) 58. (d) 59. (a) 60. (d)
61. (c) 62. (c) 63. (d) 64. (d) 65. (c) 66. (b) 67. (c) 68. (b) 69. (d) 70. (b)
71. (b) 72. (c) 73. (d) 74. (b) 75. (d) 76. (c) 77. (a) 78. (c) 79. (a) 80. (c)
81. (d) 82. (b) 83. (c) 84. (d) 85. (a) 86. (b) 87. (c) 88. (c) 89. (c) 90 (c)
91. (b) 92. (d) 93. (d) 94. (a) 95. (c) 96. (d) 97. (a) 98. (a) 99. (a) 100. (a)
101. (a) 102. (b) 103. (c) 104. (d) 105. (b) 106. (b)
Hints & Explanations

l CHECK POINT 14.1  ∆I  8.2
9 (a) β =  C  = = 82
4 (d) In insulators, the forbidden energy gap is largest and it is  ∆iB  V (8.3 − 8.2)
CE
of the order of 5 eV to 15 eV. i 5.488 α 0.98
10 (d) α = C = = 0.98; β = = = 49
5 (b) In insulators, the forbidden energy band gap is very large, iE 5.60 1− α 1 − 0.98
in case of semiconductor, it is moderate and in conductors, the
energy gap is zero because in conductor, valence band and ∆I C 1 × 10 −3
11 (b) Current gain, β = ⇒ ∆IB =
conduction band overlap to each other. ∆I B 100
9 (a) Aluminium is trivalent impurity which is doped with pure = 10 −5 A = 0.01mA
semiconductor to form p-type semiconductor. By using ∆iE = ∆iB + ∆iC ; ∆iE = 0.01 + 1= 1.01 mA
11 (b) The charge on hole is positive which is equivalent to V R
12 (b) out = β × out
charge on proton. Vin Rin
12 (b) For n-type semiconducting material, number of free Vout 1 3 1
⇒ Rout = × Rin × = × 1000 × = 3 kΩ
electrons is very large than number of holes, i.e. n e >> n h . Vin β 0.01 100
15 (d) Temperature coefficient of semiconductor is negative. 13 (a) Voltage gain = 10 log10 1000 dB = 30 dB
Copper, aluminium, iron are conductors, while germanium is
semiconductor. 15 (a) In oscillator, a portion of the output power is returned back
to the input in phase with the starting power. This process is
l CHECK POINT 14.2 termed as positive feedback.
10 (a) As, − 6 V < − 3 V l CHECK POINT 14.4
i.e. p is at low potential than n. 1 (c) 10111 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20
∴ Diode is reverse biased. = 16 + 0 + 4 + 2 + 1 = 23
−6V −3V
2 (a) 100010
p n
+ 11011
11 (c) When a large reverse voltage is applied across a p-n 111101
junction diode, a huge current flows in the reverse direction
suddenly. This is called breakdown of p-n junction diode. ∴ (100010 )2 + (11011)2 = (111101)2
5 (d) The boolean expression for AND gate is R = P ⋅ Q
12 (b) At a particular reverse voltage in p-n junction avalanche
breakdown occurs, hence a huge current flows in reverse R = P ⋅ Q ⇒ 1⋅ 1 = 1
direction known as avalanche current. 1⋅ 0 = 0; 0 ⋅ 1 = 0 and 0 ⋅ 0 = 0
13 (b) The p-n junction is used to convert AC into DC (rectifier). 6 (d) For AND gate, if output is 0, then one or both the inputs
must be 0.
14 (c) When a light falls on the junction, new hole-electron pairs
are created. Numbers of produced electron-hole pairs depend 8 (c) If inputs are A and B, then output of NAND gate isY = AB.
upon numbers of photons. So photo-emf or current is If A = B = 1, thenY = 1.1 = 1 = 0.
proportional to intensity of light.
9 (d) The given truth table is for NAND gate, sinceY = A ⋅ B.
l CHECK POINT 14.3
11 (d) Any digital circuit can be realised by repetitive use of
2 (d) In a bipolar junction transistor, emitter is heavily doped, NOR gate or NAND gate. NOR gate and NAND gate are called
base is lightly doped and collector is moderately doped. universal gates because by using these gates we can realise
5 (b) In p-n-p transistor, emitter-base is forward biased, hence other baisc gates like OR, AND and NOT gates.
holes move from emitter to base. 13 (d)
6 (a) When n-p-n transistor is used as an amplifier, majority Output
Input
charge carrier, i.e. electrons of n-type emitter move from OR AND NOR NAND
emitter to base end and then base to collector.
0 0 0 0 1 1
8 (a) Here, ∆VC = 0.5V , ∆IC = 0.05 mA
0 1 1 0 0 1
Output resistance is given by
1 0 1 0 0 1
∆VC 0.5
Rout = = = 10 4 Ω = 10 kΩ 1 1 1 1 0 0
∆I C 0.05 × 10 −3
From the above truth tables it is clear that the logic gates giving 38 (b) In the forward bias arrangement of a p-n junction diode, the
output ‘1’ for the inputs 1 and 0 are NAND and OR gates. p-end is connected to the positive terminal of the battery and
14 (d) When the two inputs of NAND gates are shorted, n-end with negative terminal of battery.
A Y p n
Y = A = which is equivalent to a NOT gate.

15 (c) A _
+
A
Y= A + B 40 (a) As, i = n eAv d

i
B So, vd =
n eA
B
So, when temperature is increased, n e increases and v d
Hence, output Y =A + B
decreases.
According to de-Morgan’s theorem,
41 (b) In forward biasing, the diffusion current increases and
Y = A + B = A⋅ B = A⋅ B drift current remains constant, so net current is due to
diffusion. In reverse biasing diffusion is not possible, so net
This is the output equation of AND gate. current (very small) is due to the drift.
42 (b) At a specific reverse voltage (breakdown voltage) in p-n
(A) Taking it together junction, a huge current flows in reverse direction known as
avalanche current.
2 (b) The concept of hole describes the lack of an electron at a
position where one could exist in an atom or atomic lattice. If 52 (d) Resistance of semiconductor decreases with increase in
an electron is excited into a higher state, it leaves a hole in its temperature. Hence, its temperature coefficient is negative.
old state.
56 (d) (E g )Ge < (E g )Si < (E g )C
Thus, hole can be defined as a vacancy created when an
electron leaves a covalent bond. [Q (E g )Ge = 0.7 eV, (E g )Si = 1.1eV, (E g )C = 5.5 eV]
3 (d) Resistance of conductor (Cu) decreases with decrease in 59 (b) From rectifier we get pulsating DC, which consists of AC
temperature while that of semiconductor (Ge) increases with ripples, to remove these unwanted ripples, we use filter circuits.
decrease in temperature. 61 (d) α is current gain in case of common base amplifier while β
8 (c) On increasing the temperature, the current in the circuit is current gain in case of common emitter amplifier. As,
will increase because with rise in temperature, resistance of α
β= . Since α < 1, hence β > 1. Hence, α is always less
semiconductor decreases, hence overall resistance of the circuit 1− α
decreases, which in turn increases the current in the circuit. than 1 and β is greater than 1.
14 (c) The majority charge carriers in p-type semiconductor are 63 (b) Collector current, IC = 10 mA
holes, while electrons are minority charge carriers.
Since, IC = 90% of IE
16 (b) p-type semiconductor can be made by doping a silicon 90
atom in the crystal lattice with a gallium (a trivalent impurity). ⇒ IC = × IE
100
17 (c) For making p-type semiconductor, we add trivalent impurity. 100 100 100
So, B impurity is mixed in Ge and Al impurity is mixed in Si. IE = × IC = × 10 = = 1111
. mA
90 90 9
18 (a) At room temperature, a p-type semiconductor has large 81.2
number of holes and few electrons, as holes are majority 65 (d) For full wave rectifier, η =
rf
charge carriers. 1+
RL
23 (b) Pentavalent impurity atom is to be added to Ge crystal, so
as to make a n-type semiconductor. ⇒ nmax = 81.2% (Q rf < < RL)
31 (b) In a transistor, emitter is heavily doped, base is least 67 (c) Here, A ⋅ A = A, A + A = A

doped while collector is moderately doped. and A + A = A ⋅ A = A
32 (d) Extrinsic semiconductors are also electrically neutral. But A ⋅ A = 0
34 (d) The conductivity of a semiconductor increases with 68 (b) When p -n junction is forward biased, it opposes the
increase in temperature, because the number density of potential barrier at junction but when p -n junction is reverse
current carriers increases. Here, due to high temperature, the biased, it supports the potential barrier at junction, resulting
relaxation time also decreases but effect of decrease in in increase in potential barrier across the junction.
relaxation time is much less than increase in number density.
69 (c) For full wave rectifier, the fundamental frequency in 83 (d) In forward biasing, both potential barrierVB and the width
ripple is twice that of input frequency. of charge depleted region x decreases.
72 (b) A NOR gate is combination of NOT and OR gate. The ∆i
85 (d) Given, β = c = 50, Ri = 1kΩ = 1 × 10 3 Ω, ∆Vi = 0.01V
boolean expression of NOR gate is C = A + B. ∆ib
∆Vi 0.01
73 (c) With the rise in temperature, resistivity of semiconductors ∴ ∆iin = ∆ib = = 3 = 10 −5 A
Ri 10
decreases exponentially.
∴ ∆ic = β ∆ib = 50 × 10 −5 A = 500 µA
75 (a) Given, E = 6 × 10 5 Vm−1
Vo
d = 500 nm = 500 × 10 −9 m 86 (d) A=
Vi − mVo
V =? Here, Vo = A V( i − 0.09Vo )
∴ Potential barrier, V = Ed = (6 × 10 5 ) (500 × 10 –9 ) = 0.30 V Vo V
Since, = 10 ⇒Vi = o
76 (c) The electrical conductivity of germanium, Vi 10
1 V 
σ = = e (µ en e + µ hn n ) ∴ Vo = A  o − 0.09Vo 
ρ  10 
= (1.6 × 10 −19 ) [0.36 + 0.17] (2.5 × 1019 ) ⇒ A = 100
(Q n e = n h = 2.5 × 1019 m−3) 87 (a) In figure (a), first gate is AND gate and second gate is NOT
= 2.12 Sm−1 gate. So, it is NAND gate.
77 (b) As, n e > > n h 88 (a) Here, diode is in reverse biased condition. In reverse
biasing, it acts as open circuit, hence no current flows.
So, it is an n-type semiconductor.
89 (a) In the given circuit, diode is in reverse biasing, so it acts as open
78 (b) In the given circuit, p -side of p-n junction diode D1 is circuit. Hence, potential difference between A and B is 6 V.
connected to lower voltage and n-side of, D1 to higher voltage. 92 (d) There is a phase difference of 180° in case of CE
Thus D1 is in reverse biased. V
amplifier. Also, voltage gain, AV = o , so
The p -side of p-n junction of D2 is at higher potential and Vi
n-side of D2 is at lower potential. Therefore, D2 is in forward Vo = AV ⋅Vi = 1000 × 0.004 = 4 V
biased.
Hence,Vo = (4 V ) sin (ωt − π / 2)
Hence, no current flows from B to A.
∆i
6 × 10 28 93 (c) α= c
80 (b) In 1cm3 of Si, there will be total = 6 × 10 22 atoms ∆ie
10 6
∴ ∆ic = α ∆ie = (0.98) (5) = 4.9 mA
Per 6 × 10 7 silicon atoms, there is one indium atom. Therefore,
hc
6 × 10 22 94 (c) Energy gap, E g =
total number of indium atoms will be = 1015 λ
6 × 10 7 hc 12400 eV-Å
⇒ λ= = = 17222 Å
81 (d) As p-n junction conducts during positive half cycle only, Eg 0.72eV
the diode connected here will work in positive half cycle.
Potential difference across C = peak voltage of the given AC 95 (d) Given, ∆ic = 0.990 mA
voltage = V0 = Vrms 2 = 220 2 V. ∆i 0.990
∴ α= c = = 0.990
82 (a) During the first half cycle whenVA > VC , all the four ∆ie 1
diodes are forward biased. Hence, no current will flow 96 (a) The given boolean expression can be written as
through RL. During second half cycle whenVC > VA, all the
Y = (A + B ) ⋅ (AB )
four diodes are reverse biased. Again, no current will flow
through RL. = (A ⋅ B ) ⋅ (A + B ) = (A ⋅ A ) ⋅ B + A (B ⋅ B )
B =A ⋅B + A ⋅B =A ⋅B
So, the truth table is
A B Y
A RL C 0 0 1
1 0 0
0 1 0
D 1 1 0
~ Hence, to getY = 1, A = 0 and B = 0.

97 (d) Given, α = 0.9 and ∆IE = 4 mA 110 (a) Intensity of electric field,
α V 0.50
Q β= ⇒ β=9 E = = = 1.0 × 10 6 Vm−1
1− α d 5 × 10 −7
∴ ∆IC = 9∆IB 111 (c) Due to forward biasing during positive half cycle of input
⇒ ∆IE − ∆IB = 9∆IB AC voltage, the resistance of p-n junction is low. The current
in the circuit is maximum. In this situation, a maximum
∆I 4
⇒ ∆I B = E = potential difference will appear across resistance connected in
10 10 series of circuit. This result into zero output voltage across p-n
⇒ IB = 0.4 mA junction.
So, ∆IC = 9 × 0.4 = 3.6 mA Similarly during negative half cycle of AC voltage, the p-n
junction is reverse biased. The resistance of p-n junction
98 (a) In case of forward biasing, resistance of p-n junction diode
becomes high which will be more than resistance in series.
is zero. So, whole voltage appears across the resistance.
That is why, there will be voltage across p-n junction with
12375 12375 negative cycle in output.
99 (c) λ (in Å) = = Å ≈ 217100 Å
E (in eV ) 57 × 10 –3
112 (c) D1 is forward biased and D2 reverse biased.
100 (c) In the truth table, output X = A . So, this truth table is of Therefore, current through the resistance and D1 will be equal
NOT gate. 5
and which is equal to = 1.25 A
103 (c) 1 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 0 × 20 + 1× 2−1 4
+ 0 × 2−2 + 1 × 2−3 = 26.625 113 (b) D1 is reverse biased. Therefore, no current will flow
through 20 Ω resistance.
104 (c) For option (c), it is a NAND gate, its output = 0.1 = 0 = 1
As, 30 Ω and 20 Ω resistance are in series, so total current
106 (d) The output D for the given combination, will be (5/50) A.
D = (A + B ) ⋅ C = (A + B ) + C 114 (a) First diode is in reverse biasing, it acts as open circuit,
If A = B = C = 0, then hence no current flows.
D = (0 + 0 ) + 0 = 0 + 0 = 1 + 1 = 1 115 (b) For forward biasing, p-side is at higher potential and
n-side is at lower potential, so diode in figures II, IV and V
If A = B = 1 and C = 0, then
are forward biased.
D = (1 + 1) + 0 = 1 + 0 = 0 + 1 = 1
116 (c) IfVA > VB , then both the junction diodes are in forward
107 (a) For upper part, biased and the given circuit diagram becomes a balanced
A Wheatstone bridge. The equivalent resistance in this case
A becomes 4 Ω.
IfVA < VB , then the diodes are reverse biased. In that case,
C= A .B 4 Ω, 5 Ω and 4 Ω are in series, i.e. Rnet = 13Ω.
117 (b) Consider the figure given here, suppose the potential
B difference between A and B isV.
B A
0.2 mA
Here, C = A ⋅ B = A + B (from de-Morgan’s theorem)
r1 5kΩ
=A+ B
Here, output C is equivalent to OR gate.
For lower part,
A .B 0.3V
A AB
C r2 5kΩ
B
C = AB = AB B
In this case, output C is equivalent to AND gate. Then,V − 0.3 = [(r1 + r2 ) 10 3] × (0.2 × 10 −3 )] (QV = ir )
108 (c) 3 −3
A
A
A+B = [(5 + 5) 10 ] × (0.2 × 10 )
Y
B = 10 × 10 3 × 0.2 × 10 −3 = 2
B
⇒ V = 2 + 0.3 = 2.3V
109 (b) Diode is in forward biased condition. So, current flow
118 (c) Here, C = A. B and D = A . B
(4 − 1)
i= = 10 −2 A
300 E = C + D = (A⋅ B ) + (A ⋅ B )
Explanation The truth table of this arrangement of gates can We know that in a forward biased p-n junction diode, the
be given by repultion of holes and electrons takes place which decreases
A B A C = A⋅B d =A ⋅B E = (C + D ) width of potential barrier by striking the combination of holes
and electrons. We also know that the options (c) and (d) show
0 0 1 0 0 0
the potential barrier in the reverse biias, whereas in options
0 1 1 0 1 1 (a) and (b) show the potential barrier in forward bias
1 0 0 0 0 0 Morevover, the width of depletion layer in option (b) is less
than shown in option (a). Thus, the option (b) is correct.
1 1 0 1 0 1
I (mA)
129 (d)
β
119 (a) Transconductance, gm = AC
Rin a
VZ
where, β AC = current gain d c b
V (V)
and Rin = input resistance. e
20
∴ gm = = 0.01 Ω −1
2 × 10 3 I (µA)
120 (b) Given,V = 9V If the reverse bias voltage is greater than theVZ , then there is
breakdown condition. In breakdown region, i.e. Vi > VZ and
ib = 35 µΑ = 35 × 10 −6 A for a long range of load (RL ), the voltage is constant.
Rb = ? 130 (c) Voltage of the source,
We know that, V = ib Rb V = VD + iR = 0.5 + 0.1 × 20 = 2.5 V
V 9 131. (b) The potential across R = 17 V − 9 V = 8 V
⇒ Rb = = = 257 kΩ
ib 35 × 10 −6
132 (c) Total resistance in the circuit, R = 2 k Ω and E = 20 V
121. (b) Voltage across Zener diode is constant, E 20
∴ The current, I = = = 10 mA
250 Ω i250Ω i1kΩ R 2000
+
5V 133 (b) In the given circuit, the Zener diode is used as a voltage
iZener diode regulating device.
+
20 V 15 V 1 kΩ Hence, the voltage across 1 k Ω is 5 V.
–
Current flowing through 1 kΩ resistor,
– 5
I= = 5 × 10 −3A = 5 mA
15 1× 10 3
i1 kΩ = = 15 mA
1 × 10 3 134 (c) In the given circuit, diode D1 is reverse biased, so it will
(20 − 15) 5 20 not conduct. Diodes D2 and D3 are forward biased, so they will
i250 Ω = = = = 20 mA conduct. The corresponding equivalent circuit is as shown in
250 250 1000 the figure
∴ iZener diode = (20 − 15) = 5 mA D3 5Ω
122 (a)Y = A + B = A ⋅ B, i.e. it is a AND gate.
123 (b) In the positive half cycle of input AC signal diode, D1 is in 5Ω
forward biased and D2 is in reverse biased, so in the output 20 Ω D2
voltage signal, A and C are due to diode D1. In negative half
cycle of input AC signal, diode D2 is in forwards biased, hence 10V
it conducts, so output signals B and D are due to diode D2.
The equivalent resistance of the circuit is
125 (d) A (5 + 5) × 20 10 × 20 200 20
A A . (B + C ) Req = = = = Ω
Y (5 + 5) + 20 10 + 20 30 3
10 V
B B+C Current through the battery, I = = 1.5 A
20
C Ω
3
126 (a) The diode is in reverse biasing, so no current flows 135 (c) In circuit A, both the p-n junction diodes are in forward
through it. biased.
127 (b) Potential across the p-n junction varies symmetrically Total resistance R is given by
linear, having p side negative and n side positive. 1 1 1 1 2
= + ⇒ = ⇒R = 2 Ω
R 4 4 R 4
According to Ohm’s law l Match the columns

V = IA R
1 (d) Diode gets forward biased during positive half cycle of
⇒ 8 = IA × 2 alternating source and current flows. Let the barrier voltage
⇒ IA = 4 A of diode isVB and its forward resistance be RF and load
In circuit B, lower p-n junction diode is in reverse biased. resistance be RL , then peak voltage of applied signal is
Hence, no current will flow in it but upper diode is forward V0 = VB + i0 (RF + RL )
biased, so current can flow through it. V − VB 20 − 0.7
∴ i0 = 0 = = 37.8 × 10 −3 A = 37.8 mA
V = IBR ⇒ 8 = IB × 4 ⇒ IB = 2 A. RF + RL 10 + 500
Peak voltage at the ends of the load RL ,
(B) Medical entrance special format VL = i0 × RL = 37.8 × 10 −3 × 500 = 18.9 V
questions For ideal diode,VB = 0 and RF = 0
V 20
l Assertion and reason ∴ i0 = 0 = = 0.04 A = 40 mA
RL 500
1. (a) In semiconductors, the energy gap between conduction and VL = i0RL = 0.04 × 500 = 20 V
band and valence band is small (≈ 1eV). Due to temperature
rise, electron in the valence band gain thermal energy and Hence, A → p, B → s, C → q, D → r.
may jump across the small energy gap, (to the conduction
band). Thus, conductivity increases and hence resistance
decreases.
1 (d) A p-n junction diode is in forward biased when p-side is
2 (a) According to law of mass action, ni2 = n en h . In
connected with more positive potential than n-side.
intrinsic semiconductors ni = n e = n h and for p-type
semiconductor n e would be less than ni, since n h is necessarily Since, 0 V > − 3V.
more than ni . Hence in option (d), diode circuit is in forward biased.
3 (b) In forward biasing of p-n junction, current flows due to 2 (c) According to given circuit diagram
diffusion of majority charge carriers. While in reverse biasing,
RC = 800 Ω, VCC = 8V
current flows due to drifting of minority charge carriers.
The circuit given in the reason is a p-n-p transistor
having emitter more negative w.r.t. base, so it is reverse 800 Ω
RB
biased and collector is more positive w.r.t. base, so it is IC
forward biased. 8V
IB
4 (a) These gates are called digital building blocks because
using these gates (either NAND or NOR) we can compile all
other gates also (like OR, AND, NOT, XOR).
Voltage drop across RC ,
5 (c) In diode, the output is in same phase with the input, VC = 0.8V ⇒ ICRC = 0.8
therefore it cannot be used to built NOT gate.
0.8 0.8
IC = = = 10 − 3A = 1 mA
l Statement based questions RC 800
1 (c) In a transistor, the base region must be very thin and 3 (c) NAND and NOR gate are called universal gate because all
lightly doped. For the normal action of transistor emitter type of logic gates and boolean expressions can be realised
junction is in forward biased and collector junction is in with the help of NAND and NOR gate.
reverse biased.
4 (a) When a pentavalent (phosphorous) impurities is doped
3 (d) Resistivity of a semiconductor decreases with the with intrinsic semiconductor (Ge, Si), then n-type
temperature. The atoms of a semiconductor vibrate with semiconductor is formed.
larger amplitudes at higher temperature thereby increasing its
5 (a) Under reverse bias condition, the holes of p-side are
conductivity not resistivity.
attracted towards the negaive terminal of the battery and
5 (c) Input impedance of common emitter configuration electrons of the n-side are attracted towards the positive
∆VBE terminal of the battery. This increases the width of the
= depletion layer.
∆iB V CE = constant
However, in the case of forward biasing, the width of the
where, ∆VBE = voltage across base and emitter (base-emitter depletion layer decreases.
region is forward biased) 6 (c) Insulators and semiconductors are those solids, which have
∆iB = base current which is order of few microampere. negative temperature coefficient of resistance. As, when
Thus, input impedance of common emitter is low. temperature increases number of free electrons increases in
both insulator and semiconductor.
7 (c) In case of transistor action, base region is thin and lightly 11 (a) From the circuit diagram given below, it can be seen that
dopped, while emitter region is heavily dopped and collector the current will flow to ground if any of the switch is closed.
region is moderately dopped. Also, the size of collector is Also, the LED will only glow when current flows through it,
slightly more than the size of emitter. i.e. both the switches should be open.
8 (a) p -type semiconductors are obtained when a trivalent +6V
impurity, e.g. boron, aluminium, gallium or indium) is added R
0
to a intrinsic semiconductor (e.g. germanium or silicon). A
1
In other words, the dopants in p-type semiconductor is 0
B
trivalent atom. Thus, this addition creates deficiencies of
1
valence electron which are most commonly known as holes. LED (Y)
These are the majority charge carriers in this type of
R
semiconductor.
However, in n-type semiconductors, the dopants are pentavalent
impurities. Also, the majority charge carriers in n-type
Thus, the truth table for the circuit diagram can be formed as
semiconductor are electrons.
A B Y
9 (b) The energy of light of wavelength λ is given by
hc 0 0 1
E = hν =
λ 0 1 0
hc 1 0 0
⇒ λ= …(i)
E 1 1 0
Here, h = Planck’s constant = 6.63 × 10 −34 J-s
The output Y
( ) is equivalent to that of NOR gate.
c = speed of light = 3 × 10 8 m/s
12 (d) Given, voltage across Zener diode,VZ = 6 V
E = energy gap = 1.9 eV = 1.9 × 1.6 × 10 −19 J
Since, Zener diode provide stabilised supply of 6 V.
Substituting the given values in Eq. (i), we get
1 kΩ
6.63 × 10 −34 × 3 × 10 8
⇒ λ=
1.9 × 1.6 × 10 −19 IL
– +
= 6.54 × 10 −7 m Vz = 6 V Iz
R I
≈ 654 nm
Thus, the wavelength of light emitted from LED will be 654 nm.
10 (b) The LED will glow when the current flows through it, i.e. 30 V
when the voltage across it is high. In this case, the value of R should be chosen such that
The truth table can be formed from this negligible current flows through the Zener diode.
∴ I = IZ + IL = 0 + IL
+6V
30
I=
R R + 10 3
0
But I = 6 mA = 6 × 10 −3A
A 1
Y 30
∴ 6 × 10 −3 = ⇒ R = 4 × 10 3 Ω = 4 kΩ
R + 10 3
R
0
13 (b) A p-n junction photodiode can be operated under
B 1
photovoltaic conditions similar to that of a solar cell. The
current-voltage characteristics of a photodiode and solar cell
A B Y under illumination are also similar.
0 0 1 When light energy falls on the solar cell, then it converts
solar energy into electrical energy.
0 1 1
The area of solar cell should be larger, so that it could
1 0 1 absorbed more amount of sunlight and hence more amount of
1 1 0
electrical energy is obtained.
Hence, Assertion and Reason both are correct but Reason is
The outputY is same as that come from NAND gate. not the correct explanation of Assertion.
14 (c) Given, R out = 200 Ω , Rin = 100 kΩ = 10 5 Ω Substituting the value of IB and IC from Eqs. (i) and (ii), we get
VCC = 3 V,VBE = 0.7 V,VCE = 0V, β = 200 5 × 10 −3
⇒ β= = 0.125 × 10 3 = 125
Applying KVL at output side, 40 × 10 −6
VCE = VCC − ICRout 19 (b) According to the question, the figure of combination of
0 = 3 − IC × 200 gates in terms of inputs and outputs can be given as
⇒ IC = 15 mA A A C=A×B
I 15 × 10 −3
∴ IB = C = = 75 × 10 −6 A B
C
Y=C+D
β 200 B B
A D
∴ IB = 75 µA A
Again, applying KVL at input side, B D=A×B
VBE = VBB − IBRin

Thus, Y = C + D = A⋅B + A ⋅B
⇒ VBB = VBE + IBRin = 0.7 + 75 × 10 −6 × 10 5
= 0.7 + 7.5 = 8.2 V 20 (c) Current passing in the circuit,
P 100 × 10 −3
15 (c) In n-p-n transistor under CE configuration, emitter current I= = = 0.2 A
IE is equal to sum of collector current IC and base current IB , V 0.5
i.e. IE = IC + IB Value of connected series resistance,
1.5 − 0.5 1
16 (a) According to give logic diagram, R= ⇒ R=
0. 2 0.2
Y ′ = (A′ B′ )′ = (A′ )′ + (B′ )′ = A + B
∴ Y = Y ′ = (A + B )′ = output of NOR gate ∴ R =5Ω
17 (d) Due to increase in temperature because of heating, thermal 21 (a) In the forward biasing of p-n junction, p -side of junction
collision increases. Thus, net electron-hole pairs increase. diode is connected to higher potential and n-side of junction
This leads to increase in the current in diode and overall diode is connected to lower potential. As 0 V > −2 V, hence
resistance of the diode changes. This in turn changes both the option (a) is the correct answer.
forward biasing and the reverse biasing. Thus, the overall I-V V 3
characteristics of p-n junction diode gets affected.
22 (c) Collector current, iC = = = 10 −3 A
R 3 × 10 3
18 (d) Given,VBE = 0 V,VCE = 0 V andVi = 20 V iC 10 −3
Now, base current, iB = = = 10 −5 A
VCC = 20 V β 100
RC = 4 kW As, voltage, Vin = iBRB
= 4×103W
IC
∴ Vin = 10 −5 × 2 × 10 3 = 2 × 10 −2 V
C Vout 3
So, voltage gain, AV = = = 150
IB Vin 2 × 10 −2
Vi VB
B
RB=500 kW Power gain = AV × β
= 500×103W E = 150 × 100 = 15000
23 (c) Truth table for given network is
NOR NOR NOT
A Y
Applying Kirchhoff’s law to the base-emitter loop, we get B Y1 Y2
Vi = IB RB + VBE
Substituting the values, we get
A B Y1 Y2 Y
20 = IB × (500 × 10 3 ) + 0
0 0 1 0 1
20
⇒ IB = = 0.04 × 10 −3 1 0 0 1 0
500 × 10 3
= 40 × 10 −6 = 40 µA …(i) 0 1 0 1 0
Similarly, VCC = ICRC + VCE 1 1 0 1 0
Substituting the given values, we get Output Y of network matches with that of NOR gate.
20 = IC × (4 × 10 3 ) + 0
24 (c) Given, one indium atom to be doped in 5 × 10 7 silicon
20
⇒ IC = = 5 × 10 −3 = 5 mA …(ii) atoms.
4 × 10 3
Number density of silicon
I
Current gain is given as β = C = 5 × 10 28 atom m −3
IB
≈ 5 × 10 22 atom cm −3
Number of acceptor atom cm −3 VL V 0.8 × 0.96

∴ Voltage gain, AV = = L = =4
5 × 10 22 Vin IBRi 10 −3 × 192
= = 1 × 1015 cm− 3
5 × 10 7 ⇒ AV = 4
3 15 −3
Hence, number of acceptor atom/cm is 1 × 10 cm . IC2RL  IC  RL
2
800
and power gain, AP = =  ⋅ = (0.96)2 ×
25 (a) Given, β = 49 and ∆IB = 5µA IB2Ri  IB  Ri 192
∆I C ∴ AP = 3.84
Current gain, β = , where ∆IC is change in collector
∆I B
30 (b) Given, collector resistance, Rout = 2 k Ω
current and ∆IB is change in base current.
∆IC = β∆IB = 49 × 5 = 245µA Current amplification factor, β = 100
∆IE = ∆IB + ∆IC = (245 + 5) µA Base resistance, Rin = 1k Ω
= 250 µA Output signal voltage = 4V
26 (a) The simplified circuit is shown in figure below Putting all the values in given equation, we get
R 2 kΩ
A AV = β out = 100 × ⇒ AV = 200
A Rin 1kΩ
( out )AC
V 4
B
B
Y Now, AV = = 200 ⇒ V
( in )AC = = 20 mV
( in )AC
V 200
C C
31 (a) We know that a diode only conducts in forward biased
condition. In the given circuit, the diode D1 will be in reverse
So, output Y = A ⋅ B ⋅ C = A + B + C = A + B + C bias, so it will block the current and diode D2 will be in
If A = 0, B = 1, C = 1 forward bias, so it will pass the current.
∴ Y = 0 + 1+ 1= 0 + 1= 1 V 10
Thus, i = = = 2.5 A
27 (c) The resultant boolean expression of the logic circuit will R1 + R3 2 + 2
be 32 (c) Output of the given circuit is given by
Y = (A + B ) ⋅ C
Now, let us try with inputs A, B and C given in the options Y = (AB )(C )
and lets see, which one of them will give output 1 at Y. When A = B = C = 0, Y1 = (0 )(0 )(0 ) = 0 = 1
If A = 0, B = 0, C = 0, then When A = B = C = 1, Y2 = (1)(1) = 0
Y = (0 + 0 ) ⋅ 0 ⇒ Y = 0
If A = 1, B = 1, C = 0, then 33 (d) IfY represents the given Boolean expression P + PQ , then
Y = (1 + 1) ⋅ 0 ⇒ Y = 1⋅ 0 ⇒ Y = 0 Y = P + PQ = P (1) + PQ
If A = 1, B = 0, C = 1, then = P (1 + Q ) + PQ (Q 1 = 1 + X)
Y = (1 + 0 ) ⋅ 1 ⇒ Y = 1⋅ 1 ⇒ Y = 1 = P + PQ + PQ
If A = 0, B = 1, C = 0, then = P + Q (P + P )
Y = (0 + 1) ⋅ 0 ⇒ Y = 1⋅ 0 ⇒ Y = 0 =P + Q (Q X + X = 1)
So, we have seen that among the given options, only = output of OR gate
option (c) is the correct choice, i.e.
Hence, given expression represents OR gate.
OutputY = 1only when inputs A = 1, B = 0 and C = 1.
34 (a) The overall conductivity of a semiconductor,
28 (a) Let us assume that current through the diode is I. σ = ne e µ e + np e µ p
From the given condition, σ = e [µ e n e + n p µ p ]
V − VB 4 − (−6) 10
Q I= A = = = 10 −2 A Also, n e n p = ni2 [for an intrinsic semiconductor]
R 1 kΩ 1 × 10 3
ni2
⇒ ne =
29 (d) Given, resistance across load, RL = 800 Ω np
Voltage drop across load,VL = 0.8 V
n 2 
Input resistance of circuit, Ri = 192 Ω Now, σ = e  i µ n + µ pn p 
V 0.8 8 n
 p 
Collector current is given by IC = L = = = 1mA
RL 800 8000  n2 
dσ
Output current On differentiating, = e − i2 µ n + µ p  = 0
∴ Current amplification = dn p  np 
Input current
ni2 µn
I 1 mA ⇒ µp = µ n ⇒ n p = ni
= C = 0.96 ⇒ IB = n p2 µp
IB 0.96
35 (b) When input signal 1 is applied to a NOT gate, then its 46 (d) Output of NOR gate,Y ′ = A + B
output will be opposite to that of the input, i.e. 0 .
Output of NAND gate,
37 (b) For an intrinsic or pure semiconductor, the number
densities of electron and hole are the same, i.e. Y ′′ = (A + B ) ⋅ (A + B ) = (A + B ) ⋅ (A + B )
np = ne = (A + B ) (A + B ) = A + B
38 (d) The common application of Zener diode is stabilisation or Output of NOT gate,
voltage regulation. Y ′′′ = A + B
39 (c) We know that, the relation between α and β is given as ∴ The boolean expression is for NOR gate.
α α 47 (c) The output of digital circuit can be given asY = AB + C .
β= ⇒ 100 =
1− α 1− α
It will be same asY = A + B + C .
⇒ 100 − 100 α = α
48 (c) Each and every extrinsic semiconductor is electrically
100 neutral whether it is p-type or n-type.
∴ α= = 0.99
101 ∆I
49 (c) We know that, α = C
40 (b) Given arrangement is ∆I E
A A.B A.B ⇒ ∆IC = α ∆IE = 0.96 × 10 = 9.6 mA
I II Y
B The change in base current, ∆IB = ∆IE − ∆IC
= 10 mA − 9.6 mA = 0.4 mA
Gate I → NAND gate
Gate II → AND gate 50 (c) The output of G1 = A + B
Above arrangement represents NAND gate. Output of G2 = A ⋅ B
−6
41 (b) Given, ∆ IB = 20 µA = 20 × 10 A and output of G3 = (A + B ) (A ⋅ B ) = AB + BA
∆ IC = 2mA = 2 × 10 −3A This output is same as the output of an XOR gate.
and ∆VBE = 0.04 V 51 (d) Voltage gain = β × Resistance gain
∴ ∆VBE = RBE × ∆ IB
α 0.99
⇒ 0.04 = RBE × 20 × 10 −6 Ω ⇒ RBE = 2 k Ω β= = = 99
1 − α (1 − 0.99)
∆I C 2 × 10 −3 Ω 1 Input impedance 10 × 10 3
Now, current gain = = = × 10 3 = 100 Resistance gain = = = 10
∆IB 20 × 10 −6 Ω 10 Load impedance 10 3
∆Q 1010 × 1.6 × 10 −19 Voltage gain = β × Resistance gain = 99 × 10 = 990
43 (c) The current, I = =
∆t 2 × 10 −6 52 (b) The circuit is
⇒ I = 1010 × 10 −19 × 10 6 × 0.8 = 0.8 × 10 −3 50 Ω
−6
= 800 × 10 A = 800 µA
100 Ω
44 (a) The output of OR gate is given by A + B =Y
B + – 150 Ω
10 V
NOT gate
The output of NOR gate As the lower diode attached to 100 Ω resistance is in reverse
A + B =Y biased, so it is non-conducting.
Now, the circuit can be redrawn as
When, A = B, then A + A = A = NOT gate
50 Ω
45 (a) Given, energy gap, E g = 1.9 eV = 1.9 × 1.6 × 10 −19 V
hc hc
We know that, E g = ⇒ λ=
λ Eg
+ − 150 Ω
Wavelength of the emitted light,
6.63 × 10 −34 × 3 × 10 8 10 V
λ=
1.9 × 1.6 × 10 −19 V 10
∴ Current through the circuit, I = = = 0.05 A
λ = 6.5 × 10 −7m R 200
53 (b) Input characteristics curve is drawn between base current 60 (d) The combination of three NAND gates are shown in the
IB and emitter-base voltageVBE at constant collector-emitter diagram
voltageVCE . Y1
A G1
Dynamic input resistance,
 ∆V  G3
Ri =  BE  Y
 ∆I B  V
CE = constant Y2
B G2
VCE = 0 V CE =1 V =2 V
IB V CE Y1 = Output due to NAND gate 1= A ⋅ A = A
(µA)
Y2 = Output due to NAND gate 2 = B ⋅ B = B
Output due to NAND gate 3

VBE (volt)
Y = Y1 ⋅Y2 = Y1 + Y2 = A + B = A + B
54 (d) The mobility of electron is greater than holes because This is OR gate. Hence, the combination is equivalent to an
electron require less energy to move. OR gate.
55 (d) As the diode is forward biased, so it takes only positive 62 (c) The resistivity of semiconductors is greater than metals.
value. Hence, option (d) is correct.
64 (d) The n -type semiconductor region has (negative) electrons
56 (b) 2Ω D2
as majority charge carriers and an equal number of fixed
positively charged donor ions. Again, the material as a whole
D1 3Ω is neutral. That is a reason, that atom is electrically neutral.
+ –
Electron
4Ω
12 V
In the given circuit, D1 is forward biased and D2 is reverse

biased, so D1 works like a closed switch and D2 works like an
n-type
open circuit, so circuit becomes
Donor ion
2Ω D2
65 (c) The wrong statement with reference to a solar cell is
D1 3Ω that, it uses materials with band gap of 5 eV. Because, for
solar cell, band gap is less than 3 eV.
66 (b) Initial current, Iin = 0
4Ω 12 V Vi = 6V 150 Ω +3V
Now, current in the circuit, (6 − 3)

E 12 Final current, If = = 0.02A
I= = 150
RS 4 + 3 So, change in current, ∆I = If − Iin = 0.02 − 0
12 = 0.02A = 20 mA
⇒ I=
7
67 (c) When the applied reverse voltage V reaches the
⇒ I = 1.71 A breakdown voltageVZ of the Zener diode, then there is a large
57 (c) The conductivity of the intrinsic semicondutor is change in the current. So, after the breakdown voltageVZ , a
independent of fermi energy. It depends upon band gap, large change in the current can be produced by almost in
temperature as well as effective mass of charge carriers. significant change in the reverse bias voltage.
58 (d) Barrier potential should depend on all the three points
given. Barrier potential depends on the material used to make R
p-n junction diode (whether it is Si or Ge). It depends on
amount of doping due to which the number of majority
Zener diode Load
carriers will change. It should also depend on temperature due
to number of minority carriers will change.
59 (a)V-I characteristic of a solar cell is shown in the question, As Zener voltage remains constant even though the current
where A represents open circuit voltage and B shows short through the Zener diode varies over a wide range, hence it is
circuit current. used to obtain regulated voltage output.
68 (b) Given, α = 0.95, Ib = 0.2 mA 74 (b) By absorption law, outputY = A + A ⋅ B

IC IE − IB I A A+A.B
As, α= = = 1− B NOT
IE IE IE Y
A
IB A AND
⇒ = 1 − α = 1 − 0.95 = 0.05 OR
IE
B A .B
I 0.2 or Y = A ⋅ B + A = A ⋅ (B + 1) = A ⋅ 1 = A
⇒ IE = B =
0.05 0.05
75 (d) According to the logical relationship,
⇒ IE = 4 mA
Output,Y = A + B = A ⋅ B = A ⋅ B
1
69 (d) For transistor as an oscillator, f =
2π LC A
A
6
where, f = 2 MHz = 2 × 10 Hz and LC = ?
Y = A+B =A.B
1 1 1
⇒ LC = = =
2πf 2π × 2 × 10 6 4π × 10 6 B
B
70 (b) α and β are the AC current gains of a transistor in the
common base configuration and in the common emitter So, it is AND gate.
configuration respectively and are related as
76 (c) A diode is symbolically shown in the adjacent diagram.
α 0.98 The diode is said to be forward biased, whenVA > VB .
β= = (Q α = 0.98)
1 − α 1 − 0.98 The diode is said to be reverse biased, whenVA < VB .
0.98 98 +5 V
= = = 49
0.02 2
71 (b) As IB is in µA, IC is in mA andVCE in V.
A B
72 (c) A common base circuit of a p-n-p transistor is shown in
figure. The emitter-base (p-n) junction on the left is given a
small forward bias (fraction of a volt) by an emitter-base 0V
batteryVEB , while the base collector (n-p) junction is given a In the option (b), 5 V > 0 V
large reverse bias (a few volt) by another batteryVCB .
Hence, VB > VA
So, the required solution is emitter-base (EB) junction forward
bias and collector-base (CB) junction reverse bias. So, the diode is reverse biased.
77 (a) The OR gate is a device that has two (or more) input
Emitter Base Collector
p n p variables A and B and one output variableY and follows the
boolean expression, A + B = Y, read as ‘A OR B equalsY ’.
E C
Truth table for given gate G1 combination
Input Output
B
A B Y =A+ B
iE ic 0 0 0
Forward iB Reverse
biased biased
Hole (+) 0 1 1
+ – + – Electron (–) 1 0 1
VEB VCB 1 1 1
Similarly, the AND gate is also has two inputs and one output
73 (d) If the two inputs of a NAND gate are joined together, it
and follows boolean expression A ⋅ B = Y , read as A AND B
works as a NOT gate. Now, if the inputs A and B are inverted
equals Y.
by using two NOT gates (obtained from two NAND gates) and
the resulting output A and B are fed to a third NAND gates. Truth table for given gate G 2 combination
A Input Output
A
A B Y = A⋅B
Y=A⋅B =A+B=A+B 0 0 0
0 1 0
B
B
1 0 0
So, three NAND gates are required to make an OR gate. 1 1 1
The NOR gate is a combination of OR and NOT gates. Truth table for the circuit
The boolean expression for the NOR gate is Y1 = AB
A B Y2 = Y1
A + B =Y .
0 0 0 1
Truth table for given gate G 3 combination
0 1 0 1
Input Output
1 0 0 1
A B Y′ = A + B Y = A + B = Y′
1 1 1 0
0 0 0 1
It represents a NAND gate.
0 1 1 0
82 (b) For making a junction transistor, the emitter E is heavily
1 0 1 0 doped, the base B is thin and lightly doped and the collector C is
1 1 1 0 moderately doped semiconductor materials are join together.
 ∆I 
The NAND gate is a combination of AND and NOT gates. 83 (c) β =  C 
 ∆I B  V
The boolean expression for the NAND gate is CE = constant
A ⋅ B =Y 4 × 10 −3
60 =
Truth table for given gate G 4 combination ∆IB
4 × 10 −3
Input Output ⇒ ∆IB = = 66.6 µA
60
A B Y′ = A ⋅ B Y = A ⋅ B = Y′
87 (c) A + A should always be equal to 1. As, addition of inputs
0 0 0 1 like 1 to 0 or 0 to 1 always gives 1.
0 1 0 1 88 (c) The depletion layer in the p-n junction region is caused
1 0 0 1 due to the diffusion of carriers on either side of the junction.
1 1 1 0 89 (c) A digital signal has only two values of voltage variation
with time. Its value is either zero or maximum (1).
So, the required solution is
90 (c) The diode D1 is in reversed biased and D2 is in forward
G1 → OR gate, G2 → AND gate, G3 → NOR gate and
biased. The resistance of D1 in in becomes infinite and of D2 is
G4 → NAND gate.
zero. Therefore, current in the circuit,
emf 12
I= = =2A
78 (c) The n-type semiconductor can be produced by doping an total resistance 4 + 2
impurity atom of valency 5, i.e. pentavalent atoms.
91 (b) For using transistor as a switch, it is used in cut-off state
Here, majority carriers are electron and minority carriers are and saturation state only.
holes.
92 (d) Here in circuit D1 is forward bias and D2 is reverse bias.
 β  β
79 (a) As, G =   RL ⇒ G = gm RL Q gm =  Current will flow only in diode D1
 Ri   Ri 
10 Ω
⇒ G ∝ gm
G2 gm2
∴ = i
G1 gm1
0.02
⇒ G2 = ×G
0.03 5V
2 5
∴ Voltage gain, G2 = G The current supplied by the battery, i = = 0.5 A
3 10
∆ IC
80 (c) X = AB = A ⋅ B (i.e. AND gate) 93 (d) Current amplification factor, β =
∆ IB
If the output X of NAND gate is connected to the input of 2V
NOT gate (made from NAND gate by joining two inputs) from Collector current, ∆ IC = = 1 × 10 −3A
the given figure, then we get an AND gate. 2 × 10 3 Ω
81 (d) Base current,

Y1 = A B Y2 = Y1 . Y1=Y1
VB VB
A ∆ IB = = = VB × 10 −3
B RB 1 × 10 3
Given, β = 100 101 (a) A

10 −3 A
A+B
Now, 100 =
VB × 10 −3 B
Y
B
1
⇒ VB = V = 10 mV
100
A + B = A⋅ B = A⋅ B
94 (a) From the given waveforms, the following truth table can
This boolean expression represents AND gate, i.e.
be made
A
Input Output Y
B
A B C
0 0 0 102 (b) When a small amount of antimony is added to germanium
1 0 1 crystal, the crystal becomes n-type semiconductor, because
1 1 1 antimony is a pentavalent substrate and act as donor atom. So,
0 1 1 there will be more free electrons than hole in the
semiconductor.
This truth table is similar to OR gate, so logic gate is OR gate.
103 (c) Symbols given in the problem are
Note The logic of the OR gate is, if any of the input is one, then (i) OR gate (ii) AND gate
output is one.
(iii) NOT gate (iv) NAND gate
V0 V
95 (c) As, Vrms = ⇒ 220 = 0 104 (d) Current gain,
2 2
∆I C (20 − 10 ) mA
⇒ V0 = 311.1 V β= =
∆IB (300 − 100 ) µA
96 (d) Resistivity of a semiconductor is 10 − 5 - 10 6 Ω-m while that
of insulator is 1011-1019 Ω -m and conductor is 10 −2 - 10 −8 Ω-m. 10 × 10 − 3
= = 50
200 × 10 − 6
97 (a) As, V = VCE + iCRC
105 (b) Integrated circuits are miniature electronic circuit produced
⇒ 15 = 7 + iC × 2 × 10 3
within a single crystal of a semiconductors such as silicon. They
8 contain a million or so transistors and resistors or capacitors.
⇒ iC = = 4 mA
2 × 10 3 They are widely used in memory circuits, micro computers,
pocket calculators and electronic watches, on account of their
iC
∴ β= low cost and reliability into specific regions of the
iB semiconductor crystals.
iC 4 106 (b) Figure in option (b) shows the equivalent diagram of n-p-n
or iB = = = 0.04 mA
β 100 transistor.
n
98 (a) By using, Vb = ibRb n p
Vb 9 E C
⇒ Rb = = = 257 kΩ
ib 35 × 10 −6
99 (a) At room temperature, due to thermal vibrations, the few ⇒ E n p n C

bonds of intrinsic semiconductor are broken and producing
equal number of electrons and holes in the semiconductor.
B
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Semiconductors

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semiconductors and insulators 4 Junction transistors

conductivity). 5 Analog and digital circuits

The values of ρ and σ given above are indicative of

Note If λ is the wavelength of radiation used in shifting the electron

filled from 2N electrons. Similarly, energy level 2p has Conductors (Metals)

Total states = 2N Eg > 3 eV

Fig. 14.6 Energy band gap for semiconductors Hole (Vacancy)

1. Intrinsic semiconductors Fig. 14.9 Energy band diagram for an intrinsic

Now, total number of current carrier

(c) Conductivity, σ = n h µ h e (c) Conductivity, σ = n e µ e e

The impurity (pentavalent) atoms are called donor atoms

more and more charge carriers (electron-hole pairs). This

= 4.54 × 109 / m3 Sol. Conductivity of semiconductor is given by

CHECK POINT 14.1

Thus, near the junction positive charge is built on n-side V 0.5

Depletion region (ii) According to work-energy theorem,

This set up a potential difference across the junction and m evi2 − 2 eV

Example 14.19 Find current passing through 4 Ω and 8 Ω R ′S

(ii) On reversing the connection of Ge diode, it will be

Reverse current (µA)

The voltage-current characteristic curves of a p-n junction 6

– – 6 This reverse saturation current depends only on

Working (v) Efficiency It is given by

same as that of AC.

3π and R L = load resistance.

(v) Ripple frequency The ripple frequency of full wave

Example 14.27 In a centre tap full wave rectifier, the value

1. Light emitting diode (LED) I (mA)

2. Photodiode Reverse bias

(i) Symbol Fig. 14.35 V-I characteristics of photodiode at different intensites

(ii) Construction (v) Uses

p n Fig. 14.41 V-I characteristics of a Zener diode

Output voltage (Vo )

CHECK POINT 14.2

n-type layers. Similarly, the p-n-p transistor has a n-type B

Type of junction transistors B

Important points related to transistor

(vi) In the connecting wires, electrons are always IE IC

The collector-base junction is reverse biased. The resistance Now, IE = IC + IB

current I E . As the base is very thin and lightly doped, a

40 Observation from the graph

 ∆V  Relation between α and β

Note Since, I C increases with IB almost linearly and I C = 0 when

Transconductance (g m ) Base current, ∆IB = 40 µA = 40 × 10−6 A

∴ 0.5 = ∆IC × 800 E VCE

Example 14.43 In the following circuit, the value of β is 200.

IC (ii) Base current amplification factor,

2. Construction Transistor as a switch

Now the operation of transistor as a switch can be

CHECK POINT 14.3

ANALOG AND DIGITAL CIRCUITS

Switch S1 Switch S2 Bulb A B C Logic system

(v) Commutative laws 1 0 1

OR Gate using diodes 2. AND gate

The following four cases are possible Logic symbol

Input and output waveforms for NOT gate 2. NOR gate

Logic symbol Input and output waveforms of XNOR gate

Logic symbol When B = A,

AND gate from NAND gate Truth table

The corresponding truth table is shown below

Example 14.61 Write the truth table for the circuit

CHECK POINT 14.4

17 p-type semiconductor is formed when 26 The symbol given in figure represents

51 Select the correct statement. 60 To use a transistor as an amplifier,

81 A 220 V AC supply is connected between points A 87 Which represents NAND gate?

88 What is the current in the circuit shown below?

Vm sin ωt (a) I, II, III (b) II, IV, V

20 V 15V 1k Ω 124 A researcher wants an alarm to sound when the

(a) ab (b) bc (c) cd (d) de

(B) Medical entrance special format questions

C 3 I. The resistivity of a semiconductor increases with

III. Zener diode works on a principle of breakdown Column I Column II

RL 500 Ω (B) Y = A⋅B (q) NOT gate

~ (C) Y=A (r) AND gate

Column I Column II Codes