STEF01

Datasheet

8 V to 48 V fully programmable universal electronic fuse

Features
• Operating input voltage range: 8 to 48 V
• Absolute maximum input voltage: 55 V
• Continuous current typ.: 4 A
• N-channel on-resistance typ.: 30 mΩ
• Enable/fault functions
HTSSOP14
• Output clamp voltage: adjustable from 10 to 52 V
• Programmable undervoltage lockout
• Short-circuit current limit
• Programmable overload current limit
• Adjustable soft-start time
Maturity status link • Latch or auto-retry thermal protection
STEF01 • Maximum allowable power protection
• Power Good
• Drives an optional external reverse current protection MOSFET
Device summary • Operating junction temperature -40 °C to 125 °C
Order code STEF01FTR • HTSSOP14 package
Package HTSSOP14
Packing Tape and reel Applications
• Hot board insertion
• Electronic circuit breaker/power busing
• Industrial/alarm/lighting systems
• Distributed power systems
• Telecom power modules

Description
The STEF01 is a universal integrated electronic fuse optimized for monitoring output
current and the input voltage on DC power lines.
When connected in series to the main power rail, it is able to detect and react
to overcurrent and overvoltage conditions. When an overload condition occurs, the
device limits the output current to a safe value defined by the user. If the anomalous
overload condition persists, the device goes into an open state, disconnecting the
load from the power supply.
The device is fully programmable. UVLO, overvoltage clamp and start-up time can be
set by means of external components.
The adjustable turn-on time is useful to keep the in-rush current under control during
startup and hot-swap operations. The device provides either thermal latch and auto-
retry protection modes, which are selectable by means of a dedicated pin.
The STEF01 provides a gate driver pin for an external power MOSFET to implement
a reverse-current blocking circuit. The intervention of the thermal protection is
signaled to the board monitoring circuits through a signal on the fault pin.

DS12147 - Rev 7 - April 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 STEF01
Device block diagram

1 Device block diagram

Figure 1. Block diagram

GIPD010220161057MT

DS12147 - Rev 7 page 2/27

 STEF01
Pin configuration

2 Pin configuration

Figure 2. Pin configuration (top view )

1 14

Expos e d
pa d

7 8
HTSSOP14 GIPD010220161207MT

Table 1. Pin description

Pin n° Symbol Note

A resistor divider connected between this pin, Vcc and GND sets the UVLO
1 UVLO
threshold. If left floating the UVLO is preset to 14.5 V.
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The
internal capacitor allows a ramp-up time of around 3 ms. An external capacitor can
2 dv/dt
be added to this pin to increase the ramp-up time. If an additional capacitor is not
required, this pin should be left open.
3 GND Ground pin.
This pin selects the thermal protection behavior. The device is set in latched mode
4 Auto when this pin is left floating or connected to a voltage higher than 1 V.
It is set in auto-retry mode when the pin is connected to GND.
A resistor divider connected between this pin, VOUT and GND sets the overvoltage
5 Vclamp
clamp level. If left floating the clamp is preset to 28 V.

6, 7, 8, 9 VOUT Output port. All the pins must be tied together with short copper tracks.

10 I-Limit A resistor between this pin and VOUT sets the overload current limit level.

11 Vg Gate driver output for the optional external reverse-blocking MOSFET.

Tri-state, bi-directional pin. During normal operation the pin must be left floating, or it
can be used to disable the output of the device by pulling it to ground using an open
drain or open collector device.
12 En/Fault If a thermal fault occurs, the voltage on this pin will go to an intermediate state to
signal a monitoring circuit that the device is in thermal shutdown. It can be connected
to another device of this family to cause a simultaneous shutdown during thermal
events.
13 PG Power Good flag. It is an open drain, to be pulled up through an external resistor.

14 VCC Input port. Connect this pin to the exposed pad.

Exposed pad. Input port of the device, internally connected to the power element
Exposed pad VCC
drain.

DS12147 - Rev 7 page 3/27

 STEF01
Maximum ratings

3 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Positive power supply voltage -0.3 to 55 V

VOUT/source Output voltage pin -0.3 to VCC V

I-Limit Current sense resistor pin -0.3 to VCC V

ID Continuous current 6 A

PG Power good flag pin -0.3 to VCC V

Vclamp, UVLO Vclamp, UVLO pins -0.3 to 7 V

En/Fault Enable/Fault pin -0.3 to 7 V
dv/dt Startup time selection pin -0.3 to 7 V
Auto Auto retry selection pin -0.3 to 7 V
Vg Gate driver pin -0.3 to 65 V
TJ Maximum junction temperature (1) 150 °C

TSTG Storage temperature range -65 to 150 °C

TLEAD Lead temperature (soldering) 10 s 260 °C

1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures
greater than the maximum ratings for extended periods of time.

Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.

Table 3. Recommended operating condition

Symbol Parameter Value Unit

Operating power supply voltage, steady state 8 to 48 V

VCC
Maximum power supply voltage, clamping active 52 V
RLimit Current sense resistor range (1) 8 to 1000 Ω

ID Continuous current 4 A

TJ Operating junction temperature -40 to 125 °C

1. Important: The RLimit resistor is mandatory in the application. Very low values of the RLimit or lack of connection of RLimit may
lead to malfunction of current limiting circuit and to device damage.

Table 4. Thermal data

Symbol Parameter HTSSOP14 Unit

Thermal resistance junction-ambient, 2 layer PCB 140

RthJA °C/W
Thermal resistance junction-ambient, 4 layer PCB 40
RthJC Thermal resistance junction-case 4 °C/W

DS12147 - Rev 7 page 4/27

 STEF01
Maximum ratings

Table 5. ESD performance

Symbol Parameter Test conditions Value Unit

HBM 2 kV
ESD ESD protection voltage
CDM 500 V

DS12147 - Rev 7 page 5/27

 STEF01
Electrical characteristics

4 Electrical characteristics

VCC = 24 V, VEN = floating, CI = 10 µF, CO = 47 µF, TJ = 25 °C (unless otherwise specified).

Table 6. Electrical characteristics for STEF01

Symbol Parameter Test conditions Min. Typ. Max. Unit

Under/over voltage protection

Output clamping voltage 28 V
VCC = 36 V, VClamp = floating
Accuracy -5 +5 %
VClamp
Output clamping voltage
With external resistor divider on Vclamp pin 10 52 V
range
Under voltage lockout
Turn on, voltage going up, UVLO = floating 13 14.5 16 V
threshold
VON
Under voltage lockout
With external resistor divider on UVLO pin 8 45 V
range
VHyst UVLO hysteresis 10 %

Power MOSFET

ID = 1 A (1) 30 50
RDSon ON resistance mΩ
-40 °C < TJ < 125 °C (2) 70

VOFF Off state output voltage VCC = 36 V, VGS = 0, RL = infinite 1 20 mV

Current limit
IShort Short circuit current limit RLimit = 22 Ω, VOUT = gnd 1.5 A

ILim Overload current limit RLimit = 22 Ω, VOUT = VCC - 2 V, VCC > 8 V 3.2 4 4.8 A

dv/dt circuit
Enable to VOUT = 22 V, No Cdv/dt 3

dv/dt Output voltage ramp time Enable to VOUT = 46 V, VCC = 48 V, VClamp = 52 V, ms

3.6
no Cdv/dt

Idv/dt dv/dt source pin current 100 nA

Enable/Fault
VIL Low level input voltage Output disabled 0 0.4 V

Intermediate level input

VI(INT) Thermal fault, output disabled 1.4 V
voltage
VIH High level input voltage Output enabled 2.8 5 V

High state maximum

VI(MAX) Pin floating 4.7 5 5.3 V
voltage
Low level input current
IIL VEnable = 0 V -20 -40 µA
(sink)
Maximum fan-out for fault Total number of chips that can be connected to this pin
5 Units
signal for simultaneous shutdown
Power Good

Power Good output VCC - VOUT value for Power Good 1

VD V
threshold Hysteresis 0.1
Power Good output
VL Isink = 6 mA open drain output 0.4 V
voltage low

DS12147 - Rev 7 page 6/27

 STEF01
Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

External MOS gate driver

Ig Sourcing current Device on 30 µA

Rp Strong pull down VEN = 0 V 450 Ω

Vg Gate driver voltage Vg-VOUT 8.5 9.5 10.5 V

Auto-retry function
Auto-retry activated 0.4
VAR Autoretry logic level V
Latched protection activated 1
Total device consumption
Device operational 0.4

IBias Bias current Thermal shutdown (2) 0.1 mA

Off state (VEN = GND) 0.1

Minimum operating
Vmin 8 V
voltage
Thermal shutdown

Shutdown temperature (2) 175

TSD °C
Hysteresis Only in auto-retry mode 25

1. Pulsed test.
2. Guaranteed by design, but not tested in production.

DS12147 - Rev 7 page 7/27

 STEF01
Typical application

5 Typical application

Figure 3. Application circuit

VIN Exp.pa d VOUT

Vcc VOUT
RP G S TEF01 R LIM
C IN RH R1 C OUT
ILIM
PG
UVLO VCLAMP
dV/dt AUTO
RL R2
C dv/dt
EN/Fa ult Vg
GND

GIPD010220161218MT

5.1 Operating modes

5.1.1 Turn-on and UVLO

The device features a programmable UVLO block. If the input voltage exceeds the UVLO ON threshold (VON), the
power pass element is turned on and the Enable/Fault pin goes up to the high state.
Figure 4. UVLO block simplified diagram shows the simplified diagram of the UVLO circuit. The voltage at the
UVLO pin is compared to an internal 1 V reference (0.9 V during turn OFF).
The default ON threshold is set by internal divider (RHD, RLD) to 14.5 V; the ID current flowing through the internal
divider is set to ~ 3 μA.
The UVLO threshold can be modified in accordance with power rail needs by adding the RH-RL resistor divider, as
shown in Figure 4. UVLO block simplified diagram. The external divider is in parallel with the internal default one,
therefore the threshold can be changed within the 8 V to 45 V range.

Figure 4. UVLO block simplified diagram

VIN VCC

RH R HD
UVLO
UVLO ON

RL IE ID R LD
VRe f

GND

GIPD010220161241MT

When the external divider is used, the ratio between external current IE and the internal current ID should be
kept as high as possible, to guarantee maximum linearity of the circuit with respect to temperature and process
variations.

DS12147 - Rev 7 page 8/27

 STEF01
Operating modes

Setting IE/ID > 10 provides sufficient UVLO linearity, at the same time keeping overall current consumption at
acceptable levels. Given the desired VON threshold, for a fixed value of the lower resistor RL, Equation 1 can be
used to calculate the upper resistor RH.
Equation 1
1
R H = -------------------------------------------------------------------
(1 / R L + 1 / 333 ) 1
------------------------------------------- – ------------------
( VO N – 1 ) 4500

(resistor values are expressed in kΩ)

Figure 5. UVLO threshold (VON) vs. RH, RL shows the relationship between RH and the UVLO turn ON threshold,
for some fixed values of RL.

Figure 5. UVLO threshold (VON) vs. RH, RL

RL=100k
10000 RL=50k
RL=33k
RL=20k
RL=10k

1000
RH [kΩ]

100

10
5 10 15 20 25 30 35 40 45 50

VON [V]

The resistor divider approach described above guarantees the best UVLO performance in terms of accuracy and
temperature dependance.
In order to reduce the application B.O.M., the 1-resistor approach can be used also, at the expenses of overall
UVLO circuit accuracy.
In this case, the RH resistor can be omitted for VON thresholds higher than 14.5 V, or RL for VON lower than 14.5
V.
In any case it is recommended to check that in all operating conditions, the UVLO threshold is never lower than 8
V, in order to guarantee correct operation.
After an initial delay time of typically 170 µs, the output voltage is supplied with a slope defined by the internal
dv/dt circuitry. If no additional capacitor is connected to the dv/dt pin, the total time from the Enable signal going
high and the output voltage reaching the nominal value is around 3 ms.

5.1.2 Normal operating condition

The STEF01 E-fuse provides the circuitry on its output with the same voltage shown at its input, with a small
voltage fall due to the N-channel MOSFET RDS-on.

5.1.3 Output voltage clamp

If the input voltage exceeds the Vclamp value, the internal protection circuit clamps the output voltage to Vclamp.
The overvoltage clamp threshold is preset to 28 V if the Vclamp pin is left floating, otherwise it can be externally
adjusted in the range of 10 to 52 V by connecting a resistor divider (R1,R2) of appropriate value between the
Vclamp pin, VOUT and GND.
The setting procedure is similar to that of UVLO, the internal divider current being fixed to 10 µA.
Given the desired Vclamp threshold, for a fixed value of the lower resistor R2, Equation 2 can be used to calculate
the upper resistor R1

DS12147 - Rev 7 page 9/27

 STEF01
Operating modes

Equation 2
1
R 1 = --------------------------------------------------------
–2
-
(1 / R 2 + 10 ) 1
------------------------------------- – -------------
( Vc la m p – 1 ) 2700
(resistor values are expressed in kΩ)
Figure 6. Clamping voltage (Vclamp) vs. R1, R2 shows the relation between R1 and the clamping voltage, for some
fixed values of R2.

Figure 6. Clamping voltage (Vclamp) vs. R1, R2

R2=100k
10000 R2=50k
R2=20k
R2=10k

1000
R1 [kΩ]

100

10
5 10 15 20 25 30 35 40 45 50 55

VCLAMP [V]

5.1.4 Current limit

The STEF01 embeds an overcurrent sensing circuit, based on an internal N-channel Sense FET with a fixed ratio,
used to monitor the output current (Figure 1. Block diagram).
The current limiting circuit responds to overcurrent events by reducing the conductivity of the power MOSFET, in
order to clamp the output current at a safe value.
The overcurrent protection trip-point can be selected externally by means of the limiting resistor RLimit, according
to the graphs in Section 5.1.4 Current limit and Figure 25. Current limit vs. Rlimit (zoom).
The circuit features two levels of current limitation, each one valid for a certain range of output voltage (VOUT).
In case of overload, when the input current surpasses the programmed overload current limit (ILIM), but the output
voltage is still higher than 5.5 V (typ.), the device clamps the current to the ILIM value.
If case of strong overload or short circuit, when the output voltage decreases to less than 3.5 V, the device
enters the foldback current limit, with the current limited to a lower value (ISHORT) that is typically 1.5 A when
RLimit = 22 Ω.

DS12147 - Rev 7 page 10/27

 STEF01
Protection circuits

Figure 7. Current limit vs. Rlimit

VIN=24V, C IN=C OUT=47µF, IOUT=from 0.5A to 8A, R LIM=from 10Ω to 1kΩ

12

Ilim
10 Is hort

Curre nt limit [A]

6

0
10 100 1000
Rlimit [Ω]

AMG180720171100MT

During startup, the foldback current limit is disabled and the current is limited by the overcurrent protection at the
ILIM value. Please refer also to Section 5.4 Maximum load at startup for more details.
It is important to note that the RLimit is mandatory for the current limiting circuit to function properly. It is
recommended to use RLimit value according to Section 3 and to the package power dissipation.
Important: very low values of RLimit or failure to connect it may lead to malfunctioning of the current limiting circuit
and to device damage.

5.2 Protection circuits

Since the power dissipation can reach remarkable levels during startup into heavy capacitive loads, large load
transients and short-circuit during operation at high voltage, the STEF01 is protected by means of two circuits: the
absolute thermal protection and the maximum power dissipation protection.

5.2.1 Thermal protection

The thermal protection is a standard thermal shutdown feature, which acts when the die temperature exceeds the
absolute shutdown threshold, set typically to 175 °C.
The behavior of the STEF01 at thermal protection intervention can be changed by the user through the external
Auto pin. This pin is internally pulled up.
When the Auto pin is left floating or connected to a voltage higher than 1 V, the thermal protection works as
latched. If the device temperature exceeds the thermal shutdown threshold, the thermal shutdown circuitry turns
the power MOSFET off, disconnecting the load. The EN/Fault pin of the device will be automatically set at an
intermediate voltage, typically 1.4 V, in order to signal the overtemperature event.
The E-fuse can be reset either by cycling the supply voltage or by pulling down the EN pin below the VIL threshold
and then releasing it.
When the AUTO pin is connected to GND or to a voltage lower than 0.4 V, the thermal protection works as
auto-retry. Once the thermal protection threshold is reached, the power is turned off and remains in an off state
until the die temperature drops below the hysteresis value. Once this occurs, the internal auto-retry circuit initiates
a new startup cycle, with controlled dv/dt. During the shutdown period, the EN/Fault pin of the device will be
automatically set to 0 V.

5.2.2 Maximum dissipated power protection

Besides the standard thermal shutdown described in Section 5.2.1 Thermal protection, which acts when the
die temperature surpasses the absolute shutdown threshold, the STEF01 is equipped with advanced thermal
protection, which limits the thermal power dissipated into the device. When the power dissipation is higher than
the internal limit, the power transistor is turned off.
The power protection always acts in auto-retry mode, regardless of the Auto pin status. Its intervention is signaled
on the EN/FAULT pin with a LOW logic state. If the fault persists, the die temperature may reach the thermal
protection limit. If this happens, the device behavior is the one fixed by the user through the Auto pin signal.
The maximum dissipated power protection is able to protect the device from very fast overheating events, such as
those caused by a short circuit on the output during operation.

DS12147 - Rev 7 page 11/27

 STEF01
Soft start function

5.3 Soft start function

The inrush current profile is controlled through a dedicated soft-start circuit. The startup time is set by default at
3 ms (typ.) and it can be prolonged by connecting a capacitor between the Cdv/dt pin and GND. Figure 8. Startup
time illustrates the turn-on sequence.
The turn-on time is defined as the time interval tΟΝ between assertion of the enable signal and the Vout reaching
the (VOUT(NOM)-2 V) voltage. The turn-on time is a function of the Cdv/dt capacitor, the input voltage VCC and the
clamping voltage VClamp.
Given the Cdv/dt external capacitor value, the turn-on time can be estimated using Equation 3 and the graph in
Figure 9. Startup time vs. CdV/dt, valid for normal operating conditions (VCC < VClamp). In case the startup occurs
with power supply voltage higher than the clamping voltage (VCC > VClamp), the total startup time will be longer.
The equation is meant as a theoretical aid in choosing the Cdv/dt capacitor, and does not take into account the
capacitor tolerance, temperature and process variations.
Equation 3

VC C ( 300 + C d vd t )
t O N = 0.952 ⋅ ------------------- ⋅ ----------------------------------- + t d e la y
VC la m p 113000

where time is expressed in [s] and the capacitor in [pF]; tdelay ~ 170 µs, is the initial delay time.

Figure 8. Startup time Figure 9. Startup time vs. CdV/dt

1000

Vcc=24V
Vcc=48V
Vcla mp

VOUT 100
VIN
S ta rtup time [ms ]

VIN - 2V
EN/FAULT

10

ra mp-up time – VIN>VCla mp

1
de la y time (tde la y) ra mp-up time – VIN<VCla mp 1 10 100 1000 10000 100000

dv/dt Ca pa citor [pF]

CIN = COUT = 22 μF, IOUT = 0 mA, RLIM = 11 Ω, VCLAMP = 52 V for VCC = 48 V,
or VCLAMP = 28 V for VCC = 24 V

GIPD020220160934MT GIPD020220160935MT

5.4 Maximum load at startup

The power limiting function described in Section 5.2.2 Maximum dissipated power protection is designed to
provide fast and effective protection for the internal FET.
Depending on supply voltage and load, it is possible that during startup the power dissipation is such that the
maximum power protection is triggered and the output is shut down before the startup is complete. The EN/Fault
signal is set according to Table 7. Enable/Fault pin behavior during thermal protection events.
In case of strong capacitive loads, the total startup time may be longer than the programmed startup time, since it
is dependent also on the limitation current, the output load and the output capacitance value. In such a situation,
the foldback current limit could activate, so that the startup is longer or eventually interrupted by the intervention
of thermal protection.
To avoid this occurrence, a longer startup time should be set by the appropriate selection of the Cdv/dt capacitor.

5.5 Enable-fault pin

The Enable/Fault pin has the dual function of enabling/disabling the device and, at the same time, providing
information about the device status to the application. The EN/Fault signal can be provided to a monitoring circuit
to control the status of device.
It can be used as a standard Enable pin, (HI = enable, LO = disable) or connected to an external open-drain or
open-collector device.

DS12147 - Rev 7 page 12/27

 STEF01
Power Good function

The EN/fault pin is internally pulled up to 5 V, therefore the device is enabled if the pin is left floating. In case of a
thermal fault, the pin is pulled to an intermediate state, with a voltage of 1.4 V (typ.) (see Section 5.1.1 ).
The EN/Fault signal can be directly connected to the Enable/Fault pins of other STEF01 devices on the same
application in order to implement a simultaneous enable/disable feature.
When a thermal fault occurs, the latch version can be reset either by cycling the supply voltage or by pulling down
the Enable pin below the VIL threshold and then releasing it.
In the auto-retry operating mode, the power MOSFET remains in an off state until the die temperature drops
below the hysteresis value. The EN/Fault pin is set to a low logic level and the auto-retry circuit attempts to restart
the device with soft start.
In case of power limit intervention, the EN/Fault pin is set to low logic level also. The following truth table and
the graph in Figure 10. Enable/Fault pin status summarize the device behavior and the EN/Fault signal in all
conditions.

Table 7. Enable/Fault pin behavior during thermal protection events

Maximum power protection

Auto pin logic level Thermal protection status EN/Fault pin status Output voltage
status

High 0 0 5V ON
High 1 X 1.4 V OFF
High 0 1 0V OFF
Low 0 0 5V ON
Low 1 X 0V OFF
Low 0 1 0V OFF

Note: Maximum power protection always auto-retries (see Section 5.2.2 Maximum dissipated power protection).

Figure 10. Enable/Fault pin status

5.6 Power Good function

Most applications require a flag showing that the output voltage is in the correct range. This function is achieved
through the Power Good (PG) pin. The Power Good function on the STEF01 is accomplished by monitoring the
voltage drop on the power pass element, Vd = VCC-VOUT.
Whenever the VD is lower than 1 V, the PG pin is in high impedance. If VD is higher than 1 V, the PG pin goes to
low impedance; therefore if either the device is functioning well or the EN pin is in low state, the PG pin is at high
impedance.
The PG pin is an open drain pin, so it requires an external pull-up resistor, which must be connected between the
PG pin and the desired high level voltage reference. The typical current capability of the PG pin is up to 6 mA. If
the Power Good function is not used, the PG pin must remain floating.

DS12147 - Rev 7 page 13/27

 STEF01
Gate driver for reverse current blocking FET

5.7 Gate driver for reverse current blocking FET

Many applications require reverse current blocking (from load to input source) to permit the completion of
important system activities or writing data to non-volatile memory prior to power down or during brownout. The
STEF01 provides a Vg pin suitable to control an external blocking N-channel FET, connected back-to-back with
the internal one, as shown in Figure 11. STEF01 with external reverse blocking FET.

Figure 11. STEF01 with external reverse blocking FET

M1
VIN Exp.pa d VOUT
Vcc VOUT
RP G R LIM
C IN RH S TEF01 R1 C OUT C LOAD LOAD
ILIM
PG
VCLAMP
UVLO
dV/dt R2
RL AUTO
C dv/dt
EN/Fa ult Vg
GND

GIPD020220160956MT

As VIN drops during input power removal, the internal logic pulls the gate of the external MOSFET down, therefore
both the internal pass element and the external MOSFET are turned off, blocking any current flow from the load
to the power supply. In this case, the CLOAD value is chosen according to the charge needed to complete the
required operations.
The typical sourcing current of the Vg driver is 30 µA, with a voltage of 10 V compared to VOUT. Therefore, when
a low threshold MOSFET is used, the Vg must be clamped by means of a suitable external clamping diode.
When the EN pin is low, the external M1 FET is kept off by a 40 Ω internal pull-down so that the device is disabled
by the user or by internal protection circuits.

5.8 External capacitors and application suggestions

Input and output capacitors are mandatory to guarantee device control loop stability and reduce the transient
effects of stray inductances which may be present on the input and output power paths. In fact, when the STEF01
interrupts the current flow, input inductance generates a positive voltage spike on the input, and output inductance
generates a negative voltage spike on the output. To reduce the effects of such transients, a CIN capacitor of at
least 10 µF must be connected between the input pin and GND, and located as close as possible to the device.
For the same reason, a COUT capacitor of at least 47 µF must be connected at the output port.
In the event of a voltage clamp, with certain combinations of parasitic elements on the application, some small
oscillations may be visible on the output voltage. This phenomenon does not affect device operation and can be
mitigated by using an electrolytic capacitor for the CIN.
When the device is powered via a power line made up of very long wires, where input inductance is higher than
3-4 µH, the input capacitor should be increased to 47 µF or more.
Additional protections and methods for addressing these transients are:
• Minimizing inductance of the input and output tracks
• TVS diodes on the input to absorb inductive spikes
• Schottky diode on the output to absorb negative spikes
• Combination of ceramic and electrolytic capacitors on the input and output

DS12147 - Rev 7 page 14/27

 STEF01
Typical performance characteristics

6 Typical performance characteristics

(The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 °C)

Figure 12. Clamping voltage vs. temperature Figure 13. UVLO voltage vs. temperature

50 20
Von
45
18 Voff
40 Vin=9V, Vcla mp=8V
Vin=36V, Vcla mp=28V
35 16
Vin=48V, Vcla mp=45V

UVLO thre s ho ld [V]

Vin=16V, Vcla mp=14V
30
VCLAMP [V]

14
25
12
20

15 10

10
8
5

0 6
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Te mpe rature [ºC] Te mpe rature [ºC]

IOUT = 10 mA,VIN = from 10 V to 16 V, Vclampset to 14 V

AMG180720171130MT AMG180720171131MT

Figure 14. Auto pin thresholds vs. temperature Figure 15. Off-state current vs. temperature

1000 300
AUTO
LATCH
900 250
VAR thre s ho ld [mV]

800 200
IBIAS _Off [µA]

700 150

600 100

500 50

400 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Te mpe rature [ºC] Te mpe rature [ºC]

VIN = 48 V , VEN = GND

AMG180720171132MT AMG180720171133MT

Figure 16. Bias current (device operational) Figure 17. ON resistance vs. temperature

1000 80

VIN=48V VIN=24V
900 70
VIN=24V VIN=48V

800 60

700 50
RDS _ON [mΩ]
IBIAS [µA]

600 40

500 30

400 20

300 10

200 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Te mpe rature [ºC] Te mpe rature [ºC]

IOUT= 1 A
AMG180720171134MT AMG180720171135MT

DS12147 - Rev 7 page 15/27

 STEF01
Typical performance characteristics

Figure 18. ON resistance vs. load current Figure 19. dv/dt pin current vs. temperature

60 140
125°C
55 VCC=24V
25°C 130
VCC=55V
50 -40°C
120
45
110
RDS _ON [mΩ]

40

Idv/dt
35 100

30
90
25
80
20
70
15

10 60
0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 150
Lo ad c urre nt [A] Te mpe rature [ºC]

AMG180720171136MT AMG180720171137MT

Figure 20. External gate driver pull-down resistance Figure 21. External gate driver voltage

800 12

11.5
700
11

10.5
600
Vg – VOUT [V]

10
RP [Ω]

500 9.5

9
400
8.5

8
300
7.5

200 7
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Te mpe rature [ºC] Te mpe rature [ºC]

AMG180720171138MT AMG180720171139MT

Figure 22. External gate driver current (source) vs. Figure 23. Low level En/Fault pin current (sink)
temperature vs. temperature

50 40

45
35
40
30
35
25
30
Ig [µA]

Ig [µA]

25 20

20
15
15
10
10
5
5

0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Te mpe rature [ºC] Te mpe rature [ºC]

AMG180720171140MT AMG180720171141MT

DS12147 - Rev 7 page 16/27

 STEF01
Typical performance characteristics

Figure 24. En/Fault pin voltage vs. temperature Figure 25. Current limit vs. Rlimit (zoom)

VI(MAX) (chip e na ble d)

5
Enable /fault vo ltag e [V]

3
VIH (Ena ble high thre s hold)

2
VI(INT) (Fa ult s ta tus )

0
-50 -25 0 25 50 75 100 125 150
Te mpe rature [ºC]
VIN = 24 V, CIN = COUT = 47 μF, IOUT = from 0.5 A to 8 A,
RLIM = from 10 Ω to 50 Ω
AMG180720171142MT AMG180720171143MT

Figure 26. VOUT ramp-up vs. Enable Figure 27. VOUT clamping (28 V)

Figure 28. VOUT clamping (44 V) Figure 29. Response to overload (latch)

DS12147 - Rev 7 page 17/27

 STEF01
Typical performance characteristics

Figure 30. Response to overload (autoretry) Figure 31. UVLO

Figure 32. Enable turn-on with external FET Figure 33. Enable turn-off with external FET

DS12147 - Rev 7 page 18/27

 STEF01
Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 HTSSOP14 package information

Figure 34. HTSSOP14 package outline

BOTTOM VIEW

SIDE VIEW

TOP VIEW 7256412

DS12147 - Rev 7 page 19/27

 STEF01
HTSSOP14 package information

Table 8. HTSSOP14 mechanical data

mm
Dim.
Min. Typ. Max.

A 1.00 1.10 1.20

A1 0.05 0.10 0.15
A2 0.80 1.00 1.05
b 0.19 0.25 0.30
c 0.09 0.25
D 4.90 5.00 5.10
D1 3.00 3.20
E 6.20 6.40 6.60
E1 4.30 4.40 4.50
E2 3.00 3.20
e 0.65 BSC
L 0.45 0.60 0.75
L1 0.95 1.00 1.05
k 0 8
aaa 0.10

Figure 35. HTSSOP14 recommended footprint

DS12147 - Rev 7 page 20/27

 STEF01
HTSSOP14 packing information

7.2 HTSSOP14 packing information

Figure 36. HTSSOP14 carrier tape outline

Table 9. HTSSOP14 carrier tape mechanical data

Dim. Value (mm)

Ao 6.8 ±0.1
Bo 5.4 ±0.1
Ko 1.6 ±0.1
Ki 1.3 ±0.1
F 5.5 ±0.05
P1 8.0 ±0.1
W 12.0 ±0.3

DS12147 - Rev 7 page 21/27

 STEF01
HTSSOP14 packing information

Figure 37. HTSSOP14 reel outline (dimensions are in mm)

DS12147 - Rev 7 page 22/27

 STEF01

Revision history
Table 10. Document revision history

Date Revision Changes

04-Aug-2017 1 Initial release.

15-Feb-2018 2 Update: ID value Table 2. Absolute maximum ratings.

24-May-2018 3 Updated maturity status link on the cover page.

13-Jul-2018 4 Updated pin 11 note Table 1. Pin description.
Updated VIL, VIH and VI(MAX) values in Table 5. Electrical characteristics
01-Oct-2018 5
for STEF01.
Added new Figure 37. HTSSOP14 reel outline (dimensions are in mm).
19-May-2020 6
Updated Figure 5 and Figure 6.
Updated Note in Table 2
29-Apr-2022 7
Added new Table 5. ESD performance.

DS12147 - Rev 7 page 23/27

 STEF01
Contents

Contents
1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 Turn-on and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.4 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Protection circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.1 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.2 Maximum dissipated power protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Soft start function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Maximum load at startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5 Enable-fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6 Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.7 Gate driver for reverse current blocking FET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8 External capacitors and application suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.1 HTSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 HTSSOP14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

DS12147 - Rev 7 page 24/27

 STEF01
List of tables

List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 5. ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 6. Electrical characteristics for STEF01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 7. Enable/Fault pin behavior during thermal protection events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. HTSSOP14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. HTSSOP14 carrier tape mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DS12147 - Rev 7 page 25/27

 STEF01
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin configuration (top view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. UVLO block simplified diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. UVLO threshold (VON) vs. RH, RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Clamping voltage (Vclamp) vs. R1, R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Current limit vs. Rlimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Startup time vs. CdV/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Enable/Fault pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. STEF01 with external reverse blocking FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Clamping voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. UVLO voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Auto pin thresholds vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Off-state current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. Bias current (device operational). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. ON resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. ON resistance vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. dv/dt pin current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. External gate driver pull-down resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21. External gate driver voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. External gate driver current (source) vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Low level En/Fault pin current (sink) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. En/Fault pin voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. Current limit vs. Rlimit (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 26. VOUT ramp-up vs. Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27. VOUT clamping (28 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28. VOUT clamping (44 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 29. Response to overload (latch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 30. Response to overload (autoretry) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 31. UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 32. Enable turn-on with external FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 33. Enable turn-off with external FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 34. HTSSOP14 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 35. HTSSOP14 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 36. HTSSOP14 carrier tape outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 37. HTSSOP14 reel outline (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DS12147 - Rev 7 page 26/27

 STEF01

IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved

DS12147 - Rev 7 page 27/27