Computer Bus Architecture Nov 2024

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COMPUTER BUS ARCHITECTURE

Introduction
This unit introduces us to the Bus Architecture of a computer. A bus is a common
pathway to connect various subsystems in a computer system. A bus consists of the
connection media like wires and connectors, and a bus protocol.
Lesson Objectives
By the end of this unit, you will be able:
∙ To explain the definition of computer architecture
∙ To discuss the history of computers
∙ To discuss how to measure the quality of a computer architecture and the factors
that influence the success of a computer architecture
Bus Architecture
A bus in computer terminology represents a physical connection used to carry a signal from one
point to another. The signal carried by a bus may represent address, data, control signal, or power.
Typically, a bus consists of a number of connections running together. Each connection is called
a bus line. A bus line is normally identified by a number. Related groups of bus lines are usually
identified by a name. For example, the group of bus lines 1 to 16 in a given computer system
may be used to carry the address of memory locations, and therefore are identified as address
lines. Depending on the signal carried, there exist at least four types of buses: address, data,
control, and power buses. The diagram below shows the system bus model of a computer system.

Computer Bus Architecture


The Data Bus provides a path for moving data among system modules. The data bus may consist
of 32, 64, 128, or even more separate lines, the number of lines being referred to as the width of
the data bus. Because each line can carry only 1 bit at a time, the number of lines determines
how many bits can be transferred at a time. The width of the data bus is a key factor in
determining overall system performance. In any case, the bus width is the size of information
that can be communicated along the bus: For example, if the data bus is 32 bits wide and each
instruction is 64 bits long, then the processor must access the memory module twice during each
instruction cycle. Some systems have separate data buses for moving information to and from
the CPU, in which case there is a data-in bus and a data-out bus. More often a single data bus
moves data in either direction, although never both directions at the same time.

BUS WIDTH - The width of the data bus has an impact on system performance: The wider the
data bus, the greater the number of bits transferred at one time. The width of the address bus has
an impact on system capacity: the wider the address bus, the greater the range of locations that
can be referenced.

The address bus indicates the source or destination of the data on the data bus. For example, if
the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the address
of the desired word on the address lines to a memory address. A memory address, or location,
identifies a memory location where data is stored, similar to the way a postal address identifies
the location where a recipient receives and sends mail. During a memory read or write
operation the address bus contains the address of the memory location where the data is to be
read from or written to. Note that the terms “read” and “write” are with respect to the CPU:
the CPU reads data from memory and writes data into memory. If data is to be read from
memory then the data bus contains the value read from that address in memory. If the data is to
be written into memory then the data bus contains the data value to be written into memory

The control bus is used to control the access to and the use of the data and address lines.
Because the data and address buses are shared by all components, there must be a means of
controlling their use. Control signals transmit both command and timing information among
system modules. Timing signals indicate the validity of data and address information.
Command signals specify operations to be performed. Typical control lines include:
• Memory write: Causes data on the bus to be written into the addressed location
• Memory read: Causes data from the addressed location to be placed on the bus
• I/O write: Causes data on the bus to be output to the addressed I/O port
• I/O read: Causes data from the addressed I/O port to be placed on the bus
• Transfer ACK: Indicates that data have been accepted from or placed on the bus
• Bus request: Indicates that a module needs to gain control of the bus
• Bus grant: Indicates that a requesting module has been granted control of the bus
• Interrupt request: Indicates that an interrupt is pending
• Interrupt ACK: Acknowledges that the pending interrupt has been recognized
• Clock: Is used to synchronize operations
• Reset: Initializes all modules
Power Bus
The computer power bus serves as a critical component for distributing electrical power within
a computer or electronic device. Its primary function is to ensure that all components receive the
correct voltage and current required for their operation. Below is an explanation of its key
aspects:
Power Distribution
• The power bus system distributes electricity from the power supply unit (PSU) to various
components like the motherboard, CPU, GPU, storage drives, and peripherals.
• It typically operates on multiple voltage levels, such as +12V, +5V, and +3.3V, catering to
different hardware requirements.
Voltage Regulation
• The system often includes regulators to ensure a stable power supply, as fluctuations can
damage sensitive electronic components or cause system instability.
• Voltage converters, such as DC-DC converters, are integrated into the power bus system to
adapt the power for specific components

Factors that influence the success of a computer architecture

Buses are low cost but very versatile, and they make it easy to connect new devices to each other
and to the system. At any one time, only one device (be it a register, the ALU, memory, or some
other component) may use the bus. However, this sharing often results in a communications
bottleneck. The speed of the bus is affected by its length as well as by the number of devices
sharing it.

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