MPMC - 4.1 8051 IO Ports

4.
1 8051 IO Ports
4.1 8051 IO Ports
Module:4 Microcontroller 8051 Peripherals

Course: BECE204L – Microprocessors and Microcontrollers
4.1 8051 IO Ports
Module:4 Microcontroller 8051 Peripherals
• I/O Ports, Timers-Counters, Serial Communication and Interrupts.
Mohammad Ali Mazidi, Janice G. Mazidi, Rolin D. McKinlay, The 8051 Microcontroller and
Embedded Systems, 2014, 2nd Edition, Pearson, India.
4.1 8051 IO Ports
1. 8051: IO Ports
4.1 8051 IO Ports
4.1 8051 IO Ports
4.1 8051 IO Ports
1. 8051: IO Ports
• All 8051 microcontrollers have 4 I/O ports each comprising 8 bits
which can be configured as inputs or outputs.
• In total of 32 input/output pins enabling the microcontroller to be
connected to peripheral devices are available for use.
• Pin configuration, i.e. whether it is to be configured as an input (1) or an
output (0), depends on its logic state.
• When the first 0 is written to a port, it becomes output port.
For reconfiguring it as input, 1 must be sent to the port (programmed)
• All the ports upon RESET are configured as input, ready to be used as
input ports
4.1 8051 IO Ports
1.1 PORT - 0
• Port 0 occupies a total of 8 pins (pins 32-39). It can be used for
input or output.
• To use the pins of port 0 as both input and output ports, each pin
must be connected externally to a 10K ohm pull-up resistor. This
is due to the fact that P0 is an open drain, unlike P1, P2, and P3.
• Dual role of port-0: Port 0 is also designated as AD0-AD7, allowing
it to be used for both address and data. When ALE = 0, it provides
data D0-D7, but when ALE =1 it has address and data with the help
of a 74LS373 latch.
4.1 8051 IO Ports
1.1 PORT - 0
4.1 8051 IO Ports
1.2 PORT - 1
• Port 1 occupies a total of 8 pins (pins 1 through 8). ‰
Port 1 can be
used as input or output
• In contrast to port 0, this port does not need any pull-up resistors
since it already has pull-up resistors internally
• Upon reset, port 1 is configured as an input port
• To make port 1 an input port, it must be programmed as such by
writing 1 to all its bits
4.1 8051 IO Ports
1.3 PORT - 2
• Port 2 occupies a total of 8 pins (pins 21- 28). It can be used as
input or output. Upon reset, Port 2 is configured as an input port.
• Just like P1, P2 does not need any pull-up resistors since it
already has pull-up resistors internally.
• In many 8051-based system, P2 is used as simple I/O
but in 8031-based systems, port 2 must be used along with P0 to
provide the 16-bit address for the external memory
• Port 2 is also designated as A8 –A15, indicating its dual function
and Port 0 provides the lower 8 bits via A0 –A7.
4.1 8051 IO Ports
1.4 PORT - 3
• Port 3 occupies a total of 8 pins, pins 10 through 17.
• It can be used as input or output.
Upon reset, Port 3 is configured as an input port.
• P3 does not need any pull-up resistors, the same as P1 and P2
did not.
• Port 3 has the additional function of providing some extremely
important signals such as interrupts.
4.1 8051 IO Ports
1.4 PORT - 3
4.1 8051 IO Ports
2.1 Pins current limitation

• When configured as outputs (logic zero (0)), single port pins can
receive a current of 10mA.
• If all 8 bits of a port are active, a total current must be limited to
15mA (port P0: 26mA).
• If all ports (32 bits) are active, total maximum current must be
limited to 71mA.
• When these pins are configured as inputs (logic 1), built-in pull-up
resistors provide very weak current, but strong enough to activate
up to 4 TTL inputs of LS series.
4.1 8051 IO Ports
2.2 LOGICAL STRUCTURE OF 8051 I/O

PORTS
PORT – 1, 2 & 3 PORT - 0

4.1 8051 IO Ports
2.3a Writing 0 to port (output port )

• Internal CPU
bus provides
logic as 0 here.
• When clock
is initiated,
Q becomes 0,
𝑄 becomes 1,
Transistor
is in saturation,
Switch ON state,
Port pin is grounded to 0.
4.1 8051 IO Ports
2.3b Writing 1 to port (output port)

• Internal CPU
bus provides
logic as 1 here.
• When clock
is initiated,
Q becomes 1,
𝑄 becomes 0,
Transistor
is in cutoff,
Switch OFF state,
Port pin is open,
No o/p current,
Vcc(1) at Port pin.
4.1 8051 IO Ports
2.3c Reading the latch (status of output previously

provided by CPU – in both cases of 0 or 1)
• In both cases, when output is provided after clock, Q holds the
status (as 0 or 1)
When read latch is enabled, this Q output of flipflop is read back
through same internal bus by the processor. This is called reading
the latch.(status of output provided previously by the processor)
4.1 8051 IO Ports
2.4a Reading the port (when 1 is external input)

• To read input
Internal CPU bus
sends 1 to D input,
which makes 𝑄=0.
This cuts off Transistor.
• Now: when
external input = 1,
Read PIN is enabled,
(in buffer)
to read external input at
internal CPU bus
4.1 8051 IO Ports
2.4b Reading the port (when 0 is external input)

• To read input
Internal CPU bus
sends 1 to D input,
which makes 𝑄=0.
This cuts off Transistor.
• Now: when
external input = 0,
Read PIN is enabled,
(in buffer)
to read external input at
internal CPU bus.
4.1 8051 IO Ports
2.5 Difference between reading a port (port pin is

input) vs reading a latch (output sent by CPU)
• There is a difference between reading a latch and reading the output
port pin.
• Reading a latch: Usually the instructions that read the latch,
read a value,
possibly change it,
and then rewrite it to the latch.
These are called "read-modify-write" instructions. Examples are-
• ORL P2, A; P2 <-- P2 or A (OR logic)
• In this the latch value of P2 is read, is modified and is then written
back to P2 latch.
4.1 8051 IO Ports

• "read-modify-write" instructions. Examples are-
4.1 8051 IO Ports

• Reading a port: (with port Pin as input) is performed as
- Read a port pin (input value,
- Perform other activities with it without affecting the port pin value.
4.1 8051 IO Ports
3. 8051 I/O PORTS & SFR

BIT AND BYTE ADDRESS LOCATIONS
Ports are SFRs
• Port 0: Address 80H
• Port 2: Address 0A0H
• Port 3: Address 0B0H
4.1 8051 IO Ports

Ports are SFRs
• Port 2: Address 0A0H
• Port 3: Address 0B0H
4.1 8051 IO Ports

PORT 0 BITS P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
BIT ADDRESS 87H 86H 85H 84H 83H 82H 81H 80H
BIT ADDRESS 97H 96H 95H 94H 93H 92H 91H 90H
BIT ADDRESS A7H A6H A5H A4H A3H A2H A1H A0H
BIT ADDRESS B7H B6H B5H B4H B3H B2H B1H B0H
4.1 8051 IO Ports
IO Program: 01
4.1 8051 IO Ports
IO Program: 02
• The following code will continuously send out to port 1 the
alternating value 55H and AAH.
4.1 8051 IO Ports
IO Program: 02 : Another way

4.1 8051 IO Ports
IO Program: 03
4.1 8051 IO Ports
IO Program: 04
4.1 8051 IO Ports
IO Program: 05
4.1 8051 IO Ports
IO Program: 06
4.1 8051 IO Ports
IO Program: 07

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4.

4.1 8051 IO Ports

Module:4 Microcontroller 8051 Peripherals

Module:4 Microcontroller 8051 Peripherals

• I/O Ports, Timers-Counters, Serial Communication and Interrupts.

2.1 Pins current limitation

2.2 LOGICAL STRUCTURE OF 8051 I/O

PORT – 1, 2 & 3 PORT - 0

2.3a Writing 0 to port (output port )

2.3b Writing 1 to port (output port)

2.3c Reading the latch (status of output previously

2.4a Reading the port (when 1 is external input)

2.4b Reading the port (when 0 is external input)

2.5 Difference between reading a port (port pin is

2.5 Difference between reading a port (port pin is

2.5 Difference between reading a port (port pin is

3. 8051 I/O PORTS & SFR

3. 8051 I/O PORTS & SFR

3. 8051 I/O PORTS & SFR

IO Program: 02 : Another way

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