ADC Dnc

Tbigital to Analog
to Digital
Analog
Converter Converter
Resistor to PAMP
Combination
ADC DAC

1 Countertype ADC C Weighted Resistor DAC

z SAR type ADC 2 R 2R ladder
type
A DAC
3 Dual Slope Integrating Dc
Voltage
4 Flash Apc
type Ifunirtiunegging

Current

Basic Concepts

DAC

1 Resolution It is the change in analog output

to one LSB incremental input
corresponding
Resolution
IslepSize
2 bit DAC
of Vr 2h 1 s 3D Vr
2bit DAC
I s yr
3
Binary 3D
D
2 bit
DA C
YI
lo 20 1D
2 Vr
f O s
D VI
2h I
00 0

Resolution stepsize D V Reference

voltage

OHM INSTITUTE, Hyderabad

 i Resolution Step size

D Vr
2h I

2 Full Scale Voltage is the maximum

analog output possible

Ves Vr
for
3
Analog output any binary
in a DAC
input

Va Decimal equivalent Resolution

of binary

1k Eid x s

3 bit DAC with referencevoltage 7

For a

is
find analog output when input
9 O lo

b 110

D VI 7 IV
2 I 23 I
a 010
Va 2 l 2V

b 110 Va 6 I GV

OHM INSTITUTE, Hyderabad

 It theanalog output corresponding
to tool in a DAC is 4.5V ther
find analog output when input is
1110

Va dec eg of binary x Ree

45 9 x s
D 05 V

Va ly os II

Full scale output

n bit DAC
G
Vps Vana F
fry
Ves Vr

4 Resolution

A loot
Y Resolution
UFS
Vr
n
2 1 X loot
Vr

ft
Resolution
alone

OHM INSTITUTE, Hyderabad

5 Maximum possible error in a DAC Resolution

maximum
6 guantisation err or I

D Stepsize Resolution

ADC Analog Apc Binary

1 Resolution
Range Vma Vmin

Resolution Range Vma Vmin

2h I 2 I

Resolution Lon

DAC
Resistor DAC
1
Weighted type
ladder DAC
2 R 212 type
1 Inv
Voltage 2 Non Inv

3 Current

hair
Resistive Amplifier
Nlw

OPAMP

OHM INSTITUTE, Hyderabad

 Weight
R 2R 4R
2 R 2R
R E2R
NSB
Resistor
bzbib Weighted type DAC
sB
DX Rf 4 MSB
3bit MSB
Mm LL x
Rel Res
R x x
b2
mm LSB 1
X MSB
OV 2
te Vo Regis Resistance
mm2R
Eb
t 412
te
I
mm Analog
L
output
Ebo TusB
Switch
Vr logic 1
Vr o
A Binary IIP logico

o Voz t VOI t Voo

bak t blunt bow

4ft

Rat Vr bat
4
3kt Dac

4kt 2b
Va RRI hey boy

4 2 I
b b bo 3ha't
binary
Decimal eq bot 2b t 462
n l

OHM INSTITUTE, Hyderabad

 ra
g is
aibi7va
n.ba C

iJf E.iaibiIlaY
Y
n
t Gain of
amplifier
Decimifaegyot Resolution for
n bit weighler
Resistor DAC

1 General DAC
Resolution Vr
2 I

2 Weighted
Resistor DAC

Resolution Vr
n l
2

3 Re 2R ladder type DAC

Resolution Vr
2
x x

LSB Ms B Resistance
Resistance

Large range of
resistances
Disadvantage
are required

OHM INSTITUTE, Hyderabad

 R 2R Ladder type DAC

R 2 R Ladder
with a grounded 2R resistor
R 2R ladder will start
will act as LSB
and a Ill 2R resistor which
and will end with a
2R resistor which
acts as MSB
R R
mm Thevenin
X mm
zpladdt
37 2K
K
s
2K are RI R
bo b bz
L L T MSB
t t
LSB
Vr

rn

nm
f FI egtYfEn

Hn
I
R R R
m m

ar I ar 2K
ar
z
z
16V 16V
T T MSB

OHM INSTITUTE, Hyderabad

 T l MSB
LSB
4 bit R 2K ladder
Vr binary 1
binary 0 binary
o

ti
fifi Hn 5
Yg
5V
R
mm

5V Of

OHM INSTITUTE, Hyderabad

 R 2R Ladder
type
DAC Non
inverting
DAC
3bit
Rf
nm

R
mm
iz
t Vo
p

Em Ia
bo bi bz
d d
te t k
Vr Rf

7 I to
nm
Rtg Vth
Uts

Vo Vin H Raf

v
I bi
Fn t'ff
Y p t
Dec egof Gain
Resolution
binary of R 2h

OHM INSTITUTE, Hyderabad

 R 2R ladder DAC Inverting

f DN ladder un
Rf
3b g
R
R R
mm mm mm

2R 2R 2R Vo
ar
d 1
Kbo Kbl bz
LSB d t MSB

tr
un
R
nm M
Rf
R
Vth t to
I
1

HI
m

f II
ro bi
En
a Csiiosisi
fair

OHM INSTITUTE, Hyderabad

 Grounded R 2 R ladder

Grounded MSB Node

3bit ladder I 18 R I ly R 42 I
µ ZR m Vr
f 4
2k 2R 212 H 2K

3 z z 3
IRm R

Reference voltage is connected

to MSB Node
I
Current pumped into
the network MSB Node

Current will spht equally every

mode

OHM INSTITUTE, Hyderabad

 A R 2 R ladder DAC
Sb't CCurrentModel
MS B
R R TVr Node D

are iI tf
far
an
VI 12
y bo b
t Rf
b
y
en V I Rf

I
fu a

t Vo
g
3

I bo bi
I
if F t
E BYE
I bot 2 bit 4
Ig by
V I Rf bot 2 bit 4bz
If f Rf
Vo bo 12 bit 4b

g
K f Rf
DAC

try
n
E Cair
v Eisibi they
9 T
n

Dec eq
Resolution
of binary
gain

OHM INSTITUTE, Hyderabad

MSD
ti

9
LSB

OHM INSTITUTE, Hyderabad

Resolution X loot

µ J
I 00

255

0.39

OHM INSTITUTE, Hyderabad

R Xiao't
Jn

100
1oz g

O 097

OHM INSTITUTE, Hyderabad

n bits

2h too

OHM INSTITUTE, Hyderabad

2
128643216 89 2 I
bzbbbsbybzbs.br bo

16 1
p
LSB H Ho

ff
v
f
2

to Ivo Voz
t
f
IK 16 1
R
R 8 Kr
16
R 0.5km

OHM INSTITUTE, Hyderabad

 0001 0.0625

O 0625 l x D

D O 0625 V

111172
Va 15 0.0625

0.9375 V

OHM INSTITUTE, Hyderabad

 1
LSB Resistance MS B Res

Max R 28 1 0.5k

255 o 5k n

127 5 kn

OHM INSTITUTE, Hyderabad

 Va Decimal eq of Binary x Resoution

D Vr

16 ne
kn D
Tfa
13A 1 10 3 16 t 1 162
µ

lot 48 t 256

314

Va 314 lo 3 069 V
1023

OHM INSTITUTE, Hyderabad

 ni
E r
j MSB 1010 z
R
mm

F
to 114
f
n
un
7km
inirm
L
R
mm
t l
Vo
Ev
Ei
Vo
f HF fool
to 5V

al

OHM INSTITUTE, Hyderabad

 Ideal
09 t.lk to C XD 5 15 5
sis
1.812 1ft 4 tf f
5.5 5 1 05 0.25 0.125
3612 Vo
5.5 Vos 9 375W
7 ZR

5.5

with Tolerance Vomax

roma
siftotat
t

12.64V

be 9.37 s v
ma
10K Vomex 12.64

1 Tolerance 12.64 9.375 X 100

9 375

34.491
F 35

OHM INSTITUTE, Hyderabad

 3500mV
E 14mV
2 I
14mV 3500mV
2h I 2 7251

2h I 250 n 8

2h 251

OHM INSTITUTE, Hyderabad

 I

o
4 Vth

Sz S So
I 1 I 0

Vtr 6
Sj
31
8

D VI 5
2h 8

OHM INSTITUTE, Hyderabad

 or 1
no 1 16 Grounded R 2 R
Y s g g f Ladder
LSB
I t
Iq EV I IV IMA
R LI 10km
i I 1000nA
lb 16
62 5mA

It
It 16
r
Vo I R
10K
E
lm
E 10K

51 V
16
3 125 V

OHM INSTITUTE, Hyderabad

 I 8
10K
O 8mA
R R f
r
ZR 2R
v v
v

7 out I
Ig Ig Iq 4Itg2I
II
8
0mA
7g O
O 7mA

OHM INSTITUTE, Hyderabad

Counter DAC Cascade

2 bit 2 bit
Upcounter
DAC
4
Staircase
Waveform
DAC o
Ip
0 Bs
00
0 I D 2b
s
to 20
O
il 30
00 7 O
i
i

OHM INSTITUTE, Hyderabad

 iii i i
i

OHM INSTITUTE, Hyderabad

 7 G 5 y 3 z l O

L L
L
L
L
L
Hur p a p
Do Dz Di Dd
929,90Dz Dl
l l l l l
1111
I
I I I 0
I O l I 0 I
0 O l O o
0010
I
I I D l I
O l O o I 0 O l O
0 o l O I Too
o o co o 0 Too

OHM INSTITUTE, Hyderabad

 I

o o o I

000 SO
I 00 y
l lo 6

111 7
011 3
001 I
000

OHM INSTITUTE, Hyderabad

Aaaaa

111
QA9139CQD D Dz D Do

i 2
OO l O
O
OOO I

OHM INSTITUTE, Hyderabad

 I
12

s v
2N I
V
9N
2N 1 412

OHM INSTITUTE, Hyderabad

 lo V E 5mV
2N I
10000mV I 2N I
5mV

2000 I 2N I
2N 22001
N 211

OHM INSTITUTE, Hyderabad

 a
1500
r r a
r r
7 8125
78125
t 7 8125
7.8125 mV s
15.625mV D

1500 7 8125 1500 7 8125

D
95.5
15.625

196 16 0
96 9,6
1
signb't 60 4

y d
196 0110 0000 z

96
10100000 z

AO y

OHM INSTITUTE, Hyderabad

 I
I DAC
I
I
I
II
2

1
Va
ADC 1
Vr 1275 bin i
i
D 1275 5mV I
255
I 2.5mV
If

OHM INSTITUTE, Hyderabad

 A DC

1 Counter ADC
type
2 SA R ADC
type
31 Dual Slope Integrating ADc

14 Flash ADC

OHM INSTITUTE, Hyderabad

 Counter ADC
a 2 type
U 01 I I
3 10 00
O O
Va Up
counter
4T clock oooo
O 7
0001 Binary equivalent

2
1 8
0010
00 11
01 00
y of Analoginput
DAC
D IV
counter counts as as it gets clock ifp
long
Counter gets the clock input as
long as

is 1
comparator ofp
is 1 as Va of
Comparator op as
long
counter counts as
long as Va Vf

When Va Vt counter stops counting

then the output of the counter will be
of
the digital or
binary equivalent
the analog input
3 01 00 Va 72 I ooo
W
as

e
I
I 0001 I
2 O o lo 2

3 00 I I 3
4 10 I 00 4

OHM INSTITUTE, Hyderabad

 3
Y G 4 Ruppe Bould

0100

7 2V 2 8
w A
upper
bound
100072

Binary equivalent
YIELD Lowton
input
Analog
x

Maximum conversion time N

1
Tcu
for n bit counter type
AD C

N bit ADC can count upto 2N 1

garth ADC
fate

sgj crow
sampling
Time Ts 2 Conversion
time Ma

OHM INSTITUTE, Hyderabad

 Ts 2 2N 1 Tak

t LN
YS 1 Tak

increases the
Disadvantage As the analoginput
in Anc
courier
conversion time a
type
increases
Ucp
Va 3.4V s 0100

PM Va 7 2V tooo
xp PT

SAR Successive Approximate

ADC
Register type

conversion time is independent of Analog

input
N bit SAR ADC total conversion
For a

to N Tak
time is
equal
ELK lies
F fuk 1MHz

4 bit SAR Tanu 4 Talk

Gus

9 For analog input of 2V in

an a

SAR ADL conversion time is 5ns

Find conversion time when input

OHM INSTITUTE, Hyderabad

I nd un s 1
is lov
5 us
Ane

OHM INSTITUTE, Hyderabad

 Vf

Va R 2R
t p
Ma iemg.no Resolution of Dac
TI VI

OHM INSTITUTE, Hyderabad

 f O5V
Counter ADC
type

V 110
6S

P
Biffing.co hBfhas

oBfo s

Resolution o 5V

t
Yone 02 bn o2 bn
ab't
VDAC x Resolution
edgecionfalbina

g
bn Resolution
o2

as

2n bn
of Vpac

OHM INSTITUTE, Hyderabad

eg n o

Resolution bae
f o2
b
gale

Resolution 4V

OHM INSTITUTE, Hyderabad

Boi D Es

oof I

l l l0

OHM INSTITUTE, Hyderabad

 Successive Approximate Register SAR ADC
SAR ADC is
Total conversion time in an
type independant
of Analog input
for N bit SAR AD c N Tcu
Tothe conversion time
Soc a
EOC
clock
V u
a
Control Counter
Logic
Vf Binary eq of
n n Analogilp
n n n

DAC

Soc Start of Count Ntc Lk

Eoc End of count
NTLLK
Soc Eoc

to first bit
After SoC Gunter is sort
as

1 and all other bits 0 s

4bit
F Soc 1000

1
5 bit
I 0000

Va Vf Next bit is set to 1

Va Lvf Current bit is reset

and neat bit is set to 1

3 bit SAR
3rd op
3

OHM INSTITUTE, Hyderabad

 3 Cl
3 Tak zudcp Va Vt 111

ptcp watt 11
110
racy
Va
it 7
110 Va Uf lol
Vacuf Of Vacuf
OC 3100 100
Va Uf
011
1
Va Uf 01
VacVf 01 0
Vacuf 010
Va Y Oo
001
Vacuf
Kay 000

Stepsizepac IV Resolution
ey
Va 7 2V
4bit
SAR 3rdCP
Istep zrdcP
4th cp
0100
Soc 21000 30110 20111
In a

l y
4 o g HAV
4 4V Vf 6v

Va 3 N
ptcp MCP
Soc 21000 30100 70010
30011
y t y ya
Vf 8 4 4 Vf 2 4 3

OHM INSTITUTE, Hyderabad

x
X Tanu F 1 ELK
X
Ntl
Toon F 2 Tak
Toon 12 Talk 12ms

12bit ADC Tak lies

Tanu 14 us 14 Talk

OHM INSTITUTE, Hyderabad

 I

OHM INSTITUTE, Hyderabad

 Tammy'eirsion
sampling
time
Ts 75ns
10
15µg 200kHz

Ge
Iz
D Vr
I 212 1112
100 t
Qe I Zayyx
I
Icy
I o 012 l

fs L 200kHz
fs 2fm
Ifm L 200kHz
f m L 100kHz

2 I 3 I 4
5ns 5ns 5
5ms 5ms 5mg
L s
30ms

Sampling 3samples130ns
Rate for CHL
samplesIsec
433am

3 06 samples ka
look Samphs Kee

OHM INSTITUTE, Hyderabad

 look Samphs Kee

NTCLK

OHM INSTITUTE, Hyderabad

OHM INSTITUTE, Hyderabad
8 Tc Lk
8 1us

OHM INSTITUTE, Hyderabad

 Resolution Vr 15 e IV
2h I 15

v v v

zadcp 3Vdcp
fits Istep
Soc 71000 1100 7.1010 7 001 3 000

la y n

Uf 8V 4 12
4 10

OHM INSTITUTE, Hyderabad

 Va 3 5V
Vv 5V
D Ur
ant
5dcp
10110000
Vad's 1stop zadcp y

10000000 7 I 1000000 0100000

it
T2 5 2 51 125
t
VI I 2.51 0.625
3.75 3 125
r
2
I
nbit
10000

E K
H'Kaun
her
1
2

OHM INSTITUTE, Hyderabad

 Dual Slope Integrating ADC
1 Most Accurate A DC

2 Slowest ADC

Va
r
if yuh UK
nm L
Vr
Vi R Gunk'T b't
1
a

I I
g
T Binary eq of
switch Va
toggling
control DAC
logic
Va and Vr are
of opposite polarities
Va Analog input Vr Reference
Voltage

Volt plz JVittldt

Counter counter as as Voltko

long
When VoCt 70 counter stops counting

and output of the counter will be

the binary equivalent for the
analog
input
input of integrator is connected
Initially
to Va and after a fixed duration of

time integrator input toggles to ur

initially vi Va for fixed time duration t

t

OHM INSTITUTE, Hyderabad

 bottle
Leg Vadt
Iat of TET
Rc

Afterti Integrator inputtoggles to Vr

t
bottle C Vrldt
E oc za
o i
It A
bolt RC 6
12

yktf.fm a
Tl Do
i k
i
tCounter
stops
9 Tyr counting
Va Rc
Ec
output of
counter is

RIE
XT
LExtz binary eq of
Analog YP

De
integration
Vax T Vr X T2 time

9
Integration
time 00
01
to

OHM INSTITUTE, Hyderabad

 I I 3rd
A OO ythcp

11 2 TCLK Tz NTCLK
ti T2 1 111after Ncp N
i i
1 Countershops
want l
swing counting
y I t Otp of
all I
La 1
Rc counter is
Rc 9 binary
After2WCP becomes eqof
µ
all 0
again
N
i.BimryegofVa

Vax2NT4LK
VrXNTcLkf.N
Vax 2
Vr

N Va

F Conversion time
L for Dual Slope ADC
Binary eq of Va T t Tz

Maximum conversion
fit 12
ma
time
dntCLK 2N 1 Tuk

OHM INSTITUTE, Hyderabad

 2N Tcl k

ADC has the

Dud slope integrating capacity
to reject power supply noise and also

noise in the analog input

Vin H Vat Un Sin21T ft

1
If sinusoidal Teme
period is
integral multiple of
time this
integrating
o p due to Sinosoidal

noise becomes 0

TI
bolt Tfc bin Hdt
0

T 20ms
looms
f
T
f 50kg
eye f
bin 50mV t 5 Sin100Mt Noise is
rejected
bin 50mV t 55in 50Mt
L
f 25
Hz
d
Noise
f 1000ms
is not 25
rejected 40ms

OHM INSTITUTE, Hyderabad

j

OHM INSTITUTE, Hyderabad

I t 2 28 us
tuk
f
26ns
64US O 064ms

OHM INSTITUTE, Hyderabad

OHM INSTITUTE, Hyderabad
 A

OHM INSTITUTE, Hyderabad

 8 CP
2N11 29 512CP
Icp

OHM INSTITUTE, Hyderabad

Vax Iit time Vr De Int

tax 300ms 00mV 37oz

Va 370.2mV I 23.4mV
3

OHM INSTITUTE, Hyderabad

OHM INSTITUTE, Hyderabad
 2NT CLK
0

2 1 8

OHM INSTITUTE, Hyderabad

 Tak lies
Max conversion
sampling
time lime

Ts 7 2N Tak
Ts 2 Ius

Ts 7 2000 us

Bc I
2000M
fs L 106
2 103

fs L 500
Hg
Tm
ts 2fm Fm

OHM INSTITUTE, Hyderabad

 Va X T Vr X Tz
420mV 50ms Coomu T2

Tz 60ms

OHM INSTITUTE, Hyderabad

 FLASH ADC
1 FASTEST ADC
2 N bit Flash ADC consists of
N l 3 2N Resistors
comparators
VR Va
2b't t un WI
flash R t
I
o n
312 B
4 R SE
ya urn Digital
Circuit
VIZ M
Bo
R vatkly
Xo
1
VI
r

Resolution for
orbit Flesh VI
ADC 2h
InputRange X X X Bi Bo

3IRLVALVR I 1 I I V
ELL Val o 1 I 0

YR VaLURK O o I 0 I
O Cvn LVRly O O O O o

9
D VR Bi X2 Xi Xo Iz X Xo

4 B Xi Xo

Bo Xz Xi Xo t Iz XT Xo
Bo Xo Xz 0 x

OHM INSTITUTE, Hyderabad

 I

OHM INSTITUTE, Hyderabad

 XL Xl Xo B Bo
2 Va I l l l l
1.5L VALZ 0 l I i 0

0524415 O O l o 1
LV 0C VALO'S 0 O O 00

I5V
Bo X2XiXotXzXT Xo
o5V 100 3 Xo X
Xz
600

OHM INSTITUTE, Hyderabad

 Xy Xz X Y Yo

2.524 3 I l l l l
1.524cL 5 o y l o

25V O 5C Vall 5 O 0
O
I I
OL Va co 5 O O o O O
f5V

0.58 41 113 2 1 115 2 1

Yi Xz.X

OHM INSTITUTE, Hyderabad

OHM INSTITUTE, Hyderabad
OHM INSTITUTE, Hyderabad
OHM INSTITUTE, Hyderabad
OHM INSTITUTE, Hyderabad
OHM INSTITUTE, Hyderabad
 8pF

8PF

or 75N

8pF

75N
em
Vin
Vin's Ves LSB

via 255 8PF

Vine Ves VEI
510
z
509425
510
one LSB Vr Vr
2h I 255

LSB VI
510 510

B Tammi

KCH Vinci e

Eff
l e
they

OHM INSTITUTE, Hyderabad

 The I
e t
510

h
than sto

Tamu th
fo
Tamu
5 255 top h Sto

7
9.54 X lo Sec
Ts 2 Tamu

I z L
Tamu Ts

fs E L
Taonu

f E l o 4 106samplesIsa

OHM INSTITUTE, Hyderabad