DSDV Lab Manual Ay 2024-25

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
Accredited by NBA, New Delhi
DIGITAL SYSTEM DESIGN USING VERILOG

BEC302
III SEMESTER
PRACTICAL COMPONENT
MANUAL - OBSERVATION
Prepared by,
Mrs. MEGHANA M N
Assistant Professor
Dept. of ECE
MIT Thandavapura
STUDENT NAME :
USN :
ACADEMIC YEAR : 2024-25
A Unit of Maharaja Education Trust®
MAHARAJA INSTITUTE OF TECHNOLOGY

THANDAVAPURA
NH 766, Nanjangud Taluk, Mysuru- 571 302

Affiliated to VTU, Belagavi and approved by AICTE, New Delhi
BEC302 DSDV practical component of IPCC Academic Year 2024-25
VISION OF THE INSTITUTE
“To be recognized as a premier institute in creating competent graduates driven towards socio-technical
needs”
MISSION OF THE INSTITUTE
1. To exhibit quality in the processes of teaching and learning evolved through continual feedback.
2. To create an ecosystem of greater learning through research and innovation.
3. To engage in self-learning through interaction with industry and alumni.
4. To maintain professional and ethical approach in dealing with stakeholders.
VISION OF ECE DEPARTMENT
“To be at the forefront in producing envisioning minds and build competencies in the field of electronics
and communication engineering to deliver quality solutions to societal problems”
MISSION OF ECE DEPARTMENT
1. To impart quality education in an ecosystem of self-learning and thought-provoking engagements that

propels creativity.
2. To adapt newer teaching methods drawn from research and innovation to accelerate problem-solving
skills.
3. To deploy strategic opportunity that potentiates leadership qualities aided with ethical and competitive
attitude.
PROGRAM EDUCATIONAL OBJECTIVES (PEOs) OF THE

DEPARTMENT
Within few years of graduation, the Electronics and Communication Engineering program will enable its
graduates to:
1. Exhibit competencies relevant for industry and reason the findings towards better performance of self
and the system.
2. Explore technological developments through inquisition of greater knowledge and their applicability.
3. Develop solutions to solve societal problems in a team or as an individual.
Department of ECE, MIT Thandavapura Page i

PROGRAM OUTCOMES (POs)
PO 1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
PO 2: Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
PO 3: Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
PO 4: Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.
PO 5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
PO 6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to the professional engineering practice.
PO 7: Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
PO 8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO 9: Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
PO 10: Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
PO 11: Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
PO 12: Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Department of ECE, MIT Thandavapura Page ii

LAB INSTRUCTIONS
General instructions
1. Uniform and ID card is must.
2. Students must bring laboratory manual - observationand recordalong with pen, pencil, calculator etc.
no borrowing from others.
3. Maintain silence in the lab. Keep laboratory clean.
4. Keep your belongings in the appropriate place provided to you.
5. Do not come late to the laboratory.
6. Work only on the computers allotted to you.
7. Computers and peripherals are not to be moved or reconfigured without approval of Lab instructor
or In-charge faculty.
8. Students may not install software on lab computers.
9. Playing of games on computer in the lab is strictly prohibited.
10. Before leaving the lab, student must close all programs positively and shutdown the computers.
Record
1. Draw truth tables and other necessary block diagrams neatly and label correctly.
2. Enter readings in the tabulation.
3. Units are to be written for various quantities.
4. Complete the record before you come to next lab session.
5. Bring the record for submission during next lab session.
Attendance
1. You have to give your attendance, submitting records, and show the updated results in laboratory
manual - observation and get it signed.
2. You have to occupy the respective computer systems which is assigned by signing in the log book.
Department of ECE, MIT Thandavapura Page iii

Digital System Design using Verilog Semester 3
Course Code BEC302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory/Practical
Course objectives:
This course will enable students to:
 To impart the concepts of simplifying Boolean expression using K-map techniques and Quine-
McCluskey minimization techniques.
 To impart the concepts of designing and analyzing combinational logic circuits.
 To impart design methods and analysis of sequential logic circuits.
 To impart the concepts of Verilog HDL-data flow and behavioural models for the design of digital
systems.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
 Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Show Video/animation films to explain the different concepts of Linear Algebra & Signal
Processing.
 Encourage collaborative (Group) Learning in the class.
 Ask at least three HOTS (Higher order Thinking)questions in the class, which promotes
critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
 Discuss how every concept can be applied to the real world-and when that's possible, it
helps improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and
have discussions on the topic in the succeeding classes.
 Give Programming Assignments.
MODULE-1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,
Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine-
McCluskey Minimization
Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1).
MODULE-2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)
(Section5.1to5.7 ofText2)
MODULE-3
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Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flip-
flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous
Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using
clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2)
MODULE-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description.(Section2.1to2.2(only Verilog) of Text3)
MODULE-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (onlyVerilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)
PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)
Sl.N Experiments
1 To simplify the given Boolean expressions and realize using Verilog program
2 To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder
6 To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator
7 To realize using Verilog Behavioral description:
Flip-flops: a)JK type b)SR type c)T type and d)D type
8 To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.
Demonstration Experiments (For CIE only–not to be included for SEE)
Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing
experiments.
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor
in the specified direction (by N steps).
10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
its working.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.
2. Analyze and design for combinational logic circuits.
3. Analyze the concepts of Flip Flops(SR, D,T and JK) and to design the synchronous sequential
circuits using Flip Flops.
4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using
Verilog descriptions.
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Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination)
taken together.
The IPCC means the practical portion integrated with the theory of the course. CIE marks for the
theory component are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for
the theory component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of
IPCC.
CIE for the practical component of the IPCC
 15 marks for the conduction of the experiment and preparation of laboratory record, and 10
marks for the test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks
of all experiments’ write-ups are added and scaled down to 15 marks.
 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.
SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion
will have a CIE component only. Questions mentioned in the SEE paper may include questions
from the practical component.
 The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum
marks-25) in the theory component and 10 (40% of maximum marks -25) in the practical
component. The laboratory component of the IPCC shall be for CIE only. However, in SEE,
the questions from the laboratory component shall be included. The maximum of 04/05 sub-
questions are to be set from the practical component of IPCC, the total marks of all questions
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should not be more than 20 marks.
 SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to
qualify for the SEE. Marks secured will be scaled down to 50.
 The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks
out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester
End Examination) taken together.
Suggested Learning Resources:
Books
1. Digital Logic Applications and Design by John MYarbrough,Thomson Learning,2001.
2. Digital Principles and Design by Donald DGivone,McGrawHill, 2002.
3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream techpress.
ReferenceBooks:
1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Logic Design, by Sudhakar Samuel, Pearson/Sanguine, 2007
3. Fundamentals of HDL,by Cyril PR, Pearson/Sanguine2010
Web links and Video Lectures (e-Resources):
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Programming Assignments/Mini Projects can be given to improve programming skills.
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CONTENTS
Contents Page No.
i Vision, mission and PEOs i

ii Program Outcomes (POs) ii
iii Lab instructions iii
iv Syllabus iv – vii
v Contents viii
vii Introduction 1-9
Marks
Sl. Conduction Faculty
Experiment Name Page No. Obtained
No. Date Signature
(5M)
1. Boolean expression 10 - 13
2. Adder / Subtractor (Half / Full) 14 - 22
3. 4-bit ALU 23 - 25
4. Code converters 26 - 35
5. 8:1mux, 8:3encoder, Priority encoder 36 - 41
1:8Demux, 3:8 decoder,2 –bit

6. 42 - 48
Comparator
7. Flip-flops 49 - 56
8. Counters-up/down (BCD and binary) 57 - 63
DEMOSTRATION EXPIREMENTS
9. Stepper motor
10. Switches and LEDs
total marks obtained
Department of ECE, MIT Thandavapura Page viii

INTRODUCTION
INTRODUCTION TO HDL
In computer engineering, a Hardware Description Language (HDL) is a

specialized computer language used to describe the structure and behavior of electronic circuits,
and most commonly, digital logic circuits.
Due to the exploding complexity of digital electronic circuits since the 1970s (see Moore's
law), circuit designers needed digital logic descriptions to be performed at a high level without
being tied to a specific electronic technology, such as CMOS or BJT. HDLs were created to
implement register-transfer level abstraction, a model of the data flow and timing of a circuit.
 There are two major hardware description languages:

1. VHDL - Very High Speed Integrated Circuits Hardware Description Language
2. Verilog – Verification Logic
 There are different types of description/modeling in them:
1. Dataflow modeling
2. Behavioral modeling
3. Structural / Gate level modeling
DIFFERENCE BETWEEN VHDL & VERILOG
DESCRIPTION VERILOG VHDL
Program structure Defined by “module” Defined by “entity”

Pascal & Ada programming
Root Language C programming language
language
Sensitivity Case sensitive Case insensitive
Complexity Less complex More complex
Built Loosely typed language Strongly typed language
Usage Used to model electronic system Used in chip designing
Dept. of ECE, MIT Thandavapura page 1

INTRODUCTION TO XILINX
ISE Xilinx (Integrated Software Environment (ISE)), i.e. programmable logic design tool in
electronics industry. This Xilinx design software suite allows taking design from design entry
through Xilinx device programming. The ISE Project Navigator manages and processes design
through several steps in the ISE design flow. These steps are Design Entry, Synthesis,
Implementation, Simulation/Verification, and Device Configuration. Xilinx is one of most popular
software tool used to synthesize VHDL code.
Release version : 14.7

XILINX TOOL PROCEDURE
PROCEDURE FOR SOFTWARE EXECUTION

STEP 1:
1. Double click on the ISE Design Suite 14.7 icon.

2. Go to file in file menu bar and select the option close project to close the old projects.
3. Go to file in file menu bar and select the new project.
4. Give the project name, location (Mandatory D Drive) and click on next.

STEP 2:
5. In Step 2 make necessary changes:

Family : Spartan 6
Device : XC6SLX4
Package : TQG144
Speed : -3
Simulator : ISim (VHDL/Verilog)
Preferred language : Verilog
Then click on next and finish.

STEP 3:
6. In the Design window (Left most top corner) Select available device (Ex. Xc6slx4-
3csg225), right click on it. Select the new source, select Verilog module, give file name,
enable the Add Project and click on next.

7. Specify the ports (Input, Output and Inout). Then click on Next and Finish.

STEP 4:
8. Write the verilog program and save it.
9. In the process window (Left most bottom corner), expand synthesize XST and double click
on check syntax.
10. If no errors found then proceed to step 5.

STEP 5:
11. In the Design window (Left most top corner), select .v file, click on new source.
12. In new source window select Verilog Test Fixture and give file name and enable the option
Add to Project, click on next, next and finish.

STEP 6:
13. Give the inputs (between initial begin and end) in the Test bench (TB) file and click on
save.
14. In the Design window (Left most top corner), Change the view to Simulation, select the test
bench (TB) file.
15. In the Process window (Left most bottom corner), elaborate ISim Simulator. Double click
on Behavioral Check Syntax to check for errors and double click on Simulate Behavioral
Model to observe the output waveform.
16. Select the measure marker option in the Toolbar to verify the simulation output.
PROGRAM 1
REALIZATION OF BOOLEAN EXPRESSIONS
AIM: To simplify the given Boolean expressions and realize using Verilog program using
dataflow and structural module.
THEORY: Boolean expression is an expression used in programming languages that produces a

Boolean value when evaluated. A logical statement that results in a Boolean value, either be True or
False, is a Boolean expression. Sometimes, synonyms are used to express the statement such as
'Yes' for 'True' and 'No' for 'False'. Also, 1 and 0 are used for digital circuits for True and False,
respectively.
BOOLEAN EXPRESSION: 𝒀 = 𝑨𝑩 + 𝑩𝑪 + 𝑨𝑪
TRUTH TABLE:
INPUTS OUTPUT
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
VERILOG CODE:
DESIGN BLOCK [DATAFLOW DESCRIPTION]
module boolean (A, B, C, Y);
input A, B, C;
output Y;
assign Y = (A&(~B)) | ((~B)&C) | ((~A)&C);
endmodule

DESIGN BLOCK [STRUCTURAL DESCRIPTION]

input A, B, C;
output Y;
wire S1, S2, S3, S4, S5;
not a1 (S1,A);
not a2 (S2, B);
and a3 (S3, A, S2);
and a4 (S4, S2, C);
and a5 (S5, S1, C);
or a6 (Y, S3, S4, S5);
endmodule
DESIGN BLOCK [BEHAVIORAL DESCRIPTION]

input A, B, C;
output Y;
always @ (A,B,C)
begin
case ({A,B,C)}
3’b000: Y=0;
3’b000: Y=1;
3’b000: Y=0;
3’b000: Y=1;
3’b000: Y=1;
3’b000: Y=1;
3’b000: Y=0;
3’b000: Y=0;
endcase
end
endmodule

WAVEFORM:
RESULT: The given Boolean expression is simplified and realized using Verilog description.

VIVA QUESTIONS – BOOLEAN EXPRESSION
1. What is Boolean Algebra?

2. What are the basic operations in Boolean algebra?
3. What is a Karnaugh Map (K-map)?
4. What is the 2 simplification technique in Boolean expression?
5. What is a Truth Table?

PROGRAM 2
HALF/FULL ADDER/SUBTRACTOR
AIM: To realize Adder/Subtractor (Full/half) circuits using Verilog dataflow and structural
description.
THEORY:
1. Half Adder: A half adder is a combinational logic circuit that performs binary addition of two
single-bit binary numbers. It has two inputs, A and B, and two outputs, SUM (S) and CARRY
OUT (Cout). The S output is the least significant bit (LSB) of the result, while the Cout output
is the most significant bit (MSB) of the result, indicating whether there was a carry-over from
the addition of the two inputs.
LOGIC SYMBOL:
LOGIC DIAGRAM:
TRUTH TABLE:
INPUTS CARRY
A B S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
LOGIC EXPRESSION:
𝑺𝑼𝑴 ∶ 𝑺 = 𝑨 ⊕ 𝑩; 𝑪𝑨𝑹𝑹𝒀 ∶ 𝑪𝒐𝒖𝒕 = 𝑨. 𝑩
VERILOG CODE:
module HalfAdder (A,B,S,Cout);
input A,B;
output S,Cout;
assign S=A^B;
assign Cout=A&B;
endmodule

module HalfAdder (A,B,S,Cout);
input A,B;
output S,Cout;
xor a1(S,A,B);
and a2(Cout,A,B);
endmodule
THEORY:
2. FULL Adder: A full adder is a combinational logic circuit that performs binary addition of
three single-bit binary numbers. It has three inputs, A,B and Cin and two outputs, SUM (S) and
CARRY OUT (Cout). The S output is the least significant bit (LSB) of the result, while the
Cout output is the most significant bit (MSB) of the result, indicating whether there was a carry-
over from the addition of the two inputs.
LOGIC SYMBOL:

LOGIC DIAGRAM:
TRUTH TABLE:
INPUTS CARRY
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LOGIC EXPRESSION:
𝑺𝑼𝑴 ∶ 𝑺 = 𝑨 ⊕ 𝑩⨁𝑪𝒊𝒏; 𝑪𝑨𝑹𝑹𝒀 𝑶𝑼𝑻 ∶ 𝑪𝒐𝒖𝒕 = 𝑨. 𝑩 + 𝑩. 𝑪𝒊𝒏 + 𝑨. 𝑪𝒊𝒏
VERILOG CODE:
module FullAdder (A,B,Cin,S,Cout);
input A, B, Cin;
output S, Cout;
assign S = A^B^Cin;
assign Cout = (A&B)|(B&Cin)|(A&Cin);
endmodule

module FullAdder (A,B,Cin,S,Cout);
input A, B, Cin;
output S, Cout;
wire S1, S2, S3, S4;
xor a1 (S1, A, B);
xor a2 (S, S1, Cin);
and a3 (S2, A, B);
and a4 (S3, B, Cin);
and a5 (S4, A, Cin);
or a6 (Cout, S2, S3, S4);
endmodule
3. Half Subtractor: A half subtractor is a combinational logic circuit that performs binary
difference of two single-bit binary numbers. It has two inputs, A and B, and two outputs,
DIFFERENCE (D) and BORROW OUT (Bout). The D output is the least significant bit (LSB)
of the result, while the Bout output is the most significant bit (MSB) of the result, indicating
whether there was a borrow-over from the subtractor of the two inputs.
LOGIC SYMBOL:

LOGIC DIAGRAM:
TRUTH TABLE:
INPUTS CARRY
A B D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
LOGIC EXPRESSION:
𝑫𝑰𝑭𝑭𝑬𝑹𝑬𝑵𝑪𝑬 ∶ 𝑫 = 𝑨 ⊕ 𝑩; 𝑩𝑶𝑹𝑹𝑶𝑾 𝑶𝑼𝑻 ∶ 𝑩𝒐𝒖𝒕 = 𝑨. 𝑩
VERILOG CODE
DESIGN BLOCK [DATAFLOW MODELLING]

module HalfSubtractor (A, B, D, Bout);
input A, B;
output D, Bout;
assign D=A^B;
Bout= (~A)&B;
endmodule
DESIGN BLOCK [STRUCTURAL MODELLING]
module HalfSubtractor (A, B, D, Bout);
input A, B;
output D, Bout;

wire S1;
xor a1 (D, A, B);
not a2 (S1, A);
and a3 (Bout, S1, B);
endmodule
4. FULL SUBTRACTOR: A full subtractor is a combinational logic circuit that performs binary
difference of three single-bit binary numbers. It has three inputs, A,B and Bin and two outputs,
DIFFERENCE (D) and BORROW OUT (Bout). The D output is the least significant bit (LSB)
of the result, while the Bout output is the most significant bit (MSB) of the result, indicating
whether there was a borrow-over from the subtractor of the two inputs.
LOGIC SYMBOL:
LOGIC DIAGRAM:

TRUTH TABLE:
INPUTS CARRY
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
LOGIC EXPRESSION:
𝑫𝑰𝑭𝑭𝑬𝑹𝑬𝑵𝑪𝑬 ∶ 𝑫 = 𝑨 ⊕ 𝑩 ⨁𝑩𝒊𝒏; 𝑩𝑶𝑹𝑹𝑶𝑾 𝑶𝑼𝑻 ∶ 𝑩𝒐𝒖𝒕 = 𝑨. 𝑩 + 𝑩. 𝑩𝒊𝒏 + 𝑨. 𝑩𝒊𝒏
VERILOG CODE:
module FullSubtractor (A, B, Bin, D, Bout);
input A, B, Bin;
output D, Bout;
assign D = A^B^Bin;
assign Bout = ((~A)&B)|(B&Bin)|((~A)&Bin);
endmodule
DESIGN BLOCK [STRUCTURAL MODELLING]

module FullSubtractor (A, B, Bin, D, Bout);
input A, B, Bin;
output D, Bout;
not a1 (S1, A);
xor a2 (S2, A, B);
xor a3 (D, S2, Bin);
and a4 (S3, S1, B);
and a5 (S4, B, Bin);

and a6 (S5, S1, Bin);

or a7 (Bout, S3, S4, S5);
endmodule
WAVEFORM :
HALF ADDER:
FULL ADDER:
HALF SUBTRACTOR:
FULL SUBTRACTOR:
RESULT: The given adder/subtractor half/fullare realized using Verilog description.

VIVA QUESTIONS – FULL ADDER
1. Define adders and subtractor.

2. What are the types of adder?
3. Explain half adder and full adder.
4. Explain half subtractor and full subtractor.
5. What is the difference between half adder and a full adder circuit?
6. What is the simplified equation of half adder and full adder?
7. What is the simplified equation of half subtractor and full subtractor?

PROGRAM 3
4 BIT ALU
AIM: To realize 4 bit ALU using Verilog program.
THOERY: ALU is a combinational logic circuit that performs arithmetic and logical operations
on integer binary numbers. It's a key component of a computer's central processing unit
(CPU). ALUs perform tasks like addition, subtraction, bitwise operations, and comparisons. The
inputs to an ALU called operands, and a operation indicating the operation to be performed;
Opcode determines the desired arithmetic or logic operation to be performed by the ALU.
LOGIC SYMBOL:
TRUTH TABLE:
Inputs Output
E opcode operation
A B Y
1 000 Addition 0100 0010 0110
1 001 Subtraction 0100 0010 0010
1 010 Multiplication 0100 0010 1000
1 011 Division 0100 0010 0010
1 100 AND gate 0100 0010 0000
1 101 OR gate 0100 0010 0110
1 110 EX-OR gate 0100 0010 0110
1 111 NOT gate 0100 0010 1011
0 - - - - ZZZZ
VERILOG CODE:
DESIGN BLOCK [BEHAVIORAL MODELLING]
module alu (A, B, E, opcode, Y);
input [3:0] A, B;
input E;
input [2:0] opcode;
output [3:0] Y;
reg [3:0] Y;
always @ (A, B, E, opcode)
begin
if (E = = 0)
y = 4’bZ;
else
case(opcode)
3'b000 : Y = A + B;
3'b001 : Y = A - B;
3'b010 : Y = A * B ;
3'b011 : Y = A / B;
3'b100 : Y = A & B;
3'b101 : Y = A | B;
3'b110 : Y = A ^ B;
3'b111 : Y = ~A;
endcase
end
endmodule
WAVEFORM:
RESULT: 4 bit ALU is realized using Verilog description.

VIVA QUESTIONS – ALU

1. Expand ALU.
2. Explain the functioning of ALU.
3. Define opcode.
4. Define operand.
5. Explain the types of logical operators in digital system.
6. Explain the types of arithmetic operators in digital system.

PROGRAM 4
CODE CONVERTERS
AIM: To realize the code converters using Verilog dataflow and behavioral description.
1. BINARY TO GRAY CODE CONVERTER
THEORY: The logical circuit which converts binary code to equivalent gray code is known as
binary to gray code converter. The gray code is a non-weighted code. The successive gray code
differs in one bit position only that means it is a unit distance code. It is also referred as cyclic code.
It is not suitable for arithmetic operations. An n-bit Gray code can be obtained by reflecting an n-1
bit code about an axis after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1
below the axis.
LOGIC SYMBOL:
LOGIC DIAGRAM:

TRUTH TABLE:
VERILOG CODE:

module bingray (b ,g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2] = b[2] ^ b[3];
assign g[1] = b[2] ^ b[1];
assign g[0] = b[1] ^ b[0];
endmodule


module bingray (b ,g);
input [3:0] b;
output [3:0] g;
reg [3:0] g;
always @ (b)
begin
g[3]=b[3];
g[2] = b[2] ^ b[3];
g[1] = b[1] ^ b[2];
g[0] = b[0] ^ b[1];
end
endmodule
2. GRAY TO BINARY CODE CONVERTER
THEORY:
The Binary code consists of two Symbols which are 0 and 1.In binary code each digit is
represented by power of 2. Gray Code system is a binary number system in which every
successive pair of numbers differs by only one bit. Binary Numbers is default way to store
numbers, but in many applications binary numbers are difficult to use and a variation of binary
numbers is needed. Gray code is an ordering of the binary numeral system such that two
successive values differ in only one bit (binary digit). Gray codes are very useful in the normal
sequence of binary numbers generated by the hardware that may cause an error or ambiguity
during the transition from one number to the next. So, the Gray code can eliminate this problem
easily since only one bit changes its value during any transition between two numbers.
LOGIC SYMBOL:

LOGIC DIAGRAM:
TRUTH TABLE:
Decimal Gray code Binary code
number G3G2G1G0 B3B2B1B0
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0111
5 0101 0110
6 0110 0100
7 0111 0101
8 1000 1111
9 1001 1110
10 1010 1100
11 1011 1101
12 1100 1000
13 1101 1001
14 1110 1011
15 1111 1010

VERILOG CODE:

module graybin(g, b);
input[3:0] g;
output [3:0] b;
assign b[3]=g[3];
assign b[2]=g[2] ^b[3];
assign b[1]=g[1]^b[2];
assign b[0]=g[0]^b[1];
endmodule

module graybin(g, b);
input[3:0] g;
output [3:0] b;
reg [3:0] b;
always @ (g)
begin
b[3]=g[3];
b[2]=g[2] ^b[3];
b[1]=g[1]^b[2];
b[0]=g[0]^b[1];
end
endmodule

3. BCD TO EXCESS3 CODE CONVERTER
THEORY: The Excess-3 code can be calculated by adding 3, i.e., 0011 to each four-digit
BCD code. Below is the truth table for the conversion of BCD to Excess-3 code. In the below
table, the variables A, B, C, and D represent the bits of the binary numbers. The variable 'D'
represents the LSB, and the variable 'A' represents the MSB. In the same way, the variables w, x,
y, and z represent the bits of the Excess-3 code.
TRUTH TABLE: K- MAP:

VERILOG CODE:

module bcd_excess3(a,b,c,d,w,x,y,x);
input a,b,c,d;
output w,x,y,z;
assign w = (a | (b & c) | (b & d));
assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d)));
assign y = ((c & d) | ((~c) & (~d)));
assign z = ~d;
endmodule

module bcd_excess3(a,b,c,d,w,x,y,x);
input a,b,c,d;
output w,x,y,z;
reg w,x,y,z;
always @ (a,b,c,d)
begin
w = (a | (b & c) | (b & d));
x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d)));
y = ((c & d) | ((~c) & (~d)));
z = ~d;
end
endmodule

4. EXCESS3 TO BINARY CODE CONVERTER
THEORY: BCD to Excess-3 conversion is just the reverse operation of excess-3 to BCD. The
process BCD to Excess-3 conversion is like subtracting by 3. As 4 bit excess-3 code start from 3
and end at 12 (input 0,1,2,13,14,15 not possible). Now subtract 3 from our excess-3 code. for
impossible inputs of 4 bit Excess-3 code, use output as Don’t care conditions.
TRUTH TABLE: K-MAP:

VERILOG CODE:

module excess3_bcd(a,b,c,d,w,x,y,z);
input w,x,y,z;
output a,b,c,d;
assign a = ((w & x) | (w & y & z));
assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z));
assign c = (((~y) & z) | (y & (~z)));
assign d = ~z;
endmodule

module excess3_bcd(a,b,c,d,w,x,y,z);
input w,x,y,z;
output a,b,c,d;
reg a,b,c,d;
always @ (w,x,y,z)
begin
a = ((w & x) | (w & y & z));
b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z));
c = (((~y) & z) | (y & (~z)));
d = ~z;
end
endmodule

WAVEFORM:
BINARY TO GRAY
GRAY TO BINARY
BINARY TO EXCESS-3
EXCESS-3 TO BINARY
RESULT: Code converters are realized using Verilog description.

PROGRAM 5
8:1 MUX, AND 8:3 ENCODER WITH AND WITHOUT
PRIORITY
AIM: To realize the 8:1 MUX, and 8:3 encoder with and without priority using Verilog
behavioral description.
1. 8:1 MULTIPLEXER
THEORY: An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select
lines S2, S1, S0 and a single output line Y. Depending on the select lines combinations, multiplexer
decodes the inputs. Since the number data bits given to the MUX are eight then 3 bits (23=8) are
needed to select one of the eight data bits.
LOGIC SYMBOL:
TRUTH TABLE:

VERILOG CODE:
module mux8to1 (s, i, y);
input [2:0] s;
input [7:0] i;
output y;
reg y;
always @ (i, s)
begin
case(s)
3'b000: y = i[0];
3'b001: y = i[1];
3'b010: y = i[2];
3'b011: y = i[3];
3'b100: y = i[4];
3'b101: y = i[5];
3'b110: y = i[6];
3'b111: y = i[7];
endcase
end
endmodule
2. 8:3 ENCODER (WITHOUT AND WITH PRIORITY)

THEORY:
ENCODER: It is a combinational logic circuit that converts “2n” binary input lines into “n”
binary output lines. It converts the original information to the coded format. In encoder the output
lines generate the binary code corresponding to input value. An encoder accepts an active level on
one of its inputs, representing digit, such as a decimal or octal digits, and converts it to a coded
output such as BCD or binary. Encoders can also be devised to encode various symbols and
alphabetic characters. The process of converting from familiar symbols or numbers to a coded
format is called encoding.

8:3 ENCODERS: It is a combinational logic circuit that converts 8-bit binary input lines into
3-bit binary output lines. If the priority concept is applied to the encoder, the highest priority input
among the entire input variable will be given the highest priority.
LOGIC SYMBOL:
TRUTH TABLE:
1. 8:3 ENCODER WITHOUT PRIORITY
INPUTS OUTPUTS
en I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0 1
1 0 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 1 0 0 0 0 1 1
1 0 0 0 1 0 0 0 0 1 0 0
1 0 0 1 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 0 1 1 1
0 X X X X X X X X 0 0 0
2. 8:3 ENCODER WITH PRIORITY (Lower indices given the highest priority)
INPUTS OUTPUTS
en I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
1 X X X X X X X 1 0 0 0
1 X X X X X X 1 0 0 0 1
1 X X X X X 1 0 0 0 1 0
1 X X X X 1 0 0 0 0 1 1
1 X X X 1 0 0 0 0 1 0 0
1 X X 1 0 0 0 0 0 1 0 1
1 X 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 0 1 1 1
0 X X X X X X X X 0 0 0

VERILOG CODE:
8:3 ENCODERS WITHOUT PRIORITY

module encoder8to3 (en, i, y);
input en;
input [7:0] i;
output [2:0] y;
reg [2:0] y;
always @ (en, i)
begin
if ( en = =1)
begin
case (i)
8'b00000001 : y = 3'b000;
8'b00000010 : y = 3'b001;
8'b00000100 : y = 3'b010;
8'b00001000 : y = 3'b011;
8'b00010000 : y = 3'b100;
8'b00100000 : y = 3'b101;
8'b01000000 : y = 3'b110;
8'b10000000 : y = 3'b111;
endcase
end
else
y = 3’b000;
end
endmodule
endmodule

8:3 ENCODERS WITH PRIORITY

module encoder8to3 (en, i, y);
input en;
input [7:0] i;
output [2:0] y;
reg [2:0] y;
always @ (en, i)
begin
if ( en = =1)
begin
casex (i)
8'bxxxxxxx1 : y = 3'b000;
8'bxxxxxx10 : y = 3'b001;
8'bxxxxx100 : y = 3'b010;
8'bxxxx1000 : y = 3'b011;
8'bxxx10000 : y = 3'b100;
8'bxx100000 : y = 3'b101;
8'bx1000000 : y = 3'b110;
8'b10000000 : y = 3'b111;
endcase
end
else
y = 3’b000;
end
endmodule

WAVEFORM:
8:1 MUX
8:3 ENCODER WITH AND WITHOUT PRIORITY
RESULT: 8:1 MUX, and 8:3 encoder with and without priority are realized using Verilog
description.

PROGRAM 6
1:8 DEMUX, AND 3:8 DECODER, AND 2 BIT COMPARATOR
AIM: To realize the 1:8DEMUX, and 3:8decoder, and 2 bit comparator using Verilog
behavioral description.
1. 1:8 DEMUX
THEORY: DEMUX or De-Multiplexer is a data distributor combinational circuit. It works in a
reverse way of the Multiplexer. The DEMUX has 1 input port and 2 n output lines. Here n signifies
the selection line for a DEMUX. A 1:8 DEMUX consists of one input line, 8 output lines and 3
select lines. Let the input be D, S0, S1, and S2 are 3 select lines and eight outputs from Y0 to Y7.
LOGIC SYMBOL:
TRUTH TABLE:
INPUTS OUTPUTS
en S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X Z Z Z Z Z Z Z Z
1 0 0 0 0 0 0 0 0 0 0 A
1 0 0 1 0 0 0 0 0 0 A 0
1 0 1 0 0 0 0 0 0 A 0 0
1 0 1 1 0 0 0 0 A 0 0 0
1 1 0 0 0 0 0 A 0 0 0 0
1 1 0 1 0 0 A 0 0 0 0 0
1 1 1 0 0 A 0 0 0 0 0 0
1 1 1 1 A 0 0 0 0 0 0 0

VERILOG CODE:
module demux_1_8(a, en, s, a, y);

input a, en;
input [2:0]s;
output reg [7:0]y;
always @(a, en, s)
begin
if (en = = 0)
y=1’bZ;
else
begin
case(s)
3'b000: y[0]=a;
3'b001: y[1]=a;
3'b010: y[2]=a;
3'b011: y[3]=a;
3'b100: y[4]=a;
3'b101: y[5]=a;
3'b110: y[6]=a;
3'b111: y[7]=a;
endcase
end
end
endmodule
2. 3:8 DECODER
THEORY: Decoder is a combinational logic circuit that converts n input lines to 2n output lines.
It is the reverse process of an encoder. It converts coded signal into original signal. In addition to
input pins, the decoder has a enable pin. 3:8 decoder has 3 input lines and 8 output lines.

LOGIC SYMBOL:
TRUTH TABLE:
INPUTS OUTPUTS
en I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X Z Z Z Z Z Z Z Z
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
VERILOG CODE:
module decoder3_to_8(en, I, y);
input [2:0] I;
input en;
output [7:0] y;
reg [7:0] y;
always @( I, en)
begin
if (en = = 0)
y=8’bz;

else
begin
case (I)
3'b000: y = 8’b00000001;
3'b001: y = 8’b00000010;
3'b010: y = 8’b00000100;
3'b011: y = 8’b00001000;
3'b100: y = 8’b00010000;
3'b101: y = 8’b00100000;
3'b110: y = 8’b01000000;
3'b111: y = 8’b10000000;
endcase
end
end
endmodule
3. 2 BIT MAGNITUDE COMPARATOR

THEORY: 2-bit Comparator is a combinational logic circuit used to compare two binary
numbers consisting of two bits. When two binary numbers A and B are compared the output can be
any of these three cases i.e. A > B, A = B and A < B.
LOGIC SYMBOL:

TRUTH TABLE:
INPUTS OUTPUTS
L=A<B E=A=B G=A>B
A B
Lesser than Equal Greater than
A1 A0 B1 B0 L E G
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0

module Comparator (a,b,l,e,g);
input [1:0] a, b;
output l, e, g;
reg l, e, g;
always @ (a, b)
begin
if (a < b)
begin
l = 1;
e = 0;
g=0;
end

else if (a == b)
begin
l = 0;
e = 1;
g=0;
end
else
begin
l =0;
e = 0;
g=1;
end
end
endmodule
WAVEFORM:
1:8 DEMUX
3:8 DECODER
2 BIT COMPARATOR
RESULT: 1:8 DEMUX, and 3:8 decoder, and 2 bit comparator are realized using Verilog
description.

VIVA QUESTIONS - COMBINATIONAL LOGIC CIRCUITS
1. What are Combinational logic circuits?

2. What is Encoder and Decoder.
3. What is the functioning of priority in Encoder?
4. What is the application of Encoder and Decoder?
5. Explain Multiplexer and Demultiplexer.
6. What is the application of multiplexer and demultiplexer.
7. Mutliplexer and de-multiplexer have how many select lines.
8. What is Magnitude Comparator?
9. What is the application of comparator?
10. What is the need of comparator?
11. What is the difference between analog comparator to digital comparator?
12. In which field comparator plays an important role?
13. What is key difference between sequential and combinational circuits?
14. Define converter.
15. Application of gray to binary and binary to gray conversion.
16. Why we need to convert from Binary to Gray code and vice versa.

PROGRAM 7
FLIP FLOPS
AIM: To realize using Verilog Behavioral description: Flip-flops: a) SR type b) JK type c) T
type and d) D type
1. SR FLIP FLOP
THEORY: SR flip flop is a simple circuit has a set input (S) and a reset input (R) inputs. The set
input causes the output of 0 (top output) and 1 (bottom output). The reset input causes the opposite
to happen (top = 1, bottom =0).
LOGIC SYMBOL:
TRUTH TABLE:
INPUTS OUTPUTS
RESET CLK S R Q Qb CONDITION
1 X X X 0 1 Reset
0 1 0 0 Q Qb No change
0 1 0 1 0 1 Reset
0 1 1 0 1 0 Set
0 1 1 1 X X Invalid

DESIGN BLOCK [BEHAVIOURAL MODELLING]
module sr_ff (SR, reset, clk, Q, Qb);

input [1:0] SR;
input clk, reset;
output Q, Qb;
reg Q,Qb;
always @(posedge clk)
begin
if (reset = = 1)
Q = 0;
else
begin
casex (SR)
2'b00:Q = Q;
2'b01:Q = 0;
2'b10:Q = 1;
2'b11:Q = 1'bX;
endcase
end
Qb = ~Q;
end
endmodule

2. JK FLIP FLOP
THEORY: The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and
R are equal to logic level “1”.
LOGIC SYMBOL:
TRUTH TABLE:
INPUTS OUTPUTS
RESET CLK J K Q Qb CONDITION
1 X X X 0 1 Reset
0 1 0 0 Q Qb No change
0 1 0 1 0 1 Reset
0 1 1 0 1 0 Set
0 1 1 1 X X Invalid

module jk_ff (JK, reset, clk, Q, Qb);
input [1:0] JK;
input clk, reset;
output Q, Qb;
reg Q, Qb;
always @(posedge clk)
begin
if (reset = = 1)
Q = 0;
else
begin
case(JK)
2'b00 : Q = Q;
2'b01 : Q = 0;
2'b10 : Q = 1;
2'b11 : Q = ~Q;
endcase
end
Qb = ~Q;
end
endmodule
3. D FLIP FLOP
THEORY: The D stands for "data", this flip-flop stores the value that is on the data line. It can
be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying
the set to the reset through an inverter.
LOGIC SYMBOL:
TRUTH TABLE:
INPUTS OUTPUTS
RESET CLK D Q Qb ACTION
1 X X 0 1 Reset
0 1 0 0 1 Reset
0 1 1 1 0 Set


module dff (d, clk, reset, Q, Qb);
input d, clk, reset;
output Q, Qb;
reg Q, Qb;
always @ ( posedge clk)
begin
if (reset = = 1)
begin
Q = 0;
Qb = 1;
end
else
begin
Q= d;
Qb = ~Q;
end
end
endmodule
4. T FLIP FLOP
THEORY: The T stands for "toggle", this flip-flop stores the value that is on the data line. It can
be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying
the set to the reset through an inverter.
LOGIC SYMBOL:

TRUTH TABLE:
INPUTS OUTPUTS
RESET CLK T Q Qb ACTION
1 X X 0 1 Reset
0 1 0 Q 𝑄 No change
0 1 1 𝑄 Q Toggle

module t_ff (t, clk, reset, Q, Qb);
input t, clk, reset;
output Q, Qb;
reg Q,Qb;
always @ ( posedge clk)
begin
if (reset = = 1)
Q = 0;
else
begin
if (t = = 0)
Q= Q;
else
Q = ~Q;
end
Qb = Q;
end
endmodule

WAVEFORM:
SR FLIP FLOP
JK FLIP FLOP
D FLIP FLOP
T FLIP FLOP
RESULT: SR, JK, D and T flip flop are realized using Verilog description.
VIVA QUESTIONS – FLIP FLOP

1. Define Flip flop.
2. Define latch.
3. What is the difference between Latch and Flip-flop?
4. What is meant by a bit?
5. What are sequential circuits?
6. Brief out the difference between combinational and sequential circuits.
7. Define SR, JK, D and T flip flop.
8. What is race around condition?
9. How to overcome from the race around condition.

PROGRAM 8
COUNTERS
AIM: To realize Counters - up/down (BCD and binary) using Verilog Behavioral description
THEORY: A binary coded decimal (BCD) is a serial digital counter that counts ten digits and it
resets for every new clock input. As it can go through 10 unique combinations of output, it is also
called as “Decade counter”. A BCD counter can count 0000 to 1001 and so on. The counter which
counts the sequence from 0000 to 1111 is called 4 bit binary counter.
Up counter counts from '0' to the highest number of counts. Down counter counts from the highest
value to the '0' value.
TRUTH TABLE:
1. BCD UP COUNTER
INPUTS OUTPUTS
4 BIT BCD UP COUNTER OUTPUTS DECIMAL
CLK RESET
Q3 Q2 Q1 Q0 EQUIVALENT
1 1 0 0 0 0 0
1 0 0 0 0 1 1
1 0 0 0 1 0 2
1 0 0 0 1 1 3
1 0 0 1 0 0 4
1 0 0 1 0 1 5
1 0 0 1 1 0 6
1 0 0 1 1 1 7
1 0 1 0 0 0 8
1 0 1 0 0 1 9
1 0 0 0 0 0 0

2. BCD DOWN COUNTER

INPUTS OUTPUTS
4 BIT BCD UP COUNTER OUTPUTS DECIMAL
CLK RESET
Q3 Q2 Q1 Q0 EQUIVALENT
1 1 1 0 0 1 9
1 0 1 0 0 0 8
1 0 0 1 1 1 7
1 0 0 1 1 0 6
1 0 0 1 0 1 5
1 0 1 0 0 0 4
1 0 0 0 1 1 3
1 0 0 0 1 0 2
1 0 0 0 0 1 1
1 0 0 0 0 0 0
1 0 1 0 0 1 9
3. BINARY UP COUNTER
4 BIT BINARY UP COUNTER
OUTPUTS DECIMAL
CLK RESET
EQUIVALENT
Q3 Q2 Q1 Q0
1 1 0 0 0 0 0
1 0 0 0 0 1 1
1 0 0 0 1 0 2
1 0 0 0 1 1 3
1 0 0 1 0 0 4
1 0 0 1 0 1 5
1 0 0 1 1 0 6
1 0 0 1 1 1 7
1 0 1 0 0 0 8
1 0 1 0 0 1 9
1 0 1 0 1 0 10
1 0 1 0 1 1 11
1 0 1 1 0 0 12
1 0 1 1 0 1 13
1 0 1 1 1 0 14
1 0 1 1 1 1 15
1 0 0 0 0 0 0

4. BINARY DOWN COUNTER

4 BIT BINARY UP COUNTER
DECIMAL
CLK RESET OUTPUTS
EQUIVALENT
Q3 Q2 Q1 Q0
1 1 1 1 1 1 15
1 0 1 1 1 0 14
1 0 1 1 0 1 13
1 0 1 1 0 0 12
1 0 1 0 1 1 11
1 0 1 0 1 0 10
1 0 1 0 0 1 9
1 0 1 0 0 0 8
1 0 0 1 1 1 7
1 0 0 1 1 0 6
1 0 0 1 0 1 5
1 0 1 0 0 0 4
1 0 0 0 1 1 3
1 0 0 0 1 0 2
1 0 0 0 0 1 1
1 0 0 0 0 0 0
1 0 1 1 1 1 15
VERILOG CODE:
1. BCD UP COUNTER
module bcd_counter (clk, reset, q);
input clk, reset;
output [3:0]q;
reg [3:0]q;
initial q = 4’b0000;
always @ (posedge clk)
begin
if (reset = = 1’b1 | q= = 4’b1001)
q = 4’b0000;
else
q=q+1;
end
endmodule
2. BCD DOWN COUNTER

input clk, reset;
output [3:0]q;
reg [3:0]q;
begin
if (reset = = 1’b1 | q= = 4’b0000)
q = 4’b1001;
else
q=q-1;
end
endmodule
3. BINARY UP COUNTER
input clk, reset;
output [3:0]q;
reg [3:0]q;
begin
if (reset = = 1)
q = 4’b0000;
else
q=q+1;
end
endmodule
4. BINARY DOWN COUNTER

input clk, reset;
output [3:0]q;
reg [3:0]q;
begin
if (reset = = 1)
q = 4’b1111;
else
q=q-1;
end
endmodule
WAVEFORM:
BCD UP COUNTER
BCD DOWN COUNTER

BINARY UP COUNTER
BINARY DOWN COUNTER
RESULT: Binary and BCD up/down counters are realized using Verilog description.

VIVA QUESTIONS - COUNTERS
1. Define counter.
2. Explain the 2 main types of counters.
3. What are the 2 ways of counting sequence in counter.
4. Define synchronous and asynchronous counter.
5. Explain the design of synchronous counter.
6. Give a another name of asynchronous counter.
7. List some of the applications of counter.
8. Counters have how many possible counting sequence.

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DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

Accredited by NBA, New Delhi

DIGITAL SYSTEM DESIGN USING VERILOG

A Unit of Maharaja Education Trust®

MAHARAJA INSTITUTE OF TECHNOLOGY

NH 766, Nanjangud Taluk, Mysuru- 571 302

VISION OF THE INSTITUTE

MISSION OF THE INSTITUTE

VISION OF ECE DEPARTMENT

MISSION OF ECE DEPARTMENT

1. To impart quality education in an ecosystem of self-learning and thought-provoking engagements that

PROGRAM EDUCATIONAL OBJECTIVES (PEOs) OF THE

Department of ECE, MIT Thandavapura Page i

PROGRAM OUTCOMES (POs)

PO 1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

PO 10: Communication: Communicate effectively on complex engineering activities with the

Department of ECE, MIT Thandavapura Page ii

Department of ECE, MIT Thandavapura Page iii

SEE for IPCC

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Contents Page No.

i Vision, mission and PEOs i

2. Adder / Subtractor (Half / Full) 14 - 22

5. 8:1mux, 8:3encoder, Priority encoder 36 - 41

1:8Demux, 3:8 decoder,2 –bit

8. Counters-up/down (BCD and binary) 57 - 63

10. Switches and LEDs

total marks obtained

Department of ECE, MIT Thandavapura Page viii

In computer engineering, a Hardware Description Language (HDL) is a

 There are two major hardware description languages:

DIFFERENCE BETWEEN VHDL & VERILOG

DESCRIPTION VERILOG VHDL

Program structure Defined by “module” Defined by “entity”

Dept. of ECE, MIT Thandavapura page 1

Dept. of ECE, MIT Thandavapura page 2

XILINX TOOL PROCEDURE

PROCEDURE FOR SOFTWARE EXECUTION

1. Double click on the ISE Design Suite 14.7 icon.

Dept. of ECE, MIT Thandavapura page 3

5. In Step 2 make necessary changes:

Dept. of ECE, MIT Thandavapura page 4

Dept. of ECE, MIT Thandavapura page 5

Dept. of ECE, MIT Thandavapura page 6

8. Write the verilog program and save it.

10. If no errors found then proceed to step 5.

Dept. of ECE, MIT Thandavapura page 7

Dept. of ECE, MIT Thandavapura page 8

THEORY: Boolean expression is an expression used in programming languages that produces a

Dept. of ECE, MIT Thandavapura page 10

DESIGN BLOCK [STRUCTURAL DESCRIPTION]

DESIGN BLOCK [BEHAVIORAL DESCRIPTION]

Dept. of ECE, MIT Thandavapura page 11

Dept. of ECE, MIT Thandavapura page 12

VIVA QUESTIONS – BOOLEAN EXPRESSION

1. What is Boolean Algebra?

Dept. of ECE, MIT Thandavapura page 13

DESIGN BLOCK [STRUCTURAL DESCRIPTION]