SOMESH KR MALHOTRA

Assistant Professor,
ECE Department,UIET
 Complementary MOS (CMOS) Inverter uses
▪ pMOS in pull-up network
▪ nMOS in pull-down network
As shown in Figure
 When input is HIGH
▪ pMOS is OFF
▪ nMOS is ON
▪ Therefore the O/P is LOW
 When input low
▪ pMOS is ON
▪ nMOS is OFF
▪ Therefore the O/P is HIGH
 Advantage of CMOS Inverter
▪ Never pMOS and nMOS are ON together due to
which there is no direct path to current take place
between VDD and ground.
▪ Therefore if we neglect leakage current, the static
power dissipation is zero.
▪ Logic swing is between 0 and VDD.
 VTC is shown in fig which is divided into five
regions depending on the operation of nMOS
and pMOS.
 In between pt A and B
▪ nMOS in cutoff region
▪ pMOS in linear region
 In between pt B and C
▪ nMOS in saturation region
▪ pMOS in linear region
 Region above this line ,pMOS operates in linear
region.
 Below this line, pMOS operates in saturation
region with satisfying the condition

 At point C,Slope is -1, this is VIL

 Between D and F,
▪ both the nMOS and pMOS are in saturation region.
 At C,
▪ I/P voltage = O/P voltage
▪ which is also called threshold voltage of the inverter.
 Between F and H,
▪ nMOS in the linear region and
▪ pMOS in the saturation region.
 At pt G,Slope is -1, known as VIH.
 Between H and I,
▪ nMOS is in the linear region and
▪ pMOS in the cutoff region.
 Above this line nMOS in saturation and satisfies the
condition

 Below this line,nMOS works in linear region.

We observe that the VTC curve of a CMOS inverter is very

sharp compared to the resistive load and nMOS load
inverter circuits.
 In between pt B and D
▪ nMOS in saturation region
▪ pMOS in linear region
Therefore we have the following equation
 Differentiating w.r.t. Vin

 At point C, the slope of the curve is -1 and

Vin= VIL. Therefore, we write above Eqn
as follows:
 Between F and H,
▪ nMOS in the linear region and
▪ pMOS in the saturation region
Therefore we have the following equation
 Differentiating w.r.t. Vin,

 At point G, the slope of the curve is -1 and Vin= VIH.

Therefore, we write above Eqn as follows:
 O/P of CMOS Inverter is given by

 I/P= logic ‘1’ (i.e., Vin > VDD + Vtp),

▪ the pMOS transistor is turned OFF, and
▪ the nMOS transistor operates in the linear region.
▪ Since there is no static current in the circuit, there
is no voltage drop across the nMOS transistor.
 Therefore, we have the following expression:

 By solving, we get

 O/P voltage
 I/P=0 (i.e., Vin < Vtn),
▪ the nMOS transistor is turned OFF,and
▪ the pMOS transistor operates in the linear region.
As there is no static current in the circuit, there is
no voltage drop across the pMOS transistor.
Hence, the output voltage is given by the following
equation:
 Threshold voltage when I/P voltage=O/P voltage,
 On VTC,Vth is defined at E, when nMOS and pMOS both
operates in saturation region
 Therefore, we can write following equation
 Positive value is acceptable for Vout
 Hence VIL is calculated
MOS Circuit Design
Er.Somesh Kr. Malhotra
Assistant Professor
ECE Department UIET
 MOS layers

• MOS circuits are formed on four basic layers

• N-diffusion
• P-diffusion
• Polysilicon
• Metal
Which are isolated by thick or thin silicon dioxide insulating layer
• There should be way of capturing the topology and layer information of the actual circuit in
silicon so that we can set out simple diagrms which convey both layer information
topology.
Stick diagram
 Stick diagram

• Stick diagram may be used to convey layer information through the use of
colour codes, for example in case of nMOS design
• Red for polysilicon
• Blue for metal
• Yellow for implant
• Black for contact areas
Stick diagram
Digital CMOS Logic
Design
Somesh Kr Malhotra
Assistant Professor
ECE Department,UIET
 Introduction

• We introduce the digital logic circuit design using CMOS transistors,which are most popular because of
low power dissipation and less area requirement compared to any other logic circuits.
• It is worthwhile mentioning that almost 90% of the total semiconductor devices are fabricated using
silicon CMOS technology.
• CMOS logic is a combination of nMOS and pMOS logic. The nMOS and pMOS transistors are both
functionally and structurally complement to each other.
 Digital Logic Design

• In digital logic design, there are three primary logic operations: (a) NOT, (b) OR,and (c) AND. Using
these three primary logics, any other logic such as NAND,NOR, XOR, or XNOR can be derived.
• In NOT logic, if the input (A) is TRUE, the output (F) is FALSE; and if the input (A) is FALSE, the
output (F) is TRUE. The NOT logic can be realized using a simple circuit as shown in Fig. 1(a). When
the switch S1 is ON, the bulb will not glow. When the switch S1 is OFF, the bulb will glow.
 Digital Logic Design

• In OR logic, if both the inputs are FALSE, the output is FALSE. Otherwise,
the output is TRUE. The OR logic can be realized using two switches S1 and
S2 connected in parallel, as shown in Fig. 1(b).
• When both switches are OFF, the bulb will not glow; otherwise, the bulb will
glow.
 Digital Logic Design

• In AND logic, if both the inputs are TRUE, the output is TRUE. Otherwise,
the output is FALSE. The AND logic can be realized using two switches S1
and S2 connected in series as shown in Fig. 1(c).
 Digital Logic Design

• The mechanical switches shown in Fig.1 can be replaced by MOS transistors as the MOS transistor
behaves as a switch when it is operated between the cut-off and saturation regions.
• As shown in Fig. 2(a), an nMOS transistor can be modelled as a switch connected between the drain
(D) and source (S) and the switch is controlled by gate (G).
• When the gate is logic high (H), the nMOS is ON and the switch is closed, and D is connected to S [see
Fig. 2(b)].
• When the gate is logic low (L), the nMOS is OFF and the switch is open, and D is disconnected from S
[see Fig. 2(c)].
Digital Logic Design
Digital Logic Design
CMOS logic Design

• Any Boolean logic function (F) has possible values: either logic 0 or logic 1.
• For some of the input combinations, F = 1 and for all other input combinations, F =0.
• So in general, any Boolean logic function can be realized using a structure as shown in Fig.
• The switch S1 is closed and the switch S2 is open for input combinations that produce F = 1.
• The switch S1 is open and the switch S2 is closed for other input combinations that produce F = 0.
CMOS logic Design

• As shown in Fig. the output (F) is either connected to VDD or to the ground, where the logic 0 is
represented by the ground and the logic 1 is represented by VDD.
• So the basic requirement of digital logic design is to implement the pull-up switch (S1) and the pull-
down switch (S2).
• As the pMOS transistors can pass logic 1 perfectly, they are used in pull-up switch realization.
• Similarly, as the nMOS transistors can pass logic 0 perfectly, they are used in pull-down switch
realization.
CMOS design methodology

• The basic CMOS design methodology involves three steps:

• Given the Boolean expression, take its complement
• Design PDN by realizing
• AND terms using series-connected nMOSFETs
• OR terms using parallel-connected nMOSFETs
• Design PUN just reverse (or dual) of the PDN
Design of CMOS Inverter (NOT) Gate

• A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS transistor. The nMOS
is used in PDN and the pMOS is used in the PUN, as shown in Figs (a)–(c).
 Design of CMOS Inverter (NOT) Gate

• Operation When input is low, the nMOS is OFF and the pMOS is ON. Hence,the output is connected
to VDD through pMOS.
• When the input is high, the nMOS is ON and the pMOS is OFF. Hence, the output is connected to the
ground through nMOS.
• We can connect a capacitor at the output node as shown in Fig. to represent the load seen by the
inverter. The load capacitor is charged to VDD through pMOS when the input is low and is discharged
to the ground through nMOS when the input is high.
Design of Two-input NAND Gate
Design of Two-input NAND Gate
Design of Two-input NAND Gate
 Design of Two-input NAND Gate

• Operation When A = 0 and B = 0, both the nMOS transistors are OFF and both pMOS transistors are ON.
Hence, the output is connected to VDD and we get logic high at the output.
• When A = 1 and B = 0, the upper nMOS is ON and lower nMOS is OFF. So, output cannot be connected to
the ground. Under this condition, left pMOS is OFF but right pMOS is ON. Hence, the output is connected to
VDD, and we get logic high at the output.
• When A = 0 and B = 1, the upper nMOS is OFF and lower nMOS is ON. So,output cannot be connected to
ground. Under this condition, left pMOS is ON but right pMOS is OFF. Hence, the output is connected to
VDD, and we get logic high at the output.
• When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transistors are OFF. Hence, the output
is connected to the ground, and we get logic low at the output. This is illustrated in Figs 6.11(a) and (c). This
proves by the truth table of NAND gate shown in Fig. 6.11(b).
Design of Two-input NOR Gate
Design of Two-input NOR Gate
Design of Two-input NOR Gate
 Design of Two-input NOR Gate

• Operation When A = 0 and B = 0, both nMOS transistors are OFF and both pMOS transistors are ON.
Hence, the output is connected to VDD and we get logic high at the output.
• When A = 1 and B = 0, the upper pMOS is OFF and lower pMOS is ON. So, output cannot be connected to
the VDD. Under this condition, left nMOS is ON and right nMOS is OFF. Hence, the output is connected to
the ground and we get logic low at the output.
• When A = 0 and B = 1, the upper pMOS is ON and lower pMOS is OFF. So, output cannot be connected to
VDD. Under this condition, left nMOS is OFF and right nMOS is ON. Hence, the output is connected to the
ground and we get logic low at the output.
• When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transistors are OFF. Hence, the output
is connected to VDD and we get logic low at the output. This proves the truth table of NOR gate as shown in
Fig. 6.14(b).
Design the circuit with a suitable stick diagram
Solution
 Solution

B+C

B+C
 Carry
sum