LTC3412A

3A, 4MHz, Monolithic

Synchronous
Step-Down Regulator
FEATURES DESCRIPTION
n High Efficiency: Up to 95% The LTC®3412A is a high efficiency monolithic synchro-
n 3A Output Current nous, step-down DC/DC converter utilizing a constant
n Low Quiescent Current: 64µA frequency, current mode architecture. It operates from
n Low RDS(ON) Internal Switch: 77mΩ an input voltage range of 2.25V to 5.5V and provides a
n 2.25V to 5.5V Input Voltage Range regulated output voltage from 0.8V to 5V while deliver-
n Programmable Frequency: 300kHz to 4MHz ing up to 3A of output current. The internal synchronous
n ±2% Output Voltage Accuracy power switch with 77mΩ on-resistance increases efficiency
n 0.8V Reference Allows Low Output Voltage and eliminates the need for an external Schottky diode.
n Selectable Forced Continuous/Burst Mode® Operation Switching frequency is set by an external resistor or can
with Adjustable Burst Clamp be synchronized to an external clock. 100% duty cycle
n Synchronizable Switching Frequency provides low dropout operation extending battery life in
n Low Dropout Operation: 100% Duty Cycle portable systems. OPTI-LOOP® compensation allows the
n Power Good Output Voltage Monitor transient response to be optimized over a wide range of
n Overtemperature Protected loads and output capacitors.
n Available in 16-Lead Exposed Pad TSSOP and
The LTC3412A can be configured for either Burst Mode
QFN Packages
operation or forced continuous operation. Forced continu-
APPLICATIONS ous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reducing
n Point-of-Load Regulation gate charge losses at light loads. In Burst Mode operation,
n Notebook Computers external control of the burst clamp level allows the output
n Portable Instruments voltage ripple to be adjusted according to the application
n Distributed Power Systems requirements.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.

TYPICAL APPLICATION
22µF
VIN Efficiency and Power Loss
3.3V
100 100000
PVIN SVIN 95 EFFICIENCY
2.2M RT PGOOD 90 10000
0.47µH
294k LTC3412A VOUT 85
POWER LOSS (mW)

SW
2.5V AT 3A
EFFICIENCY (%)

COUT 80 1000
RUN/SS PGND 100µF 75
1000pF 12.1k ×2
ITH SGND 70 100
SYNC/MODE VFB
65
820pF POWER LOSS
60 10
69.8k 392k
115k 55
3412A F01a
50 1
0.01 0.1 1 10
LOAD CURRENT (A)
Figure 1. 2.5V/3A Step-Down Regulator 3412A F01b

Rev. G

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LTC3412A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage..................................... –0.3V to 6V Operating Junction Temperature Range (Notes 2, 5)
ITH, RUN/SS, VFB, PGOOD, E-, I-Grades........................................– 40°C to 125°C
SYNC/MODE Voltages.....................................–0.3 to VIN MP-Grade...........................................– 55°C to 125°C
SW Voltages...................................–0.3V to (VIN + 0.3V) Storage Temperature Range.....................–65°C to150°C
Lead Temperature (Soldering, 10 sec)................... 300°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW

SYNC/MODE
SVIN 1 16 PVIN

VFB
2 15 SW

ITH
PGOOD

RT
ITH 3 14 SW 16 15 14 13

VFB 4 13 PGND RUN/SS 1 12 PGOOD

17
RT 5 12 PGND SGND 2 11 SVIN
17
6 PVIN 3 10 PVIN
SYNC/MODE 11 SW
SW 4 9 SW
RUN/SS 7 10 SW
5 6 7 8
SGND 8 9 PVIN

SW
PGND
PGND
SW
FE PACKAGE
16-LEAD PLASTIC TSSOP UF PACKAGE
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W 16-LEAD (4mm × 4mm) PLASTIC QFN
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 37°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE CONNECTED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3412AEFE#PBF LTC3412AEFE#TRPBF 3412AEFE 16-Lead Plastic TSSOP –40°C to 125°C
LTC3412AIFE#PBF LTC3412AIFE#TRPBF 3412AIFE 16-Lead Plastic TSSOP –40°C to 125°C
LTC3412AMPFE#PBF LTC3412AMPFE#TRPBF 3412AMPFE 16-Lead Plastic TSSOP –55°C to 125°C
LTC3412AEUF#PBF LTC3412AEUF#TRPBF 3412A 16-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LTC3412AIUF#PBF LTC3412AIUF#TRPBF 3412A 16-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3412AEFE LTC3412AEFE#TR 3412AEFE 16-Lead Plastic TSSOP –40°C to 125°C
LTC3412AIFE LTC3412AIFE#TR 3412AIFE 16-Lead Plastic TSSOP –40°C to 125°C
LTC3412AMPFE LTC3412AMPFE#TR 3412AMPFE 16-Lead Plastic TSSOP –55°C to 125°C
LTC3412AEUF LTC3412AEUF#TR 3412A 16-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LTC3412AIUF LTC3412AIUF#TR 3412A 16-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev. G

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 LTC3412A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SVIN Signal Input Voltage Range 2.25 5.5 V
VFB Regulated Feedback Voltage (Note 3)
E-, I-Grades l 0.784 0.800 0.816 V
MP-Grade l 0.780 0.800 0.816 V
IFB Voltage Feedback Leakage Current 0.1 0.2 µA
∆VFB Reference Voltage Line Regulation VIN = 2.7V to 5.5V (Note 3) l 0.04 0.2 %V
VLOADREG Output Voltage Load Regulation Measured in Servo Loop, VITH = 0.36V l 0.02 0.2 %
Measured in Servo Loop, VITH = 0.84V l –0.02 –0.2 %
∆VPGOOD Power Good Range ±7.5 ±9 %
RPGOOD Power Good Pull-Down Resistance 120 200 Ω
IQ Input DC Bias Current (Note 4)
Active Current VFB = 0.78V, VITH = 1V 250 330 µA
Sleep VFB = 1V, VITH = 0V 64 80 µA
Shutdown VRUN = 0V, VMODE = 0V 0.02 1 µA
fOSC Switching Frequency ROSC = 294kΩ 0.88 1 1.1 MHz
Switching Frequency Range (Note 6) 0.3 4 MHz
fSYNC SYNC Capture Range (Note 6) 0.3 4 MHz
RPFET RDS(ON) of P-Channel FET ISW = 1A (Note 7) 77 110 mΩ
RNFET RDS(ON) of N-Channel FET ISW = –1A (Note 7) 65 90 mΩ
ILIMIT Peak Current Limit 4.5 6 A
VUVLO Undervoltage Lockout Threshold 1.75 2 2.25 V
ILSW SW Leakage Current VRUN = 0V, VIN = 5.5V 0.1 1 µA
VRUN RUN Threshold 0.5 0.65 0.8 V
IRUN RUN/SS Leakage Current 1 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: The LTC3412A is tested in a feedback loop that adjusts VFB to
may cause permanent damage to the device. Exposure to any Absolute achieve a specified error amplifier output voltage (ITH).
Maximum Rating condition for extended periods may affect device Note 4: Dynamic supply current is higher due to the internal gate charge
reliability and lifetime. being delivered at the switching frequency.
Note 2: The LTC3412AE is guaranteed to meet performance specifications Note 5: TJ is calculated from the ambient temperature TA and power
from 0°C to 85°C. Specifications over the – 40°C to 125°C operating dissipation as follows: LTC3412AFE: TJ = TA + PD (38°C/W)
junction temperature range are assured by design, characterization and LTC3412AUF: TJ = TA + PD (34°C/W)
correlation with statistical process controls. The LTC3412AI is guaranteed Note 6: 4MHz operation is guaranteed by design and not production tested.
to meet performance specifications over the –40°C to 125°C operating
Note 7: Switch on resistance is guaranteed by design and test condition in
junction temperature range. The LTC3412AMP is guaranteed and tested to
the UF package and by final test correlation in the FE package.
meet performance specifications over the full –55°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.

Rev. G

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LTC3412A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current, Efficiency vs Load Current,
Efficiency vs Load Current Burst Mode Operation Forced Continuous Operation
100 100 100
90 95 VIN = 3.3V 90 VIN = 3.3V
Burst Mode
80 OPERATION 90 80
VIN = 5V VIN = 5V
70 85 70
FORCED
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
60 CONTINUOUS 80 60
50 75 50
40 70 40
30 65 30
20 VIN = 3.3V 60 20
10 VOUT = 2.5V 55 VOUT = 2.5V 10 VOUT = 2.5V
FIGURE 4 CIRCUIT FIGURE 4 CIRCUIT FIGURE 4 CIRCUIT
0 50 0
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
3412A GO1 3412A GO2 3412A GO3

Efficiency vs Input Voltage Efficiency vs Frequency Load Regulation

94 96 0
FIGURE 4 CIRCUIT FIGURE 4 CIRCUIT FIGURE 4 CIRCUIT
95 VIN = 3.3V VIN = 3.3V
92 1µH –0.1
1A 94 0.22µH
90
93 0.47µH –0.2

∆VOUT/VOUT (%)
EFFICIENCY (%)
EFFICIENCY (%)

0.1A
88 92
–0.3
86 91

90 –0.4
84
3A 89
82 –0.5
88

80 87 –0.6
2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT VOLTAGE (V) FREQUENCY (MHz) LOAD CURRENT (A)
3412A GO4 3412A GO5 3412A GO6

Load Step Transient Burst Mode

Burst Mode Operation Output Voltage Ripple Operation

BURST
VOUT
MODE
20mV/DIV VOUT
20mV/DIV
100mV/DIV
PULSE
SKIPPING
20mV/DIV
INDUCTOR
CURRENT FORCED
INDUCTOR
1A/DIV CONTINUOUS
CURRENT
20mV/DIV
2A/DIV

FIGURE 4 CIRCUIT 5µs/DIV VIN = 3.3V 5µs/DIV VIN = 3.3V 40µs/DIV

VOUT = 2.5V VOUT = 2.5V
3412A GO7 FIGURE 4 CIRCUIT 3412A GO8 F = 1MHz 3412A GO9
LOAD STEP = 50mA TO 2A
FIGURE 4 CIRCUIT

Rev. G

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 LTC3412A
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Transient Forced
Continuous Start-Up Transient VREF vs Temperature
0.7975
VIN = 3.3V
VOUT 0.7970
2V/DIV
VOUT 0.7965
100mV/DIV
0.7960

0.7955

VREF (V)
RUN/SS
2V/DIV 0.7950
INDUCTOR
0.7945
CURRENT INDUCTOR
2A/DIV CURRENT 0.7940
2A/DIV
0.7935

0.7930
VIN = 3.3V 40µs/DIV VIN = 3.3V 1ms/DIV –45 –25 –5 15 35 55 75 95 115
VOUT =2.5V VOUT =2.5V TEMPERATURE (°C)
f = 1MHz 3412A G10 LOAD STEP = 2A 3412A G11 3412A G12
LOAD STEP = 0A TO 3A FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT

Switch On-Resistance Switch On-Resistance Switch Leakage Current

vs Input Voltage vs Temperature vs Input Voltage
100 120 50
VIN = 3.3V
95 45
100

SWITCH LEAKAGE CURRENT (nA)

90 40
ON-RESISTANCE (mΩ)

ON-RESISTANCE (mΩ)

85 35
PFET 80
PFET
80 30
75 60 25
NFET PFET
70 20
NFET 40
65 15
60 10
20
55 5
NFET
50 0 0
2.5 3.0 3.5 4.0 4.5 5.0 –40 –20 0 20 40 60 80 100 120 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V) TEMPERATURE (°C) INPUT VOLTAGE (V)
3412A G13 3412A G14 3412A G15

Frequency vs ROSC Frequency vs Input Voltage Frequency vs Temperature

5000 1060 1020
VIN = 3.3V ROSC = 294k VIN = 3.3V
4500 1015 ROSC = 294k
1050
4000 1010
3500 1040 1005
FREQUENCY (kHz)
FREQUENCY (kHz)

FREQUENCY (kHz)

3000 1030 1000

2500 995
1020
2000 990
1500 1010 985
1000 980
1000
500 975
0 990 970
40 140 240 340 440 540 640 740 840 940 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100 120
ROSC (kΩ) INPUT VOLTAGE (V) TEMPERATURE (°C)
3412A G16 3412A G17 3412A G18

Rev. G

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LTC3412A
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
vs Input Voltage Quiescent Current vs Temperature
350 350
VIN = 3.3V
300 ACTIVE 300 ACTIVE
QUIESCENT CURRENT (µA)

QUIESCENT CURRENT (µA)

250 250

200 200

150 150

100 100
SLEEP SLEEP
50 50

0 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100 120
INPUT VOLTAGE (V) TEMPERATURE (°C)
3412A G19 3412A G20

Minimum Peak Inductor Current

vs Burst Clamp Voltage Peak Current vs Input Voltage
4000 8.0
MAXIMUM PEAK INDUCTOR CURRENT (mA)

3500 7.5
PEAK INDUCTOR CURRENT (A)

3000 7.0

2500 6.5

2000 6.0

1500 5.5

1000 5.0

500 4.5

0 4.0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 2.25 2.75 3.25 3.75 4.25 4.75
VBURST (V) INPUT VOLTAGE (V)
3412A G22
3412A G21

Rev. G

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 LTC3412A
PIN FUNCTIONS (FE/UHF)

SVIN (Pin 1/Pin 11): Signal Input Supply. Decouple this RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
pin to SGND with a capacitor. Forcing this pin below 0.5V shuts down the LTC3412A.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain In shutdown all functions are disabled drawing <1µA of
logic output that is pulled to ground when the output volt- supply current. A capacitor to ground from this pin sets
age is not within ±7.5% of regulation point. the ramp time to full output current.

ITH (Pin 3/Pin 13): Error Amplifier Compensation Point. SGND (Pin 8/Pin 2): Signal Ground. All small-signal com-
ponents, compensation components and the exposed pad
The current comparator threshold increases with this
on the bottom side of the IC should connect to this ground,
control voltage. Nominal voltage range for this pin is from
which in turn connects to PGND at one point.
0.2V to 1.4V with 0.4V corresponding to the zero-sense
voltage (zero current). PVIN (Pins 9, 16/Pins 3, 10): Power Input Supply. Decouple
this pin to PGND with a capacitor.
VFB (Pin 4/Pin 14): Feedback Pin. Receives the feedback
voltage from a resistive divider connected across the SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
output. Connection to the Inductor. This pin connects to the drains
RT (Pin 5/Pin 15): Oscillator Resistor Input. Connecting of the internal main and synchronous power MOSFET
a resistor to ground from this pin sets the switching switches.
frequency. PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
SYNC/MODE (Pin 6/Pin 16): Mode Select and External this pin close to the (–) terminal of CIN and COUT .
Clock Synchronization Input. To select forced continuous, Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
tie to SVIN. Connecting this pin to a voltage between 0V soldered to PCB for electrical connection and rated thermal
and 1V selects Burst Mode operation with the burst clamp performance.
set to the pin voltage.

Rev. G

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LTC3412A
FUNCTIONAL BLOCK DIAGRAM
PVIN
SVIN SGND ITH
1 8 3 9 16

VOLTAGE SLOPE PMOS CURRENT

REFERENCE COMPENSATION COMPARATOR
RECOVERY
0.8V
BCLAMP +
+
– – P-CH
VFB 4 – ERROR
AMPLIFIER +
SYNC/MODE + BURST
– COMPARATOR
0.74V + 10
SLOPE
11
COMPENSATION
– OSCILLATOR SW
14

15
+
RUN/SS 7 RUN N-CH
LOGIC
0.86V – +
PGOOD 2
–
NMOS
CURRENT
COMPARATOR
–

+
REVERSE 12
CURRENT PGND
COMPARATOR 13

5 6 3412 FBD
RT SYNC/MODE

OPERATION
Main Control Loop comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.8V reference. When the load
The LTC3412A is a monolithic, constant-frequency, current
current increases, it causes a reduction in the feedback
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is voltage relative to the reference. The error amplifier raises
turned on at the beginning of each clock cycle. Current in the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
the inductor increases until the current comparator trips
off, the synchronous power switch (N-channel MOSFET)
and turns off the top power MOSFET. The peak inductor
turns on until either the bottom current limit is reached or
current at which the current comparator shuts off the top
the beginning of the next clock cycle. The bottom current
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by limit is set at –1.3A for forced continuous mode and 0A
for Burst Mode operation.

Rev. G

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 LTC3412A
OPERATION
The operating frequency is externally set by an external Pulse-skipping operation is implemented by connecting
resistor connected between the RT pin and ground. The the SYNC/MODE pin to ground. This forces the burst
practical switching frequency can range from 300kHz to clamp level to be at 0V. As the load current decreases, the
4MHz. peak inductor current will be determined by the voltage
Overvoltage and undervoltage comparators will pull the on the ITH pin until the ITH voltage drops below 400mV. At
this point, the peak inductor current is determined by the
PGOOD output low if the output voltage comes out of
minimum on-time of the current comparator. If the load
regulation by ±7.5%. In an overvoltage condition, the top
demand is less than the average of the minimum on-time
power MOSFET is turned off and the bottom power MOSFET
inductor current, switching cycles will be skipped to keep
is switched on until either the overvoltage condition clears
the output voltage in regulation.
or the bottom MOSFET’s current limit is reached.
Frequency Synchronization
Forced Continuous Mode
The internal oscillator of the LTC3412A can be synchro-
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation. nized to an external clock connected to the SYNC/MODE
At light loads, forced continuous mode operation is less pin. The frequency of the external clock can be in the
efficient than Burst Mode operation, but may be desirable in range of 300kHz to 4MHz. For this application, the oscil-
lator timing resistor should be chosen to correspond to
some applications where it is necessary to keep switching
a frequency that is 25% lower than the synchronization
harmonics out of a signal band. The output voltage ripple
frequency. During synchronization, the burst clamp is set
is minimized in this mode.
to 0V, and each switching cycle begins at the falling edge
Burst Mode Operation of the clock signal.

Connecting the SYNC/MODE pin to a voltage in the range Dropout Operation

of 0V to 1V enables Burst Mode operation. In Burst Mode
When the input supply voltage decreases toward the output
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz- voltage, the duty cycle increases toward the maximum
ing switching losses. During Burst Mode operation, the on-time. Further reduction of the supply voltage forces
minimum peak inductor current is externally set by the the main switch to remain on for more than one cycle
voltage on the SYNC/MODE pin and the voltage on the ITH eventually reaching 100% duty cycle. The output voltage
pin is monitored by the burst comparator to determine will then be determined by the input voltage minus the
when sleep mode is enabled and disabled. When the voltage drop across the internal P-channel MOSFET and
average inductor current is greater than the load current, the inductor.
the voltage on the ITH pin drops. As the ITH voltage falls
Low Supply Operation
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MOSFET The LTC3412A is designed to operate down to an input
is held off and the ITH pin is disconnected from the output supply voltage of 2.25V. One important consideration at low
of the error amplifier. The majority of the internal circuitry input supply voltages is that the RDS(ON) of the P-channel
is also turned off to reduce the quiescent current to 64µA and N-channel power switches increases. The user should
while the load current is solely supplied by the output calculate the power dissipation when the LTC3412A is used
capacitor. When the output voltage drops, the ITH pin is at 100% duty cycle with low input voltages to ensure that
reconnected to the output of the error amplifier and the thermal limits are not exceeded.
top power MOSFET along with all the internal circuitry is
switched back on. This process repeats at a rate that is
dependent on the load demand.
Rev. G

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LTC3412A
APPLICATIONS INFORMATION
Slope Compensation and Inductor Peak Current Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412A imposes a minimum
Slope compensation provides stability in constant fre-
limit on the operating duty cycle. The minimum on-time
quency architectures by preventing subharmonic oscilla-
is typically 110ns; therefore, the minimum duty cycle is
tions at duty cycles greater than 50%. It is accomplished
equal to 100 • 110ns • f(Hz).
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally, Inductor Selection
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412A, however, For a given input and output voltage, the inductor value
slope compensation recovery is implemented to keep the and operating frequency determine the ripple current. The
maximum inductor peak current constant throughout the ripple current ∆IL increases with higher VIN or VOUT and
range of duty cycles. This keeps the maximum output decreases with higher inductance.
current relatively constant regardless of duty cycle. ⎛V ⎞⎛ V ⎞
ΔIL = ⎜ OUT ⎟ ⎜ 1– OUT ⎟
⎝ fL ⎠ ⎝ VIN ⎠
Short-Circuit Protection
When the output is shorted to ground, the inductor cur- Having a lower ripple current reduces the core losses in
rent decays very slowly during a single switching cycle. the inductor, the ESR losses in the output capacitors, and
To prevent current runaway from occurring, a secondary the output voltage ripple. Highest efficiency operation is
current limit is imposed on the inductor current. If the achieved at low frequency with small ripple current. This,
inductor valley current increases larger than 4.4A, the top however, requires a large inductor.
power MOSFET will be held off and switching cycles will A reasonable starting point for selecting the ripple current
be skipped until the inductor current is reduced. is ∆IL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
The basic LTC3412A application circuit is shown in Fig-
below a specified maximum, the inductor value should
ure 1. External component selection is determined by the
be chosen according to the following equation:
maximum load current and begins with the selection of
the operating frequency and inductor value followed by ⎛ V ⎞⎛ VOUT ⎞
L=⎜ OUT
CIN and COUT. ⎟ ⎜ 1– ⎟
⎝ fΔIL(MAX) ⎠ ⎝ VIN(MAX) ⎠
Operating Frequency The inductor value will also have an effect on Burst Mode
Selection of the operating frequency is a trade-off between operation. The transition to low current operation begins
efficiency and component size. High frequency operation when the peak inductor current falls below a level set by
allows the use of smaller inductor and capacitor values. the burst clamp. Lower inductor values result in higher
Operation at lower frequencies improves efficiency by ripple current which causes this to occur at lower load
reducing internal gate charge losses but requires larger currents. This causes a dip in efficiency in the upper
inductance values and/or capacitance to maintain low range of low current operation. In Burst Mode operation,
output ripple voltage. lower inductance values will cause the burst frequency
The operating frequency of the LTC3412A is determined to increase.
by an external resistor that is connected between pin RT
Inductor Core Selection
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing Once the value for L is known, the type of inductor must
capacitor within the oscillator and can be calculated by be selected. Actual core loss is independent of core size
using the following equation: for a fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
3.08•1011 losses decrease. Unfortunately, increased inductance
R OSC = (Ω) –10kΩ
f requires more turns of wire and therefore copper losses
will increase.
Rev. G

10 For more information www.analog.com

 LTC3412A
APPLICATIONS INFORMATION
Ferrite designs have very low core losses and are pre- capacitance that is necessary to ensure that the control
ferred at high switching frequencies, so design goals can loop is stable. Loop stability can be checked by viewing
concentrate on copper loss and preventing saturation. the load transient response as described in a later section.
Ferrite core material saturates “hard,” which means that The output ripple, ∆VOUT, is determined by:
inductance collapses abruptly when the peak design current ⎛ 1 ⎞
is exceeded. This results in an abrupt increase in inductor ΔVOUT ≤ ΔIL ⎜ ESR +
ripple current and consequent output voltage ripple. Do ⎝ 8fCOUT ⎟⎠
not allow the core to saturate!
The output ripple is highest at maximum input voltage
Different core materials and shapes will change the size/cur- since ∆IL increases with input voltage. Multiple capacitors
rent and price/current relationship of an inductor. Toroid placed in parallel may be needed to meet the ESR and
or shielded pot cores in ferrite or permalloy materials are RMS current handling requirements. Dry tantalum, special
small and don’t radiate much energy, but generally cost polymer, aluminum electrolytic, and ceramic capacitors are
more than powdered iron core inductors with similar all available in surface mount packages. Special polymer
characteristics. The choice of which style inductor to use capacitors offer very low ESR but have lower capacitance
mainly depends on the price verus size requirements and density than other types. Tantalum capacitors have the
any radiated field/EMI requirements. New designs for highest capacitance density but it is important to only
surface mount inductors are available from Coiltronics, use types that have been surge tested for use in switching
Coilcraft, Toko and Sumida. power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
CIN and COUT Selection applications provided that consideration is given to ripple
The input capacitance, CIN, is needed to filter the trapezoidal current ratings and long-term reliability. Ceramic capacitors
wave current at the source of the top MOSFET. To prevent have excellent low ESR characteristics but can have a high
large voltage transients from occurring, a low ESR input voltage coefficient and audible piezoelectric effects. The
capacitor sized for the maximum RMS current should be high Q of ceramic capacitors with trace inductance can
used. The maximum RMS current is given by: also lead to significant ringing.

V VIN Using Ceramic Input and Output Capacitors

IRMS = IOUT(MAX) OUT –1
VIN VOUT Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
This formula has a maximum at VIN = 2VOUT, where
current, high voltage rating and low ESR make them ideal
IRMS = IOUT/2. This simple worst-case condition is com-
for switching regulator applications. However, care must
monly used for design because even significant deviations
be taken when these capacitors are used at the input and
do not offer much relief. Note that ripple current ratings
output. When a ceramic capacitor is used at the input and
from capacitor manufacturers are often based on only
the power is supplied by a wall adapter through long wires,
2000 hours of life which makes it advisable to further
a load step at the output can induce ringing at the input,
derate the capacitor, or choose a capacitor rated at a higher
VIN. At best, this ringing can couple to the output and be
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the mistaken as loop instability. At worst, a sudden inrush
design. For low input voltage applications, sufficient bulk of current through the long wires can potentially cause a
input capacitance is needed to minimize transient effects voltage spike at VIN large enough to damage the part.
during output load changes. When choosing the input and output ceramic capacitors,
The selection of COUT is determined by the effective series choose the X5R or X7R dielectric formulations. These
resistance (ESR) that is required to minimize voltage ripple dielectrics have the best temperature and voltage charac-
and load step transients as well as the amount of bulk teristics of all the ceramics for a given value and size.
Rev. G

For more information www.analog.com 11

LTC3412A
APPLICATIONS INFORMATION
Output Voltage Programming The value for IBURST is determined by the desired amount
of output voltage ripple. As the value of IBURST increases,
The output voltage is set by an external resistive divider
the sleep period between pulses and the output voltage
according to the following equation:
ripple increase. The burst clamp voltage, VBURST, can be
⎛ R2 ⎞ set by a resistor divider from the VFB pin to the SGND pin
VOUT = 0.8V ⎜ 1+ ⎟
⎝ R1⎠ as shown in Figure 1.
Pulse skipping, which is a compromise between low out-
The resistive divider allows pin VFB to sense a fraction of put voltage ripple and efficiency, can be implemented by
the output voltage as shown in Figure 2. connecting pin SYNC/MODEto ground. This sets IBURST to
VOUT 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
R2 lowest output voltage ripple is achieved while still operat-
VFB ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
LTC3412A R1
while maintaining the output voltage in regulation.
SGND
3412A F02 Frequency Synchronization
Figure 2. Setting the Output Voltage The LTC3412A’s internal oscillator can be synchronized
to an external clock signal. During synchronization, the
Burst Clamp Programming top MOSFET turn-on is locked to the falling edge of the
If the voltage on the SYNC/MODE pin is less than VIN by external frequency source. The synchronization frequency
1V, Burst Mode operation is enabled. During Burst Mode range is 300kHz to 4MHz. Synchronization only occurs if
Operation, the voltage on the SYNC/MODE pin determines the external frequency is greater than the frequency set
the burst clamp level, which sets the minimum peak by the external resistor. Because slope compensation
inductor current, IBURST. To select the burst clamp level, is generated by the oscillator’s RC circuit, the external
use the graph of Minimum Peak Inductor Current vs Burst frequency should be set 25% higher than the frequency
Clamp Voltage in the Typical Performance Characteristics set by the external resistor to ensure that adequate slope
section. compensation is present.
VBURST is the voltage on the SYNC/MODE pin. IBURST Soft-Start
can only be programmed in the range of 0A to 6A. For
values of VBURST greater than 1V, IBURST is set at 6A. For The RUN/SS pin provides a means to shut down the
values of VBURST less than 0.4V, IBURST is set at 0A. As LTC3412A as well as a timer for soft-start. Pulling the
the output load current drops, the peak inductor currents RUN/SS pin below 0.5V places the LTC3412A in a low
decrease to keep the output voltage in regulation. When quiescent current shutdown state (IQ < 1µA).
the output load current demands a peak inductor current The LTC3412A contains an internal soft-start clamp that
that is less than IBURST, the burst clamp will force the peak gradually raises the clamp on ITH after the RUN/SS pin is
inductor current to remain equal to IBURST regardless of pulled above 2V. The full current range becomes available
further reductions in the load current. Since the average on ITH after 1024 switching cycles. If a longer soft-start
inductor current is greater than the output load current, period is desired, the clamp on ITH can be set externally
the voltage on the ITH pin will decrease. When the ITH with a resistor and capacitor on the RUN/SS pin as shown
voltage drops to 150mV, sleep mode is enabled in which in Figure 1. The soft-start duration can be calculated by
both power MOSFETs are shut off along with most of the using the following formula:
circuitry to minimize power consumption. All circuitry is
⎛ VIN ⎞
turned back on and the power MOSFETs begin switching t SS = RSS CSS ln ⎜ (SECONDS)
again when the output voltage drops out of regulation. ⎝ VIN – 1.8V ⎟⎠
Rev. G

12 For more information www.analog.com

 LTC3412A
APPLICATIONS INFORMATION
Efficiency Considerations The RDS(ON) for both the top and bottom MOSFETs can be
The efficiency of a switching regulator is equal to the output obtained from the Typical Performance Characteristics
power divided by the input power times 100%. It is often curves. To obtain I2R losses, simply add RSW to RL and mul-
useful to analyze individual losses to determine what is tiply the result by the square of the average output current.
limiting the efficiency and which change would produce Other losses including CIN and COUT ESR dissipative losses
the most improvement. Efficiency can be expressed as: and inductor core losses generally account for less than
Efficiency = 100% – (L1 + L2 + L3 + ...) 2% of the total loss.

where L1, L2, etc. are the individual losses as a percent- Thermal Considerations
age of input power.
In most applications, the LTC3412A does not dissipate
Although all dissipative elements in the circuit produce much heat due to its high efficiency.
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses. However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
The VIN quiescent current loss dominates the efficiency loss high duty cycles, such as in dropout, the heat dissipated
at very low load currents whereas the I2R loss dominates may exceed the maximum junction temperature of the part.
the efficiency loss at medium to high load currents. In a If the junction temperature reaches approximately 150°C,
typical efficiency plot, the efficiency curve at very low load both power switches will be turned off and the SW node
currents can be misleading since the actual power lost is will become high impedance.
of no consequence.
To avoid the LTC3412A from exceeding the maximum junc-
1. The VIN quiescent current is due to two components: the tion temperature, the user will need to do some thermal
DC bias current as given in the electrical characteristics analysis. The goal of the thermal analysis is to determine
and the internal main switch and synchronous switch whether the power dissipated exceeds the maximum junction
gate charge currents. The gate charge current results temperature of the part. The temperature rise is given by:
from switching the gate capacitance of the internal power
tr = (PD)(θJA)
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves where PD is the power dissipated by the regulator and θJA
from VIN to ground. The resulting dQ/dt is the current is the thermal resistance from the junction of the die to
out of VIN that is typically larger than the DC bias cur- the ambient temperature. For the 16-lead exposed TSSOP
rent. In continuous mode, IGATECHG = f(QT + QB) where package, the θJA is 38°C/W. For the 16-lead QFN package
QT and QB are the gate charges of the internal top and the θJA is 34°C/W.
bottom switches. Both the DC bias and gate charge The junction temperature, TJ, is given by:
losses are proportional to VIN; thus, their effects will
be more pronounced at higher supply voltages. TJ = TA + tr

2. I2R losses are calculated from the resistances of the where TA is the ambient temperature.
internal switches, RSW, and external inductor RL. In Note that at higher supply voltages, the junction tempera-
continuous mode the average output current flowing ture is lower due to reduced switch resistance (RDS(ON)).
through inductor L is “chopped” between the main To maximize the thermal performance of the LTC3412A,
switch and the synchronous switch. Thus, the series the Exposed Pad should be soldered to a ground plane.
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle Checking Transient Response
(DC) as follows: The regulator loop response can be checked by looking
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
Rev. G

For more information www.analog.com 13

LTC3412A
APPLICATIONS INFORMATION
When a load step occurs, VOUT immediately shifts by an Decoupling the PVIN and SVIN pins with two 22µF capaci-
amount equal to ∆ILOAD(ESR), where ESR is the effective tors is adequate for most applications.
series resistance of COUT. ∆ILOAD also begins to charge or The burst clamp and output voltage can now be pro-
discharge COUT generating a feedback error signal used by grammed by choosing the values of R1, R2 and R3. The
the regulator to return VOUT to its steady-state value. During voltage on pin MODE will be set to 0.50V by the resistor
this recovery time, VOUT can be monitored for overshoot divider consisting of R2 and R3. According to the graph
or ringing that would indicate a stability problem. The ITH of Minimum Peak Inductor Current vs Burst Clamp Volt-
pin external components and output capacitor shown in age in the Typical Performance Characteristics section, a
Figure 1 will provide adequate compensation for most burst clamp voltage of 0.5V will set the minimum inductor
applications. current, IBURST, to approximately 1.1A.
Design Example If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
As a design example, consider using the LTC3412A in an
application with the following specifications: R2 + R3 = 185k
VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 3A, R2 0.8V
1+ =
IOUT(MIN) = 100mA, f = 1MHz. R3 0.50V
Because efficiency is important at both high and low load The two equations shown above result in the following
current, Burst Mode operation will be utilized. values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
First, calculate the timing resistor: of R1 can now be determined by solving the following
equation.
3.08 • 1011 R1 2.5V
ROSC = – 10k = 298k 1+ =
1• 106 185k 0.8V
R1 = 392k
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN: A value of 392k will be selected for R1. Figure 4 shows
⎛ ⎞ ⎛ 2.5V ⎞ the complete schematic for this design example.
2.5V
L=⎜ ⎜ 1– ⎟ = 0.51µH
⎝ (1MHz)(1.2A) ⎟⎠ ⎝ 3.3V ⎠ PC Board Layout Checklist

Using a 0.47µH inductor results in a maximum ripple When laying out the printed circuit board, the following
current of: checklist should be used to ensure proper operation of
the LTC3412A. Check the following in your layout:
⎛ 2.5V ⎞ ⎛ 2.5V ⎞
ΔIL = ⎜ 1– = 1.29A 1. A ground plane is recommended. If a ground plane layer
⎝ (1MHz)(0.47µH) ⎟⎠ ⎜⎝ 3.3V ⎟⎠ is not used, the signal and power grounds should be
COUT will be selected based on the ESR that is required to segregated with all small signal components returning
satisfy the output voltage ripple requirement and the bulk to the SGND pin at one point which is then connected
capacitance needed for loop stability. For this design, two to the PGND pin close to the LTC3412A.
100µF ceramic capacitors will be used. 2. Connect the (+) terminal of the input capacitor(s), CIN, as
CIN should be sized for a maximum current rating of: close as possible to the PVIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
⎛ 2.5V ⎞ 3.3V
IRMS = (3A) ⎜ – 1= 1.29ARMS
⎝ 3.3V ⎟⎠ 2.5V

Rev. G

14 For more information www.analog.com

 LTC3412A
APPLICATIONS INFORMATION
3. Keep the switching node, SW, away from all sensitive 5. Connect the VFB pin directly to the feedback resistors.
small-signal nodes. The resistor divider must be connected between VOUT
and SGND.
4. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PVIN, SVIN, VOUT, PGND, SGND, or any other
DC rail in your system).

Top Bottom

Figure 3. LTC3412A Layout Diagram

VIN
3.3V
CFF 22pF X5R
R1 392k CIN3**
100µF

1 16
SVIN PVIN
RPG CIN1
100k 22µF
2 15
PGOOD PGOOD SW
CITH 330pF X7R RITH
17.4k 3 14
ITH SW
CC
LTC3412A
47pF 13 L1*
EFE PGND
4 0.47µH VOUT
VFB 2.5V
R3 R2 12
PGND 3A
115k 69.8k 5
RT
ROSC 11
RSS 294k 6 SYNC/MODE SW

2.2M COUT**
7 10 100µF
RUN SW
CSS ×2
1000pF X7R 8 9
SGND PVIN
CIN2
22µF GND
X5R 6.3V
3412 F04
*VISHAY IHLP-2525CZ-01
**TDK 4532X5R0J107M

Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation

Rev. G

For more information www.analog.com 15

LTC3412A
TYPICAL APPLICATIONS
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
VIN
3.3V
C1 22pF X5R
R1 95.3k

11 10
SVIN PVIN
CIN1
RPG 10µF
100k 12 9 X5R 6.3V
PGOOD PGOOD SW
CITH 1000pF X7R RITH
6.34k 13 8
ITH SW
CC LTC3412A
22pF EUF 7 L1*
14 PGND 0.47µH VOUT
VFB 1.2V
R2 6 3A
187k 15 PGND
RT
ROSC 5
196k 16 SW
RSS COUT**
SYNC/MODE
2.2M 22µF
1 4 X3
RUN SW
CSS
1000pF X7R 2 3
SGND PVIN
CIN2
10µF GND
X5R 6.3V
3412 TA01
*COOPER SD10-R47
**TAIYO YUDEN AMK212BJ226MD-B

1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation

VIN
C1 47pF X5R 2.5V
CIN3**
100µF
R1 232k

1 16
SVIN PVIN CIN1
RPG 22µF
100k 2 15 X5R 6.3V
PGOOD PGOOD SW
CITH 820pF X7R RITH
15k 3 14
ITH SW
C2
47pF LTC3412A
EFE 13 L1
4 PGND 0.47µH* VOUT
VFB 1.8V
R3 R2 12 3A
115k 69.8k 5 PGND
RT
ROSC 11
294k 6 SW COUT**
RSS SYNC/MODE 100µF
2.2M 7 10 ×3
RUN SW
CSS
1000pF X7R 8 9
SGND PVIN
CIN2
22µF
X5R 6.3V 3412 TA02
GND
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M

Rev. G

16 For more information www.analog.com

 LTC3412A
TYPICAL APPLICATIONS
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
VIN
CIN3** 5V
C1 22pF X5R 100µF
R1 634k

1 16
SVIN PVIN
CIN1
RPG
22µF
100k 2 15 X5R 6.3V
PGOOD PGOOD SW
CITH 820pF X7R RITH
7.5k 3 14
ITH SW
CC
LTC3412A
47pF 4 13 L1*
EFE PGND 0.47µH VOUT
VFB 3.3V
R2 12
PGND 3A
200k 5
RT
ROSC 11
137k 6 SW
COUT**
SYNC/MODE
100µF
7 10 ×2
RUN SW
RSS CSS
2.2M 1000pF X7R 8 9
SGND PVIN
CIN2
22µF GND
X5R 6.3V
3412 TA03

*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M

2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz

VIN
3.3V
C1 22pF X5R
R1 392k

1 16
SVIN PVIN
RPG CIN1
100k 22µF
2 15 X5R 6.3V
PGOOD PGOOD SW
CITH 220pF X7R RITH
6.49k 3 14
ITH SW
CC 22pF LTC3412A
EFE 13 L1*
4 PGND 0.47µH VOUT
VFB 1.5V
R2 162k 12 3A
5 PGND
RT
ROSC 182k 11
1.8MHz 6 SYNC/MODE
SW + COUT**
RSS
2.2M EXT CLOCK 7 150µF
10
RUN SW
CSS
1000pF X7R 8 9
SGND PVIN
CIN2
22µF GND
X5R 6.3V
3412 TA04
*COOPER SD20-R47
**SANYO POSCAP 4TPE150MAZB
Rev. G

For more information www.analog.com 17

LTC3412A
PACKAGE DESCRIPTION

FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation BA

4.90 – 5.10*
2.74 (.193 – .201)
(.108)
2.74
(.108)
16 1514 13 12 1110 9

6.60 ±0.10
2.74
4.50 ±0.10 (.108)
SEE NOTE 4 2.74 6.40
(.108) (.252)
0.45 ±0.05 BSC

1.05 ±0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8
1.10
4.30 – 4.50* (.0433)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE16 (BA) TSSOP REV L 0117
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692 Rev Ø)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
4.00 ±0.10 0.75 ±0.05 R = 0.115 OR 0.35 × 45° CHAMFER
(4 SIDES) TYP
15 16
0.72 ±0.05
PIN 1 0.55 ±0.20
TOP MARK
(NOTE 6) 1

2
4.35 ±0.05 2.15 ±0.05 2.15 ±0.10
2.90 ±0.05 (4 SIDES) (4-SIDES)

PACKAGE
OUTLINE (UF16) QFN 10-04

0.30 ±0.05 0.200 REF 0.30 ±0.05

0.65 BSC 0.00 – 0.05 0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

Rev. G

18 For more information www.analog.com

 LTC3412A
REVISION HISTORY (Revision history begins at Rev E)

REV DATE DESCRIPTION PAGE NUMBER

E 03/10 Changed Temperature Range for E- and I-Grades to –40°C to 125°C in Absolute Maximum Ratings and Order 2
Information Sections
Changed from TA = 25°C to TA ≈ TJ = 25°C in the Electrical Characteristics Heading 3
Updated Note 2 3
F 05/17 Add Storage Temperature to Absolute Maximum Ratings 2
G 02/21 Added LTC3412AMPFE#PBF/TRPBF to Ordering Table 2

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 19
LTC3412A
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LTC3440 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V, IQ =
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LTC3441 1.2A (IOUT), 1MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ =
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Rev. G

20
02/21
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