EE3404 (MP&MC)

[Regulation-2021]

Microprocessor & Microcontroller

(Second Year, 4th Semester EEE)

Unit 5
Introduction to RISC-based
Architecture
MP&MC/EE3404 Lecture Notes
by
Dr.I.William Christopher
Asso.Prof/EEE Dept./LICET
6/9/2024 EE3404/MPMC/Unit-5 1
 Course Objectives
▪ To study the addressing modes & instruction set of 8085
& 8051

▪ To develop skills in simple program writing in assembly

languages

▪ To introduce commonly used peripheral/interfacing ICs.

▪ To study and understand typical applications of micro-

processors.

▪ To study and understand the typical applications of

micro-controllers
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 Course Outcomes
Upon successful completion of the course, the students should have
the:
C01 Ability to write assembly language program for microprocessor
and microcontroller
C02 Ability to design and implement interfacing of peripheral with
microprocessor and microcontroller
C03 Ability to analyze, comprehend, design and simulate
microprocessor based systems used for control and monitoring.
C04 Ability to analyze, comprehend, design and simulate
microcontroller based systems used for control and monitoring.
C05 Ability to understand and appreciate advanced architecture
evolving microprocessor field

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 Units of Microprocessor & Microcontroller
The Course deals with the following Units:
Unit –I : Introduction to 8085 Architecture

Unit –II : 8085 Instruction Set and Programming

Unit –III : Interfacing Basics and ICs

Unit –IV : Introduction to 8051 Microcontroller

Unit –V : Introduction to RISC Based Architecture

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 Text and Reference Books
Textbooks:
1) Ramesh S. Gaonkar, ‘Microprocessor Architecture Programming and
Application’, Pen ram International (P)ltd., Mumbai, 6th Education, 2013.
2) Muhammad Ali Mazidi & Janice Gilli Mazidi, ‘The 8051 Micro Controller
and Embedded Systems’, Pearson Education, Second Edition 2011.
3) Muhammad Ali Mazidi & Janice Gilli Mazidi, ‘The PIC Micro Controller
and Embedded Systems’, 2010
Reference Books:
1) Douglas V. Hall, “Micro-processors & Interfacing”, Tata McGraw Hill 3rd
Edition, 2017.
2) Krishna Kant, “Micro-processors & Micro-controllers”, Prentice Hall of
India, 2007.
3) Mike Predko, “8051 Micro-controllers”, McGraw Hill, 2009
4) Kenneth Ayala, ‘The 8051 Microcontroller’, Thomson, 3rd Edition 2004.
6/9/2024 EE3404/MPMC/Unit-5 5
 Unit-I: Introduction to 8085 Architecture

Topics to be discussed:
▪ Functional Block Diagram

▪ Memory Interfacing

▪ I/O Ports and Data Transfer Concepts

▪ Timing Diagram

▪ Interrupt Structure

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 Unit-II: 8085 Instruction Set and Programming
Topics to be discussed:
▪ Instruction Format and Addressing Modes
▪ Assembly Language Format
▪ Data Transfer, Data Manipulation &
Control Instructions
▪ Programming:
✓Loop structure with Counting & Indexing
✓Look up table
✓Subroutine instructions
✓Stack
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 Unit-III: Interfacing Basics and ICs
Topics to be discussed:
▪ Study of Architecture and programming of ICs:
✓ 8255 - PPI
✓ 8259 - PIC
✓ 8251 - USART
✓ 8279 - Keyboard display controller
✓ 8254 - Timer/Counter
▪ Interfacing with 8085
✓A/D and D/A converter interfacing
6/9/2024 EE3404/MPMC/Unit-5 8
 Unit-IV: Introduction to 8051 Microcontroller
Topics to be discussed:
▪ Functional Block Diagram
▪ Instruction Format And Addressing Modes
▪ Interrupt Structure
▪ Timer
▪ I/O Ports
▪ Serial Communication
▪ Simple Programming
▪ Keyboard And Display Interface
▪ Temperature Control System
▪ Stepper Motor Control
▪ Usage of IDE for Assembly Language Programming
6/9/2024 EE3404/MPMC/Unit-5 9
 Unit-V: Introduction to RISC Based Architecture
Topics to be discussed:
▪ PIC16 /18 Architecture
▪ Memory Organization
▪ Addressing Modes
▪ Instruction Set
▪ Programming Techniques
▪ Timers
▪ I/O Ports
▪ Interrupt Programming
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 Introduction (1)
Microcontroller Vs General-purpose Microprocessor

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 Introduction (2)
Companies that produce widely used 8-bit Microcontrollers

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 Brief History of PIC- Microcontroller (1)
▪ In 1989, Microchip Technology Corporation introduced an 8-
bit Microcontroller

▪ PIC – Peripheral Interface Controller.

▪ It had small amounts of data RAM, a few hundred bytes of on-

chip ROM for the program, one-timer and a few pins for I/O
ports, all on a single chip with only 8-pins.

▪ Since the introduction of the PIC16xxx, they have introduced

an array of 8-bit microcontrollers too numerous to list here…

▪ They include the PIC families of 10xxx, 12xxx, 14xxx, 16xxx,

17xxx and 18xxx.
6/9/2024 EE3404/MPMC/Unit-5 13
 Brief History of PIC- Microcontroller (2)
▪ They all 8-bit processors, meaning that the CPU can work on
only 8-bits of data at a time

▪ Data larger than 8-bits has to be broken into 8-bit pieces to be

processed by the CPU.

▪ For example, while the 12xxx/16xxx have 12-bit and 14-bit

wide instructions, the PIC18xxx instruction is 16 bits wide with
many new instructions

▪ PIC18xxx family has the highest performance of all the families

of 8-bit PIC controllers.

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 PIC- Microcontroller Core Features (1)
▪ High-performance RISC CPU
▪ Only 35 single-word instructions to learn
▪ All single-cycle instructions except for program branches which
are two-cycle
▪ Operating speed: DC - 20 MHz clock input DC - 200 ns instruction
cycle
▪ Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8
bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM
Data Memory
▪ Pinout compatible to the PIC16C73B/74B/76/77
▪ Interrupt capability (up to 14 sources)
▪ Eight-level deep hardware stack
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 PIC- Microcontroller Core Features (2)
▪ Direct, indirect, and relative addressing modes
▪ Power-on Reset (POR)
▪ Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
▪ Watchdog Timer (WDT) with its own on-chip RC oscillator for
reliable operation
▪ Programmable code protection
▪ Power saving SLEEP mode
▪ Selectable oscillator options
▪ Low power, high-speed CMOS FLASH/EEPROM technology
▪ Fully static design
▪ In-Circuit Serial Programming ICSP) via two pins
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 PIC- Microcontroller Core Features (3)
▪ Single 5V In-Circuit Serial Programming capability
▪ In-circuit debugging via two pins
▪ Processor read/write access to program memory
▪ Wide operating voltage range: 2.0V to 5.5V
▪ High Sink/Source Current: 25 mA
▪ Commercial, Industrial, and Extended temperature ranges
▪ Low-power consumption: - < 0.6 mA typical @ 3V, 4 MHz

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 Pin out of PIC16877 Microcontroller

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 Pin out of PIC16877 Microcontroller

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 Pin out of PIC16877 Microcontroller

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 Pin out of PIC16877 Microcontroller

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 Pin out of PIC16877 Microcontroller

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 Pin out of PIC16877 Microcontroller

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 Simplified view of PIC Microcontroller

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PIC16877
Architecture
/Functional
Block
Diagram

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 Pin out of PIC18(L)F2X/4XK22

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PIC18(L)F2X
/4XK22
Architecture
/Functional
Block
Diagram

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 PIC16877 Architecture /Functional Block Diagram
Watchdog Timer (WDT)
▪ The Watchdog Timer is a free running on-chip RC oscillator which does
not require any external components.
▪ This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
▪ That means that the WDT will run, even if the clock on the OSC1/CLKIN
and OSC2/ CLKOUT pins of the device has been stopped, for example, by
execution of a SLEEP instruction.
▪ During normal operation, a WDT time-out generates a device RESET
(Watchdog Timer Reset).
▪ If the device is in SLEEP mode, a WDT time-out causes the device to wake-
up and continue with normal operation (Watchdog Timer Wake-up).
▪ The TO bit in the STATUS register will be cleared upon a Watchdog Timer
time-out.
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PIC16877 Architecture /Functional Block Diagram
Watchdog Timer (WDT) Block Diagram

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 PIC16/18 - Memory Organization (1)
▪ There are three memory blocks in each of the PIC16F87X
MCUs.
1) Program Memory (ROM)
2) Data Memory (RAM)
3) Data EEPROM Memory and Flash Memory
▪ As Harvard architecture devices, the data and program
memories use separate buses;
▪ This allows for concurrent access of the two memory
spaces.
▪ The data EEPROM, for practical purposes, can be regarded
as a peripheral device, since it is addressed and accessed
through a set of control registers.
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 PIC16/18 - Memory Organization (2)
Program Memory (1)
▪ The PIC16F87X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space.

▪ The PIC16F877/876 devices have 8K x 14 words of FLASH

program memory

▪ PIC16F873/874 devices have 4K x 14

▪ The RESET vector is at 0000h and the interrupt vector is

at 0004h.

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 PIC16/18 -
Memory
Organization (3)
Program Memory
(2)

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 PIC16/18 - Memory Organization (4)
Data Memory (1)
▪ The data memory is partitioned into multiple banks which contain
the General Purpose Registers and the Special Function Registers.
▪ Bits RP1 (STATUS) and RP0 (STATUS) are the bank select bits.

▪ Each bank extends up to 7Fh (128 bytes).

▪ The lower locations of each bank are reserved for the Special
Function Registers.
▪ Above the Special Function Registers (SFRs) are General Purpose
Registers (GPRs) , implemented as static RAM.
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 PIC16/18 - Memory Organization (5)
Data Memory (2)
▪ General Purpose Register File can be accessed either directly,
or indirectly through the File Select Register (FSR)
▪ The Special Function Registers are registers used by the CPU
and peripheral modules for controlling the desired operation
of the device.
▪ These registers are implemented as static RAM.
▪ The Special Function Registers can be classified into two sets:
core (CPU) and peripheral.
▪ The STATUS register contains the arithmetic status of the ALU,
the RESET status and the bank select bits for data memory
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 PIC16/18 - Memory Organization (6)
Data Memory (3)
▪ The OPTION_REG Register is a readable and writable register, which
contains various control bits to configure the
✓ TMR0 prescaler/WDT postscaler
✓ External INT Interrupt,
✓ TMR0
✓ weak pull-ups on PORTB
▪ The INTCON Register is a readable and writable register, which
contains various enable and flag bits for
✓ TMR0 register overflow
✓ RB Port change
✓ External RB0/INT pin interrupts
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 PIC16/18 - Memory Organization (7)
Data Memory (4)
▪ The PIE1 register contains the individual enable bits for the
peripheral interrupts
▪ The PIR1 register contains the individual flag bits for the
peripheral interrupts
▪ The PIE2 register contains the individual enable bits for the
✓ CCP2 peripheral interrupt
✓ SSP bus collision interrupt
✓ EEPROM write operation interrupt
▪ The PIR2 register contains the flag bits for the
✓ CCP2 interrupt
✓ SSP bus collision interrupt
✓ EEPROM write operation interrupt
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 PIC16/18 - Memory Organization (8)
Data Memory (5)
▪ The Power Control (PCON) Register contains flag bits to
allow differentiation between a

✓ Power-on Reset (POR)

✓ Brown-out Reset (BOR)

✓ Watchdog Reset (WDT)

✓ External MCLR Reset

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 PIC16/18 - Memory Organization (9)
Data Memory (6)
PCL and PCLATH:

▪ The program counter (PC) is 13-bits wide.

▪ The low byte comes from the PCL register, which is a

readable and writable register.

▪ The upper bits (PC) are not readable but are indirectly
writable through the PCLATH register.

▪ On any RESET, the upper bits of the PC will be cleared

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 PIC16/18 - Memory Organization (10)
Data Memory (7)

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 PIC16/18 - Memory Organization (11)
Data Memory (8)
STACK
▪ The PIC16F87X family has an 8-level deep x 13-bit wide
hardware stack.
▪ The stack space is not part of either program or data space
and the stack pointer is not readable or writable.
▪ The PC is PUSHed onto the stack when a CALL instruction is
executed, or an interrupt causes a branch.
▪ The stack is POPed in the event of a RETURN,RETLW or a
RETFIE instruction execution.
▪ PCLATH is not affected by a PUSH or POP operation.
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 PIC16/18 - Memory Organization (12)
Data Memory (9)
Indirect Addressing, INDF, and FSR Registers
▪ The INDF register is not a physical register.
▪ Addressing the INDF register will cause indirect addressing

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 PIC16/18 - Memory Organization (13)
Data EEPROM and Flash Program Memory (1)
▪ The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range.

▪ These operations take place on a single byte for Data

EEPROM memory and a single word for Program memory.

▪ A write operation causes an erase-then-write operation to

take place on the specified byte or word.

▪ A bulk erase operation may not be issued from user code

(which includes removing code protection).

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 PIC16/18 - Memory Organization (14)
Data EEPROM and Flash Program Memory (2)
▪ Read and write access to both memories takes place
indirectly through a set of Special Function Registers (SFR).
▪ The six SFRs used are:
1) EEDATA (EEPROM Data Register, Low Byte)
2) EEDATH (EEPROM Data Register, High Byte)
3) EEADR (EEPROM Address Register, Low Byte)
4) EEADRH (EEPROM Address, High Byte)
5) EECON1 (EEPROM Control Register1)
6) EECON2 (EEPROM Control Register2)
- Not a physical register
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 PIC18xxx – Timers (1)
Introduction (1)
▪ PIC18 has two to five timers depending on the family member
▪ Referred to as Timers 0, 1, 2, 3 and 4
▪ Used as Timers to generate a Time delay
▪ Used as Counters to count events happening outside the
microcontroller
▪ Every timer needs a clock pulse to tick
▪ The clock source can be internal or external
▪ If the clock source is internal, then 1/4th of the frequency of
the crystal oscillator on the OSC1 and OSC2 pins (Fosc/4) is
fed
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 PIC18xxx – Timers (2)
Introduction (2)
▪ PIC18 timers are 16 bits wide
▪ Because the PIC18 has an 8-bit architecture, each 16-bit
timer is accessed as two separate registers of
1) Low byte (TMRxL)
2) High byte (TMRxH)
▪ For example Timer0 has TMR0H & TMR0L

▪ Each timer also has the TCON (timer control) register for
setting modes of operation
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 PIC18xxx – Timers (3)
Timer0 Module(1)
▪ The Timer0 module incorporates the following features:
✓ Software selectable operation as a timer or counter in
both 8-bit or 16-bit modes
✓ Readable and writable registers
✓ Dedicated 8-bit, software programmable prescaler
✓ Selectable clock source (internal or external)
✓ Edge select for external clock
✓ Interrupt-on-overflow
▪ T0CON Register (Timer0 Control Register)
✓ Controls all aspects of the module’s operation
✓ It is both readable and writable.
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 PIC18xxx – Timers (4)
Timer0 Module(2)
Timer0 Block Diagram (8-bit Mode)

Where, T0CKI-Timer0 clock input

T0SE-Timer0 Source Edge Select bit
T0CS- Timer0 Clock Source Select bit
TOPS<2:0>-Timer0 Prescaler Select bits
PSA- Timer0 Prescaler Assignment bit
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 PIC18xxx – Timers (5)
T0CON (Timer0 Control) Register (1)

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 PIC18xxx – Timers (6)
Timer1/3/5 Module with Gate Control (1)
The Timer1/3/5 module is a 16-bit timer/counter with the
following features:
✓ 16-bit timer/counter register pair (TMRxH: TMRxL)
✓ Programmable internal or external clock source
✓ 2-bit Prescaler
✓ Dedicated Secondary 32 kHz oscillator circuit
✓ Optionally synchronized comparator out
✓ Multiple Timer1/3/5 gate (count enable) sources
✓ Interrupt on overflow
✓ 16-bit Read/Write Operation
✓ Time base for the Capture/Compare function
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 PIC18xxx – Timers (7)
Timer1/3/5 Module with Gate Control (2)
The Timer1/3/5 module is a 16-bit timer/counter with the
following features:
✓ Wake-up on overflow (external clock, Asynchronous
mode only)Prescaler
✓ Special Event Trigger (with CCP/ECCP)
✓ Selectable Gate Source Polarity
✓ Gate Toggle mode
✓ Gate Single-pulse mode
✓ Gate Value Status
✓ Gate Event Interrupt
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 PIC18xxx – Timers (8)
Timer1/3/5 Module with Gate Control (3)
Timer1/3/5 Enable Selections

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 PIC18xxx – Timers (9)
Timer1/3/5 Module with Gate Control (4)
Timer1/3/5 16-bit Read/Write Mode Block Diagram

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 PIC18xxx – Timers (10)
Timer1/3/5 Module with Gate Control (5)
Timer1/3/5 Gate Sources

TxGSS Timer1/3/5 Gate Source

00 Timer1/3/5 Gate Pin 01
Timer2/4/6 Match to PR2/4/6 (TMR2/4/6 increments
01 to match PR2/4/6)
Comparator 1 Output sync_C1OUT (optionally
10 Timer1/3/5 synchronized output) 11
Comparator 2 Output sync_C2OUT (optionally
11 Timer1/3/5 synchronized output)

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 PIC18xxx – Timers (11)
Timer2/4/6 Module (1)
▪ There are three identical 8-bit Timer2-type modules
available.
▪ To maintain pre-existing naming conventions, the Timers
are called Timer2, Timer4 and Timer6 (also Timer2/4/6).
▪ The Timer2/4/6 module incorporates the following
features:
✓ 8-bit Timer and Period Registers (TMRx and PRx,
respectively)
✓ Readable and writable (both registers)

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 PIC18xxx – Timers (12)
Timer2/4/6 Module (2)
▪ The Timer2/4/6 module incorporates the following
features:
✓ Software programmable prescaler
✓ Software programmable postscaler
✓ Interrupt on TMRx match with PRx, respectively
✓ Optional use as the shift clock for the MSSPx modules
(Timer2 only)
✓ MSSP- Master Synchronous Serial Port
1) MSSP1 Module
2) MSSP2 Module
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 PIC18xxx – Timers (13)
Timer2/4/6 Module (3)

Timer2/4/6 Block Diagram

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 PIC18xxx – I/O Ports (1)
Introduction (1)
▪ Depending on the device selected and features enabled,
there are up to five ports available
✓ Port A : RA0 – RA7
✓ Port B: RB0 – RB7
✓ Port C : RC0 – RC7
✓ Port D : RD0 – RD7
✓ Port E : RE0 – RE2
▪ All pins of the I/O ports are multiplexed with one or more
alternate functions from the peripheral features on the
device.
▪ In general, when a peripheral is enabled, that pin may not
be used as a general-purpose I/O pin.
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 PIC18xxx – I/O Ports (2)
Introduction (2)
▪ Each port has five registers for its operation. These registers
are:
✓ TRIS register (data direction register)
✓ PORT register (reads the levels on the pins of the device)
✓ LAT register (output latch)
✓ ANSEL register (analog input control)
✓ SLRCON register (port slew rate control)
▪ The Data Latch (LAT register) is useful for read-modify write
operations on the value that the I/O pins are driving.

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 PIC18xxx – I/O Ports (3)
Generic I/O Port Operation

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 PIC18xxx – I/O Ports (4)
Port A Registers
▪ PORTA is an 8-bit wide, bidirectional port (RA0 – RA7).
▪ The corresponding data direction register is TRISA.
▪ Setting a TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., disable the output driver).
▪ Clearing a TRISA bit (= 0) will make the corresponding PORTA pin
an output (i.e., enable the output driver and put the contents of
the output latch on the selected pin).
▪ Reading the PORTA register reads the status of the pins, whereas
writing to it, will write to the PORT latch.
▪ The Data Latch register (LATA) is also memory mapped.
▪ Read-modify-write operations on the LATA register read and
write the latched output value for PORTA
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 PIC18xxx – I/O Ports (5)
Port B Registers
▪ PORTB is an 8-bit wide, bidirectional port (RB0 – RB7)
▪ The corresponding data direction register is TRISB.
▪ Setting a TRISB bit (= 1) will make the corresponding PORTB pin an
input (i.e., disable the output driver).
▪ Clearing a TRISB bit (= 0) will make the corresponding PORTB pin
an output (i.e., enable the output driver and put the contents of
the output latch on the selected pin).
▪ The Data Latch register (LATB) is also memory mapped.
▪ Read-modify-write operations on the LATB register read and write
the latched output value for PORTB.

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 PIC18xxx – I/O Ports (6)
Port C Registers
▪ PORTC is an 8-bit wide, bidirectional port (RC0 – RC7)
▪ The corresponding data direction register is TRISC.
▪ Setting a TRISC bit (= 1) will make the corresponding PORTC pin an
input (i.e., disable the output driver).
▪ Clearing a TRISC bit (= 0) will make the corresponding PORTC pin
an output (i.e., enable the output driver and put the contents of
the output latch on the selected pin).
▪ The Data Latch register (LATC) is also memory mapped.
▪ Read-modify-write operations on the LATC register read and write
the latched output value for PORTC.
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 PIC18xxx – I/O Ports (7)
Port D Registers
▪ PORTD is an 8-bit wide, bidirectional port (RD0 – RD7)
▪ The corresponding data direction register is TRISD.
▪ Setting a TRISD bit (= 1) will make the corresponding PORTC pin an
input (i.e., disable the output driver).
▪ Clearing a TRISD bit (= 0) will make the corresponding PORTC pin
an output (i.e., enable the output driver and put the contents of
the output latch on the selected pin).
▪ The Data Latch register (LATD) is also memory mapped.
▪ Read-modify-write operations on the LATC register read and write
the latched output value for PORTC.
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 PIC18xxx – I/O Ports (8)
Port E Registers (1)
▪ For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit wide port.
▪ Three pins (RE0/P3A/CCP3/AN5, RE1/P3B/ AN6 and
RE2/CCP5/AN7) are individually configurable as inputs or outputs.
▪ These pins have Schmitt Trigger input buffers. When selected as an
analog input, these pins will read as ‘0’s.
▪ The corresponding data direction register is TRISE.
▪ Setting a TRISE bit (= 1) will make the corresponding PORTE pin an
input (i.e., disable the output driver).
▪ Clearing a TRISE bit (= 0) will make the corresponding PORTE pin
an output (i.e., enable the output driver and put the contents of
the output latch on the selected pin).
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 PIC18xxx – I/O Ports (9)
Port E Registers (2)
▪ TRISE controls the direction of the REx pins, even when they are
being used as analog inputs.

▪ The user must make sure to keep the pins configured as inputs
when using them as analog inputs.

▪ The Data Latch register (LATE) is also memory mapped.

▪ Read-modify-write operations on the LATE register read and write

the latched output value for PORTE.

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 PIC18xxx – Interrupts (1)
Introduction (1)
▪ The PIC18(L)F2X/4XK22 devices have multiple interrupt
sources

▪ An interrupt priority feature that allows most interrupt

sources to be assigned a high or low-priority level

▪ INT0 does not have a priority bit, it is always a high-priority

▪ The high-priority interrupt vector is at 0008h and the low-

priority interrupt vector is at 0018h.

▪ A high-priority interrupt event will interrupt a low-priority

interrupt that may be in progress
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 PIC18xxx – Interrupts (2)
Introduction (2)
▪ There are 19 registers used to control interrupt operation

▪ These registers are:

1) Interrupt Control Registers (INTCON) - 3

2) Peripheral Interrupt Request (PIR) Flag registers - 5

3) Peripheral Interrupt Enable (PIE) registers - 5

4) Peripheral Interrupt Priority Registers (IPR) -5

5) RCON -1

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 PIC18xxx – Interrupts (3)
INCON Registers (1)
▪ The INTCON registers are readable and writable registers

▪ It contains various enable, priority, and flag bits

▪ It has three registers namely

1) INTCON

2) INTCON2

3) INTCON3

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 PIC18xxx – Interrupts (4)
INCON Registers (2)
▪ In general, interrupt sources have three bits to control
their operation. They are:
1) Flag Bit
✓ to indicate that an interrupt event occurred
2) Enable Bit
✓ that allows program execution to branch to the
interrupt vector address when the flag bit is set
3) Priority Bit
✓ to select high-priority or low-priority

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 PIC18xxx – Interrupts (5)
INCON Registers (3)

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 PIC18xxx – Interrupts (6)
INCON Registers (4)

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 PIC18xxx – Interrupts (7)
INCON Registers (5)

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 PIC18xxx – Interrupts (8)
PIR Registers (1)
▪ The PIR (Peripheral Interrupt Request) registers contain the
individual flag bits for the peripheral interrupts.
▪ Due to the number of peripheral interrupt sources, there
are five Peripheral Interrupt Request Flag registers namely
1) PIR1
2) PIR2
3) PIR3
4) PIR4
5) PIR5

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 PIC18xxx – Interrupts (9)
PIE Registers (1)
▪ The PIE (Peripheral Interrupt Enable) registers the
individual enable bits for the peripheral interrupts.
▪ Due to the number of peripheral interrupt sources, there
are five Peripheral Interrupt Enable registers
1) PIE1
2) PIE2
3) PIE3
4) PIE4
5) PIE5
▪ When IPEN = 0, the PEIE/GIEL bit must be set to enable any
of these peripheral interrupts.
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 PIC18xxx – Interrupts (10)
IPR Registers (1)
▪ The IPR(Interrupt Priority Registers) registers contain the
individual priority bits for the peripheral interrupts.
▪ Due to the number of peripheral interrupt sources, there are
five Peripheral Interrupt Priority registers
1) IPR1
2) IPR2
3) IPR3
4) IPR4
5) IPR5
▪ Using the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
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 PIC18xxx – Interrupts (11)
Interrupt Vector Table for PIC18 (1)

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 PIC18xxx – Interrupts (12)
Simplified View of Interrupts (1)

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 PIC18xxx – Interrupts (13)
Hardware Interrupts (1)

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 PIC18xxx – Interrupts (14)
Hardware Interrupts (2)

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 PIC18xxx Instruction Set (1)
▪ RISC (Reduced Instruction Set Computing)

▪ PIC18(L)F2X/4XK22 devices incorporate the standard set

of 75 PIC18 core instructions

▪ Each single-word instruction is a 16-bit word divided

into an opcode

▪ Which specifies the instruction type, and one or more

operands, which further specify the operation of the
instruction.

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 PIC18xxx Instruction Set (1)
▪ The instruction set is highly orthogonal and is
grouped into four basic categories:

✓ Byte-oriented operations

✓ Bit-oriented operations

✓ Literal operations

✓ Control operations

✓ Data Memory-Program Memory or

Table Processing Operations

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 PIC18xxx Instruction Set (1)
Opcode Field Descriptions (1)

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 PIC18xxx Instruction Set (1)
Opcode Field Descriptions (2)

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 PIC18xxx Instruction Set (1)
Opcode Field Descriptions (3)

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 PIC18xxx Instruction Set (1)
Opcode Field Descriptions (4)

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 PIC18xxx Instruction Set (1)
Byte-oriented Instructions (1)
▪ Most byte-oriented instructions have three operands:

1) The file register (specified by ‘f’)

2) The destination of the result (specified by ‘d’)

3) The accessed memory (specified by ‘a’)

▪ The file register designator ‘f’ specifies which file register is

to be used by the instruction.

▪ The destination designator ‘d’ specifies where the result of

the operation is to be placed. I

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 PIC18xxx Instruction Set (1)
Byte-oriented Instructions (2)
Instruction Format

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 PIC18xxx Instruction Set (1)
Byte-oriented Instructions (3)

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 PIC18xxx Instruction Set (1)
Byte-oriented Instructions (4)

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 PIC18xxx Instruction Set (1)
Bit-oriented Instructions (1)
Instruction Format

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 PIC18xxx Instruction Set (1)
Bit-oriented Instructions (2)

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 PIC18xxx Instruction Set (1)
Literal Operations (1)
Instruction Format

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 PIC18xxx Instruction Set (1)
Literal Operations (2)

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 PIC18xxx Instruction Set (1)
Control Operations (1)
Instruction Format

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 PIC18xxx Instruction Set (1)
Control Operations (2)
Instruction Format

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 PIC18xxx Instruction Set (1)
Control Operations (3)

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 PIC18xxx Instruction Set (1)
Control Operations (4)

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 PIC18xxx Instruction Set (1)
Data Memory-Program Memory (or)
Table Processing Operations (1)

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 PIC1687X Instruction Set (1)
▪ RISC (Reduced Instruction Set Computing)
▪ Only 35 single-word instructions
▪ Each PIC16F87X instruction is a 14-bit word, divided into an
OPCODE which specifies the instruction type, and one or more
operands which further specify the operation of the
instruction.
▪ The PIC16F87X instruction set summary has 3 types
1) Byte-oriented Operations (18)
2) Bit-oriented Operations (4)
3) Literal And Control Operations (13)

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 PIC1687X Instruction Set (2)
Opcode Field Descriptions

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 PIC1687X Instruction Set (3)
General Format for Instructions (1)

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 PIC1687X Instruction Set (4)
General Format for Instructions (2)

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 PIC1687X Instruction Set (5)
Byte-Oriented File Register Operations-18

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 PIC1687X Instruction Set (6)
Bit-Oriented File Register Operations-04

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 PIC1687X Instruction Set (7)
Literal and Control Operations - 13

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 References

▪ Muhammad Ali Mazidi & Janice Gilli Mazidi, ‘The PIC

Micro Controller and Embedded Systems’, 2010

▪ PIC18xxx series Datasheet by Microchip Technology

▪ PIC16xxx series Datasheet by Microchip Technology

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