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dlpkrshnaDigital Logic Design CSE-241
INSTITUTE OF BUSINESS ADMINISTRATION, KARACHI
Digital Logic Design (CSE-241)
Laboratory Manual
LAB # 12
Combinational Logic implementation using Decoders
Objective:
To use decoders to implement different combinational logic circuits.
Equipment: Components:
1. One- Single Polarity Variable DC Power 1. One- 3-to-8 Line Decoder, 74LS138
Supply 2. One quad 3-input NAND (Negative
2. Logic Probe OR) gate, 74LS10
3. Switches
4. LEDs
5. One- Bread Board
Note: Do consult the data sheets before connecting you ICs
Theory:
DECODERS:
The basic function of a decoder is to detect the presence of a specified combination of bits (code) on its
inputs and to indicate the presence of that code by a specified output level. Now we know that a two bit
can give us 4 codes. So we can design a 2 input 4-output decoder. In which every output represents the
presence of a particular combination of inputs.
What we originally do is for every combination we use an AND gate so that the output of the AND gate
is only high for the one combination it is designed for.
Faculty of Computer Science Page 1
Instructor: Muhammad Usman Arif
Digital Logic Design CSE-241
Combinational Logic Circuit Implementation using a Decoder :
• Any combinational logic circuit with n inputs and m outputs can be implemented with
an n-to-2n-line decoder and m OR gates.
• Procedure:
– Express the given Boolean function in sum of min-terms. Choose a decoder to
generate all the min-terms of the input variables. Select the inputs to each OR
gate from the decoder outputs according to the list of min-term for each
function.
• Example
– A combinational circuit is defined by F = Σ 0, 2, 5, 6, 7. Hardware implement the
Boolean function F with a suitable decoder and an external OR/NOR gate having
the minimum number of inputs.
• Solution
– The given Boolean function has five three-variable minterms. This implies that
the function can be implemented with a 3-to-8 line decoder and a five-input OR
gate. Also, F will have only three three-variable minterms, which means that F
could also be implemented by considering minterms corresponding to the
complement function and using a three-input NOR gate at the output. The
second option uses a NOR gate with fewer inputs and therefore is used instead
F = Σ 0, 2, 5, 6, 7. Therefore, F’ = Σ 1, 3, 4.
Faculty of Computer Science Page 2
Instructor: Muhammad Usman Arif
Digital Logic Design CSE-241
Task 1:
Construct a circuit using decoders provided to you to implement the following truth table
INPUT OUTPUT
x y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Task 2:
Construct the truth table for the function given below. Also construct the circuit using decoder
provided.
F(A,B,C)=∑(1,3,4,6,7)
Faculty of Computer Science Page 3
Instructor: Muhammad Usman Arif
