M54/74HC373 M54/74HC533

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING

. . . . . . . .

HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS373/533

B1R (Plastic Package)

F1R (Ceramic Package)

M1R (Micro Package)

C1R (Chip Carrier)

ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R

DESCRIPTION The M54/74HC373/533 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS 2 fabricated with in silicon gate C MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. These 8 bit D-Type latches are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level PIN CONNECTION (top view)
HC373 HC533

of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outpts will be in a high impedance state. The application designer has a choise of combination of inverting and non inverting outputs. The three state output configuration and the wide choise of outline make bus organized system simple. All inputs are equipped with protection circuits against discharge and transient excess voltage.

HC373

HC533

October 1993

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INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION (HC373)

PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND FUNCTION 3 State output Enable Input (Active LOW) 3 State outputs

PIN DESCRIPTION (HC533)

PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND FUNCTION 3 State output Enable Input (Active LOW) 3 State outputs

D0 to D7

Data Inputs

D0 to D7

Data Inputs

LE GND V CC

Latch Enable Input Ground (0V) Positive Supply Voltage

LE GND VCC

Latch Enable Input Ground (0V) Positive Supply Voltage

IEC LOGIC SYMBOLS

HC373

HC533

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TRUTH TABLE
INPUTS OE H L L L LE X L H H D X X L H Q (HC373) Z NO CHANGE * L H OUTPUTS Q (HC533) Z NO CHANGE * H L

X: DONT CARE Z: HIGH IMPEDANCE *: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.

LOGIC DIAGRAMS
HC373

HC533

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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 35 70 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW
o o

C C

Absolute Maximum Ratings are those values beyond which damage tothe device may occur. Functional operation under these conditions is not implied. (*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC

RECOMMENDED OPERATING CONDITIONS

Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time M54HC Series M74HC Series VCC = 2 V VCC = 4.5 V VCC = 6 V Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V C o C ns
o

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DC SPECIFICATIONS
Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 V OH High Level Output Voltage 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II IOZ ICC Input Leakage Current 3 State Output Off State Current Quiescent Supply Current 6.0 6.0 VI = IO=-20 A VIH or V IL IO=-6.0 mA IO=-7.8 mA VI = IO= 20 A VIH or V IL IO= 6.0 mA IO= 7.8 mA VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 0.5 4 TA = 25 oC 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 5.0 40 Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 10 80 A A A V V 1.5 3.15 4.2 0.5 1.35 1.8 V V Unit

VIH

High Level Input Voltage Low Level Input Voltage

V IL

VI = VIH or VIL VO = VCC or GND 6.0 VI = VCC or GND

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AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6 ns)

Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CIN COUT CPD (*) Input Capacitance Out put Capacitance Power Dissipation Capacitance 5 10 38 50 50 CL (pF) TA = 25 C 54HC and 74HC Min. Typ. Max. 25 60 7 6 42 14 12 57 19 16 39 RL = 1 K 13 11 54 18 15 30 14 13 15 6 6 16 4 3 12 10 125 25 21 175 35 30 125 25 21 175 35 30 125 25 21 75 15 13 50 10 9 5 5 5 10
o

tTLH tTHL tPLH tPHL

Output Transition Time Propagation Delay Time (LE, D - Q, Q)

Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 75 90 15 13 155 31 26 220 44 37 155 31 26 220 44 37 155 31 26 95 19 16 65 13 11 5 5 5 10 18 15 190 38 32 265 53 45 190 38 32 265 53 45 190 38 32 110 22 19 75 15 13 5 5 5 10

Unit

ns

50

ns

150

ns

tPZL tPZH

3 State Output Enable Time

50

ns

150

RL = 1 K

ns

tPLZ tPHZ tW(H)

3 State Output Disable Time Minimum Pulse Width (LE) Minimum Set-up Time Minimum Hold Time

50

RL = 1 K

ns

ns

ts

50

ns

th

50

ns pF pF pF

(*) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by following equation: CPD (TOTAL) = 22 + 16 x n [pF]

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SWITCHING CHARACTERISTICS TEST WAVEFORM
tPLH, tPHL, (D - Q, Q) tPLH, tPHL (LE - Q, Q), ts, th, tW

tPLZ, tPZL The 1K load resistors should be connected between outputs and VCC line and the 50pF load capacitors should be connected between outputsand GND line. All inputs except OE input should be connected to VCC line or GND line such that outputs will be in low logic level while OE input is held low.

tPHZ, tPZH The 1K load resistors and the 50pF load capacitors should be connected between each output and GND line. All inputs except OE input should be connected to VCC or GND line such that output will be in high logic level while OE input is held low.

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TEST CIRCUIT ICC (Opr.)

INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST.

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Plastic DIP20 (0.25) MECHANICAL DATA

mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.

DIM.

P001J

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Ceramic DIP20 MECHANICAL DATA

mm MIN. A B D E e3 F G I L M N1 P Q 7.9 2.29 0.4 1.27 0.22 0.51 0.5 22.86 2.79 0.55 1.52 0.31 1.27 0.090 0.016 0.050 0.009 0.020 3.3 1.78 0.020 0.900 0.110 0.022 0.060 0.012 0.050 TYP. MAX. 25 7.8 0.130 0.070 MIN. inch TYP. MAX. 0.984 0.307

DIM.

4 (min.), 15 (max.) 8.13 5.71 0.311 0.320 0.225

P057H

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SO20 MECHANICAL DATA

DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012

P013L

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PLCC20 MECHANICAL DATA

mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180

DIM.

P027A

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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A

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