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Unit - III :Circuit characterization and performance
estimation:
Delay estimation, RC delay models, linear delay model, logical effort, parasitic delay, Delay in a logic gate, delay in a multistage logic networks, power dissipation, interconnect, design margin, Reliability, Scaling
Unit IV:Combinational circuit design : Circuit families ,static CMOS, Ratioed circuits, Cascode voltage switch logic, dynamic circuits, pass transistor circuits, differential circuits, sense amplifier circuits, BiCMOS circuits
2 Logic Circuit Types: CMOS Complementary Logic CMOS complementary logic gate has two function determining blocks N-block and p-block. There are normally 2n transistors in an n input gate. 3 2) BiCMOS Logic: Fig.BiCMOS nand gate Transistor N1,N2 supply the pull down NPN transistor with base current when input is high. N3 clamps the pull down when output is high. Transistor P1,PN2 supply the pull up NPN transistor. 4 BiCMOS inverter: 5 Pseudo-NMOS Logic There are n+1 transistor in an n-input pseudo nmos gate. The main problem with the gate is the static power dissipation that occurs whenever the pull down chain is turned on. As the p load is always on, when the n pull down is on current flows in the gate structure. A gate so implemented should have a density advantage over a fully complementary gate. 6 4)Dynamic CMOS logic: It consists of an n transistor logic structure whose output node is precharged to VDD by a ptransistor and conditionally discharged by an n- transistor connected to VSS. Clk is a single phase clock. The precharge phase occurs when clk=0. footed 7 unfooted 8 Problem: Input can only change during the precharge phase and must be stable during evaluate phase of the cycle. If the condition not met, charge redistribution effects can corrupt the output node 9 5) C 2 MOS Logic: 10 Pass Signals Vi 6) Pass transistor logic: A B XNOR Pass function 0 0 1 -A+-B 0 1 0 -A+B 1 0 0 A+-B 1 1 1 A+B XNOR truth table: 11 Operation P1 P2 P3 P4 NOR(A,B) 0 0 0 1 XOR(A,B)
0 1 1 0 NAND(A,B)
0 1 1 1 AND (A,B)
1 0 0 0 OR(A,B)) 1 1 1 0 12 13 7) CMOS domino logic: Limitations:1)each gate must be buffered. 2)Only noninverting structures are possible. 14 CMOS TG Realization of 3-Variable Boolean Function 15 16 Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgans Law 17 Y Y Y D Y (a) (b) (c) (d) Ex:Design a circuit to compute F=AB+CD using NAND and NORs 18