Switching Power Supply Design:

EMI Reduction

AGENDA

Introduction EMI Overview

Noise Sources Identification

Minimize EMI Generation by Layout

Protect Sensitive Circuits From Noise

Conducted EMI and EMI Filters

Summary

2011 National Semiconductor Corporation.

2

AGENDA

Introduction EMI Overview

Noise Sources Identification

Minimize Noise Generation by
Layout
Protect Sensitive Circuits from
Noise

Conducted EMI and EMI Filters

Summary

What is EMI & EMC?

EMI/EMC Standards
EMC Standards vary by
Region
US = FCC
Europe = CISPR = EN

Application usage
Consumer
Medical
Automotive

What standards do we use

FCC part 15 B
CISPR 22 = EN 55022

EMI/EMC Standards Organizations

United States
Electrostatic Discharge Association (ESD)
Federal Communication Commission (FCC)

International

Institute of Electrical and Electronic Engineers (IEEE)

European Committee for Electrotechnical Standardization

Institute of Interconnecting and Packaging Electronic

Circuits (IPC)

(CENELEC)

European Telecommunications Standards (ETSI)

National Institute of Standards and Technology (NIST)

Institute of Electrical and Electronic Engineers (IEEE)

International Society for Measurement and Control (ISA)

International Electrotechnical Commission (IEC)

National Standards System Network (NSSN)

International Organization for Standardization (ISO)

Society of Automotive Engineers (SAE) International

International Special Committee on Radio Interference

Telecommunication Industry Association (TIA)

(CISPR)

International Telecommunication Union (ITU)

Underwriters Laboratories, Inc (UL)
US Standard Developing Organizations (ANSI)
6

Links
EU EMC Directives:
http://ec.europa.eu/enterprise/sectors/electrical/documents/emc/legislation/index_en.htm
EU EMC Standards List (24 Feb 2011):
http://eur-lex.europa.eu/LexUriServ/LexUriServ.do?uri=OJ:C:2011:059:0001:0019:EN:PDF
FCC Rules (Title 47 Telecommunications, Part 2):
http://www.access.gpo.gov/nara/cfr/waisidx_10/47cfr2_10.html
FCC Rules (Title 47 Telecommunications, Part 15) Information Technology Equipment (ITE):
http://www.access.gpo.gov/nara/cfr/waisidx_10/47cfr15_10.html
FCC Rules (Title 47 Telecommunications, Part 18) Industrial, Scientific, & Medical Equipment
(ISM):
http://www.access.gpo.gov/nara/cfr/waisidx_10/47cfr18_10.html
FDA Inspection and Compliance (Medical devices are exempt from FCC regulations):
http://www.fda.gov/ICECI/Inspections/InspectionGuides/ucm090621.htm

Conducted vs. Radiated Emission Limits

Conducted

Radiated

FCC/CISPR Conducted Emission Limits

FCC/CISPR Radiated Emission Limits

Measured at 10m

FCC and CISPR standards the same

FCC and CISPR standards somewhat

different
FCC B (consumer) much more
stringent than FCC A (commercial,
industrial, and business)
8

How Does Noise Show Up in the System?

NOISE SOURCE
Emissions

ENERGY COUPLING MECHANISM

Conducted
Low Frequency

Electric
Fields

Magnetic
Fields

Low, Mid Frequency, LC Resonance

Radiated
High Frequency

SUSCEPTIBLE SYSTEM
Immunity
9

Engineering Approach To Mitigate EMI

NOISE SOURCE

Identify Significant
EMI Sources
Figure Out EMI
Coupling Paths

Unwanted Emissions

Shielding
EMI
Filters
ENERGY
COUPLING MECHANISM
Electric
Fields

Conducted

Engineer Circuit Layout

To Mitigate EMI
Add EMI Filter /
Snubber / Shielding

Magnetic
Fields

EMI
Filters

Radiated

Shielding

SUSCEPTIBLE SYSTEM

10

SMPSs Are Big Generators Of Radiated

And Conducted Emissions

Due to

High power
High di/dt on the switches and diodes
Fast transients (voltage and current)
Not generally enclosed (not shielded)
Parasitic inductance and capacitance in
current paths

Causing

Noise Conducted to
Supply and / or Load
Interfere with circuits in the
same system
Interfere with other
systems
11

Electrically Small Loop Antennas

Electro Magnetic Field Energy is *:

263e

16

f I A
r
2

f: frequency of interest (Hz)

A: loop area of the current path (meters squared)
I : Current magnitude at the frequency of interest (A)
r is measured distance between source and receiver
(meters)
*Henry Otts classic Noise Reduction Techniques in Electronic Systems

12

Theory Behind EMI Mitigation by PCB Layout

Any Current must go from a source of energy and they must RETURN to the
same source
Self Inductance

L AC
Voltage Spike

vL

di
dt

Reduce loop area reduces L

B fields cancel each other if
current return path is close to
current path
13

13

Theory Behind EMI Mitigation by PCB Layout

Which PATH is the current going to
take?

Current Takes the Path of Least

IMPEDANCE, NOT the Path of
Least RESISTANCE!

HF Current Path

Z = R + jX
High freq components contained by
high di/dt current can go through
different path than their low freq
counterpart
Thus, the loop area enclosed by
high freq components can be
completely different

DC Current Path

14

Theory Behind EMI Mitigation by PCB Layout

ElectroMagnetic Field Energy is Proportional To*:

f2: frequency of the harmonic of interest

From switching frequency and di/dt

A: loop area of the current path

If: current magnitude at the frequency of interest
1/r: measured distance r

E f I f A/ r
2

Reduce Noise Generation

Reduce fsw and high freq component in di/dt
Reduce high freq loop area

*Henry Otts classic Noise Reduction Techniques in Electronic Systems

15

EMI Mitigation

Choice of
Switching
Frequency

SpreadSpectrum
Switching

Not just for efficiency/space trade-offs

Beware of EMI keep out zones
- Automotive = 500kHz < AM Band > 2MHz
- ADSL = >1.24MHz to avoid channel interference
- Harmonics
Choose switching frequency that keeps beat
frequency and harmonics out of the EMI range

LM5088 dithers frequency

and shows up to 20dB
decrease in EMI

Fundamental switching frequency spike reduction and

sidebands using spread spectrum switching in the LM5088
16

Steps To Mitigate EMI In PCB

Switching components generate high di/dt
current where is the return path?

Loop Contains high di/dt current is

CRITICAL PATH.

Slow down switching action

Reduce high freq path enclosed area

17

AGENDA

EMI Overview definition and

standards

Noise Sources Identification

Minimize EMI Generation by

Layout

Protect Sensitive Circuits from

Noise

Conducted EMI and EMI Filters

Summary

Isolated and High Power

Density Power Supply Board
18

Identify Critical Path

Buck Converter

Switching Current exist

in the input side

Boost Converter

Buck-Boost
Converter

Critical
path
19

Identify Critical Path

Buck Converter

Boost Converter

Buck-Boost
Converter

Critical
path

20

Identify Critical Path

Non-Inverting
Buck Converter

Boost Converter

Inverting

Critical path

Buck-Boost
Converter

21

What Can We Do In PCB Layout?

--Buck example
Buck Converter

Boost Converter

Buck-Boost
Converter

Minimize critical path area

Separate noisy ground path from quiet ground
22

What Can We Do In PCB Layout?

--Buck-Boost example
Non-Inverting
Buck Converter

Boost Converter

Buck-Boost
Converter

23

AGENDA

Minimize EMI Generation by Layout

24

EMI Mitigation by PCB Layout

Critical Path Area Reduction

Grounding

BUCK Example
High
di/dt
Caps

SW
Node

FETs
&
Driver

Bypass Caps in High di/dt loop should be placed as close as

possible to the switching components
Low side FET SOURCE should be connected as close as
possible to the input capacitor
Apply to critical paths in other SMPS topologies

25

Lower EMI can be achieved by

Place capacitors on
same side of board
as component being
decoupled
Locate as close to
pin as possible
Keep trace
width thick
and
minimized

Connecting to decoupling
capacitors

Connecting to output capacitors

26

Customer Layout
Example

BUCK controller
Input Cap GND
connection

Input Cap GND

Bad Layout
Input
Cap
GND

Good Layout

LS FET
GND

LS FET
GND
LS FET
GND
Input
Cap
GND
27

EMI Mitigation by PCB Layout

Grounding

Critical Path Area Reduction

Buck Regulator Comparison with Cin location (single Cin,

smaller loop area)
High
di/dt
Caps

80
75
70
65

SW
14.5V
max

Cispr 22 Class A 3M

55
50
Level in dBV/m

SW
Node

60

VOUT
47mVpp

Cispr 22 Class B3M

41dBV/
m

45
40
35
30
25
20

FETs
&
Driver

15
10

VOUT

VIN
0
30M

50 60

80 100M

200

300

400 500

800

Frequency in Hz

28

28

1G

EMI Mitigation by PCB Layout

Grounding

Critical Path Area Reduction

Buck Regulator comparison with Cin location (single Cin, 2.5

times larger area)
High
di/dt
Caps

75
70
65

SW
18.1V
max

60

Cispr 22 Class A 3M

55
50
Level indBV/m

SW
Node

80

45
40

44dBV/
m

Cispr 22 Class B3M

35
30

FETs
&
Driver

25

VOUT
75mVpp

20
15
10
5
0
30M

50 60

80 100M

200

300

400 500

800

Frequency in Hz

29

29

1G

EMI Mitigation by PCB Layout

Grounding

Critical Path Area Reduction

High
di/dt
Caps

SW
Node

SW Swings from VIN or VOUT to ground at Fsw. Very

high dv/dt node! Electrostatic radiator
Requires a contradiction:
As large as possible for current handling,
yet as small as possible for electrical noise reasons

Solutions:
Switch node short and wide
Minimum Copper Width Requirement:
Roughly 30mils/Amp for 1 Oz Cu and 60 mils/Amp for Oz Cu, or
2

FETs
&
Driver

T 1.31 5.813 A 1.548 A .052 A

CuWt

Where T = Trace width in mils, A is current in Amps, and CuWt is

copper weight in Ounces. Formula approximates IPC recommendation
for a 10 degree rise for currents from 1A to 20A.
30

EMI Mitigation by PCB Layout

Critical Path Area Reduction

Grounding

Minimize loop area enclosed by high-side FETs, lowside FETs, and bypass caps
Connect the low-side FETs source to the input- cap
ground directly on the same layer, then connect to
the ground plane
Use copper pours for drain and source connections
to power FETs
Minimize stray inductance in the power path
31

EMI Mitigation by PCB Layout

Critical Path Area Reduction

Grounding

Gate drives are also high di/dt paths, lower current

level
Place drivers close to MOSFETs
Keep CBOOT and VDD bypass caps very close to driver
and FETs
Minimize loop area between gate drive and its return
path: from source of FET to bypass cap ground
Minimize stray inductance in the power path
Avoid vias in di/dt path
Short trace and width > 20mil for CBOOT, CVDD-bypass, and Gate
drive

32

EMI Mitigation by PCB Layout

Critical Path Loop Reduction

Grounding

Contradiction
on SW node
transition rate:
Faster Rising and
Falling Times
= Less Losses
=Higher EMI

Resistor Value:
Start with 1-10
ohms and adjust
from there
33

EMI Mitigation by PCB Layout

Critical Path Loop Reduction

Grounding

Ground Plane
Return Current Takes The Least IMPEDANCE Path
Unbroken Ground Plane Provides Shortest Return Path Image current
return path
Trace or Cut on
the ground plane
Current flow in top layer trace

Return current path in

unbroken ground plane
directly under path
Area minimized
B field minimized

Ground
Plane
Ground
Plane

Return current path enclose much larger

area if the direct path is blocked

34

EMI Mitigation by PCB Layout

Grounding

Critical Path Area Reduction

Ground Shielding Example Two Layer Board
80
75

VOUT
30mVpp

70
65
60

Cispr 22 Class A 3M

55
50
Level in dBV/m

SW 15.7V
max

Cispr 22 Class B3M

45

32.5dBV/
m

40
35
30
25
20
15
10
5
0
30M

50

60

80

100M

200

300

400

500

800

1G

Frequency in Hz

35

EMI Mitigation by PCB Layout

Grounding

Critical Path Area Reduction

Ground Shielding Example Four Layer Board w/ Identical Layout /

BOM Two GND Planes in between
80

VOUT
23mVpp

75
70
65
60

Level in dBV/m

SW 13V
max

Cispr 22 Class A 3M

55
50

Cispr 22 Class B3M

45
40
35
30
25
20
15
10
5
0
30M

50

60

80

100M

27.5dBV/
m
200

300

400

500

800

1G

Frequency in Hz

36

EMI Mitigation by PCB Layout

Grounding

Critical Path Area Reduction

Ground Shielding Example Four Layer Board w/ Identical Layout /

BOM w/ CUT under SW node
VOUT
26mVpp

80
75
70
65
60

Level in dBV/m

SW 15.7V
max

Cispr 22 Class A 3M

55
50

Cispr 22 Class B3M

45
40

32.5dBV/
m

35
30
25
20
15
10
5
0
30M

50

60

80

100M

200

300

400

500

800

1G

Frequency in Hz

37

EMI Mitigation by PCB Layout

Critical Path Area Reduction

Grounding

Ground Plane

Unbroken Ground Plane provides shortest return path to

EMI and Best Shielding
Dont cut ground plane
Keep high power, high di/dt current away from ground
plane, run separate paths on the top layer to contain it
Ground plane is for DC distribution and signal reference
only, ideally, there should be no current flow on ground
plane
Bypass to ground PINs, not the plane
38

Switcher Power Modules

(LMZ23610)

15 mm
5.9 mm

Ease of Use

15 mm

Webench, Ease to mount & rework

2.8 mm

Internal Comp

Dual Lead frame

Built in Vin Capacitors to solve EMI issue, &
shielded inductor

10 Amp Current
Sharing Eval board

CISPR 22 Measurements
EMI Configuration
39

Nano Module LMZ10501/0 (1A/650mA)

Extremely Small Solution
Size

LLP-8 Footprint

1.2 mm

2.5 mm

Place on front-side or backside of PCB

3 mm
Mounted on PCB

Expanded View

Excellent Performance
COUT = 10uF

Low output voltage ripple

High efficiency
Fast transient response

Low EMI

Complies with CISPR22

Class B Standard

40

Vout = 1.8V

Innovative Packaging
Key Features:
LLP Footprint
Micro SMD is a standard National package
running in high volume
Moisture sensitivity level 3
Standard soldering process
Reliability testing on complete module
according to NSC standards
RoHS compliance to IPC 1752

1.2 mm
2.5 mm

3 mm

Top View

Side View

Solder Reflow Profile

41

Passing CISPR22 Class B Radiated EMI

The evaluation board with the default components complies with the CISPR 22
Class B radiated emissions standard.

5Vin, 1.8Vout, 1A load

10uF input capacitor
10uF output capacitor
1nF VCON capacitor

42

Nano Module - Cispr 25 Class 5 EMI

(Radiated)

43

43

Passing CISPR 25 Class 5 Radiated EMI

Adding two small 0.1F 0805 input capacitors results in CISPR 25 Class 5 radiated emissions
standard compliance

44

AGENDA

Protect Sensitive Circuits from Noise

45

Protect EMI Sensitive Nodes from Noise

Noisy Nodes: Any
Nodes in High di/dt
Loop

SW node
Inductor
High di/dt
bypass caps
MOSFETs
Power Diodes

Sensitive Nodes: Control

and Sensing Circuits

Vout sensing path and

feedback node
Compensation network
Current sensing path
Frequency setting
Monitoring and Protecting
Circuits

Shielded by Ground / Power Planes

Away from EMI source

46

Good Practice to Protect EMI Sensitive

Nodes
Use Layers four layer board stack-up plan
Top: All high power parts and high di/dt paths, signals that can be routed away
from high di/dt paths
Mid1: Ground Plane
Mid2: Ground Plane / Power Plane / Signal & low power traces
Bottom: low power and signal traces
Flood unused area with copper for improved thermal performance and
shielding

Place and Route

Keep all bypass caps close to pins
The higher the impedance and/or gain, the smaller the node should be,
especially inputs to op-amps: FB pin, comp pin, etc
Low impedance nodes can be wide, such as VIN and VOUT
47

Protect EMI Sensitive Nodes Cont.

Make long runs to low impedance nodes, short runs to high
impedance nodes. Apply to
Place output voltage divider close to the FB node (high impedance), farther from
Vout (low impedance), if have to choose

Route Sense+/Sense- traces parallel to one another minimize

differential-mode noise pickup. Apply to
Current sensing traces
Voltage remote sense lines

Keep sensitive small signal traces thin and further away from
surrounding signals lower capacitance coupling

48

Customer Layout Example

LM20k 5A Buck regulator

SW
FB trace
L

Identified layout problems

1. Vout sensing point is right under

the inductor noise pick up
2. FB trace route very close to SW
node and di/dt loop noise
coupling

Res 49
Divider
49

Customer Layout Example

More problems in this layout

COMP RC

GND
CIN

PGND
pins

3. CIN GND to LS source path (high

di/dt) undefined, through gnd plane
4. AVIN bypass cap gnd return path
very long
5. Comp network close to high di/dt
loop

AVIN
GND
50

Check List
If your board is not working
properly (no schematic
reason) or too much volt
spikes, check

If your board can not pass

Radiated EMI
Check high di/dt loop layout,
especially CIN gnd to LS FET
source connection
Check GND shielding
Suggest Shielded L
Use twisted pair at input / output
(where switching current exists)

High di/dt loop layout

GND shielding
Sensitive nodes layout,
especially FB divider and
routing
Sensitive node grounding
Bypass caps
Add small bypass caps (e.g.
47nF) to Vin and Vout as
close as possible
Add snubber to SW node

Suggest to reduce fsw or switch

transition rate
Consider adding conducted EMI
filter (also alleviate Radiated EMI)

51

AGENDA

Conducted EMI and EMI Filters

52

DM Conducted EMI

Differential Mode Conducted EMI

In DC-DC converter topology, only Hot and Neutral lines, no CM EMI involved
Involves the Normal Operation of the Circuit
Does not involve Parasitics, except input / output CAP ESR and ESL
Only Related to CURRENT, not voltage
For example, with the same power level Buck converter, lower input voltage means higher input
current, thus worse conducted EMI

Why we care?
Excessive Input and/or Output Voltage Ripples can compromise operation of Supply and/or Load
53

DM Conducted EMI Mitigation

EMI filter design
Add filter to prevent noise conducted to Supply or Load
Must be designed so it does not affect SMPS stability
See Application Note for practical EMI filter design (AN-2162)

(Buck)
54

54

Input Filter Design for Conducted EMI

There are two basic requirements for the conducted EMI filter:

Must meet noise attenuation requirement to meet regulations (i.e. CISPR 22)

Must not interfere with the normal operation of the SMPS converter
If filter impedance exceeds the negative impedance of the input supply, it will cause interaction and stability
issues.

Example of a Buck regulator

No input filter

Fails CISPR 22 regulation limits

This regulator needs an

input filter to meet
regulations.
But how do we estimate
how much filter
attenuation to add?

55

Necessary Input Filter Attenuation

Methods of estimating the filter attenuation without LISN and Spectrum Analyzer
Method 1 estimation using oscilloscope measurement
Measure the input ripple voltage using a wide bandwidth scope and calculate the
attenuation.

| Att |dB 20 log(

VinRipple pk pk
1V

) VMAX

VMAX is the allowed dBV noise level for the particular EMI standard.
Method 2 Estimation using the first harmonic of input current
Assume the input current is a square wave (small ripple approximation)

VMAX is the allowed dBV noise level for the particular EMI standard.

CIN is the existing input capacitor of the Buck converter.

D is the duty cycle , I is the output current, Fs is the switching frequency

56

Typical Conducted EMI Filter

Follow the design steps described in AN-2162.

Calculate the required attenuation using Method 1 or Method 2.

Capacitor CIN represents the existing capacitor at the input of the switching converter.

Inductor Lf is usually between 1H and 10H, but can be smaller to reduce losses if this is a high current design.

Calculate capacitor Cf. Use the larger of the two values (Cfa and Cfb) below:

Capacitor Cd and its ESR provides damping so that the Lf Cf filter does not affect the stability of the switching
converter.

57

Conducted EMI Filter Design Tool

Excel based tool is available to help design the
conducted EMI filter.
The tool is based on the steps described in
AN-2162.
The filter design can be printed on one page.

double click to open calculator

Calculator

58

Conducted EMI Before and After Filter

VIN = 30V, VOUT=3.3V,
IOUT = 1.6A, CIN = 10F + 1F,

Results with the following filter:

Fs = 370kHz

Lf = 3.9 H, Cf = 10 F, Cd = 100 F

Results before installing filter:

59

59

AGENDA

EMI Overview definition and standards

Noise Sources Identification

Minimize EMI Generation by Layout

Protect Sensitive Circuits from Noise

Conducted EMI and EMI Filters

Summary
60

SUMMARY
EMI is Electromagnetic Interference. There are many EMC standards,
based on regions and applications
SMPSs are big source of radiated and conducted EMI
EMI comes from high power switching action
EMI problems can be mitigated by identifying high di/dt loop and
reducing loop area by careful board layout
Sensitive circuits should be protected with careful layout and shielding
Filters can be designed to attenuate conducted EMI to protect supply /
Load
Filters also help reduce radiated EMI
61

AGENDA

Questions
62

Isolated and High Power Density

Power Supply Board

Youhao Xi
Phoenix Design Center
April 2011
63

Outline
Identify critical paths in isolated power circuits
Considerations for high power density board layout: copper layer
thickness, trace width, and trace spacing and width
The isolation boundary
PCB Heat-sink
An isolated power supply example
Summary

64

Identify Critical Paths In Isolated

Converters
Flyback
Converter
Forward
Converter
Push-Pull
Converter
Half Bridge
Converter

Critical
paths

Full Bridge
Converter

65

Identify Critical Paths In Isolated

Converters
Flyback
Converter
Forward
Converter
Push-Pull
Converter
Half Bridge
Converter

Critical
paths

Full Bridge
Converter

66

Identify Critical Paths In Isolated

Converters
Flyback
Converter
Forward
Converter
Push-Pull
Converter
Half Bridge
Converter
Full Bridge
Converter

Critical
paths

67

Identify Critical Paths In Isolated

Converters
Flyback
Converter
Forward
Converter
Push-Pull
Converter
Half Bridge
Converter
Critical
paths

Full Bridge
Converter

68

Identify Critical Paths In Isolated

Converters
Flyback
Converter
Forward
Converter
Push-Pull
Converter
Half Bridge
Converter
Critical
paths

Full Bridge
Converter

69

Isolated and High Power Density Board

The good practices and generic rules covered previously all apply to
the isolated power board layout.

There are some additional considerations for isolated and high power
density power boards:
Spacing requirement to sustain the potential difference between adjacent
traces;
PC Board copper layer thickness and trace widths;
PC Board heatsink;
Isolation boundary.

70

High Power Density Board

What does it mean by high power density?
Power density is measured by the ratio of power capacity to the physical
volume of the unit, usually expresses in the unit of W/in3, or W/cm3 .
Regarding PC Board design, power density normally means the ration of
power capacity to the board size, expressed as W/in2, or W/cm2.
High power density implies the board involves high current, and/or high
voltage, traces.
For typical communication applications, on the power board the current can be
>30A, and the voltage can be >150V (mainly switching node voltage).
High current traces requires large copper usage to reduce conduction losses
High voltage traces requires certain minimal spacing between each other.
Components are small, and placed densely.

71

High Power Density Board: Components

Use Small Sized Components, and Place Densely, as long as it does
not violate the minimum spacing defined in the next slide.
To achieve high power density, select small components, place densely. Note that
the ratings must meet the application requirements.
Resistors: voltage and power ratings. For example:
R0201 size: 30V max, 0.05W max @70C
R0402 size: 50V max, 0.063W max @70C
R0603 size: 75V max, 0.10W max @70C
R0805 size: 150V max, 0.125W max @70C
R1206 size: 200V max, 0.250W max @70C
Capacitors: voltage rating; ripple current rating.
Inductor: current rating; power dissipation.
MOSFET: voltage rating; power dissipation.
Diode: voltage rating; power dissipation.
72

A 200W 8th Brick Board

High Power Density Board Trace Spacing

PC Board Trace Spacing Guidelines

IPC-2221: A widely accepted standard in Industry

In power circuit
board that you
commonly see:

There are other

standards which
are applicable case
by case.

For signal traces

For high voltage traces

IPC-2152
IPC-9592
UL-60950
etc.

73

High Power Density Board Copper Layers

PC Board Copper Thickness
Typical power converter PC Board can be done with copper layer
thickness of 1 Oz and 2 Oz.
1 Oz = 0.0014 in, or 35 m.
1 Oz copper layer is normally for signals traces.
2 Oz copper layer is for power circuit traces that conduct high current.
For high power density board dealing with high current, heavy copper --- 3
Oz or thicker copper layers --- can be used.

74

High Power Density Board Trace Width

PC Board Trace Width
It is NOT ALWAYS TRUE that a wider trace is better. It depends on the
function of the trace.
If it conducts power current, a wider traces means lower resistance
and hence lower conduction losses.
If it conducts a low current signal, a wider trace may (or may not)
increase the susceptibility to noise interference via capacitive
coupling.
Switch node pads, though conducting high current, should be kept as
small as possible to minimize the radiated EMI.
For traces conducting small signals, like feedback and control signals,
typically use 0.010~0.015 inch.

75

High Power Density Circuit Trace Width

PC Board Trace Width (ref: IPC-2125)
For trace current >0.25A, refer to the following for minimum width.
Try to make it wider if board room permits.

An example: 10A trace, 10C rise, 2 Oz copper

Figure A indicates to 420 mil2, leading to 160 mil wide trace according to
Figure B. For inner layers, double the width (2x160 = 320 mil).
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PC Board Heatsink
PC Board Heatsink
For surface mount (SMT) power components, like power MOSFETs, power rectifier
diodes, etc, PC Board copper pads can help heatsinking these components in
addition to additional heatsink devices.
Typical PCB heatsink:
Heatsink is realized by enlarging footprint of power component. For instance, the drain pad of a DPAK power
MOSFET.
Heatsink also extends to all other layers through the PC board, connected thermally and electrically with an
array of thermal via holes.

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Isolation Boundary
Isolation boundary
Depending on application, the requirement of isolation strength is different.
For telecom, it is usually 1.5kVac rms, or 2.2kV dc.
For medical, it is 2.5kVac rms up to 5kVac rms.
Some applications may require 10.1kVdc .

Isolation boundary needs to be clear of conductors, or clear of copper traces. The

clearance should confirm the spacing per applicable safety regulations and
standards.
In power supply, there are four types of devices that are usually placed across the
isolation boundary.

Power transformers fulfilling isolated power transfer

Opto-couplers, or solid state isolators
Pulse transformers for isolated gate drive
A common mode capacitor (always reserve a position on PCB, even if not intended to use
initially).

78

An Example
A Flyback Converter: LM5072 POE Eval Board Schematic

79

An Example
Example circuit board

Isolation
boundary

Top Side

Primary

Seondary

Rectifier
Heatsink

MOSFET
Heaksink

80

An Example
Example circuit board

Isolation
boundary

Bottom Side

Primary

Seondary

Rectifier
Heatsink

MOSFET
Heaksink

OptoCoupler

Cross
Boundary
Cap

81

Summary
Switching current paths are critical, and need to follow the rules
previously discussed for high di/dt circuit loops.
Identify the high di/dt circuit loops on both the primary and secondary sides.
Good practices for non-isolated circuit board layout also apply to isolated circuit.

Considerations for high power density circuit boards:

Use components as small as possible;

Follow industry standards for layer thickness, trace width and trace spacing;
Minimize the trace width for low current signal traces.
Enlarge PC board pads of power components to enhance heat-sinking;
Pay attention to isolation boundary. Remember to reserve a position for a common
mode capacitor.

82

Thank You

83

Appendix A) Snubbers
David Baba
Power Design Group

84

Lower EMI can be achieved by

Use snubbers and clamps to minimize both dv/dt and
di/dt of switching waveforms

Typical snubbers in switching power supplies

85

Designing RC Snubbers
RC to damp out ringing
Determine R
Measure the Ring at the switch
node
Determine Cswitch
If it is a Diode Look at Junction
capacitance.
If FET

Csw.EST

Make Rsnub = Rchar

Determine Power Dissp Rsnub

Rsnub .diss

4 Qgs

Vgate
Determine Characteristic Impedance
RChar

1
2 Fring Csw.EST

Csnub Vin Fsw

Guidelines to designing RCD Snubber

SetC snub to 10nF to 100nF
For a set leakage inductance the
Resistor value will determine the
Clamp voltage and the losses in
the snubber circuit.
Typical clamp voltages to be set
at ~2 x VRO.

Vsnub

VRO 2

Select Rsnub based on power

dissipation

Psnub

1
2

Fsw Llk Ipeak

Designing Clamps for Flybacks

Determine reflected voltage to
Primary

Add a transorb whose value is

GREATER than

Use Schottky for clamp

Appendix B) Component Selection

David Baba
Power Design Group

89

Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
Resistors/Capacit
ors

Inductors/Transfor
mers

Power MOSFETs

Rectifier Diodes

Concerns with components dealing with high

di/dt and dv/dt stresses
Cin, Cout, FET decoupling, snubbers, sense resistors

Biggest concern is stray inductance

Surface mount parts have less inductance than through-hole

Use
Low inductance resistors for current sense applications to preserve waveform
shape

Avoid Using
Wirewound Resistors
90

Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
Resistors/Capacit
ors

Inductors/Transfor
mers

Power MOSFETs

Rectifier Diodes

Use shielded inductors for all power inductor paths

If cannot find shielded coupled inductor, specify two shielded inductors

Transformers major problem in EMI

Flyback voltages can be very high

Reflected voltages must be snubbed
Different cores have different leakage flux
Work with a reputable transformer manufacturer such as Pulse or Coilcraft to
ensure quiet transformer design

91

Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
Resistors/Capacit
ors

Inductors/Transfor
mers

Power MOSFETs

Rectifier Diodes

Come in many packages (TO-220, SO-8, DPAK, etc)

Surface mount devices have EMI advantages
Lower lead inductance
Use copper traces to cool part and
reduce EMI
Through-hole cooled via insulator
which creates parasitic capacitance
and radiates during switching cycles
Method to reduce this noise shown
using faraday shield

Drain-heatsink (chassis) capacitance of thruhole components and its neutralization with a

Faraday screen.

92

Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
Resistors/Capacit
ors

Inductors/Transfor
mers

Power MOSFETs

Rectifier Diodes

Used as freewheeling diodes in asynchronous bucks,

secondary side rectifiers for transformer-based
topologies, voltage doublers, valley fill circuits, etc.
Same package concerns as FETs
Budget space for RC snubber across diodes
Several different types

General purpose High reverse voltage but too slow for SMPS
Schottky Low Vf, very fast but limited to <100V apps
Ultra and super fast High Vr, fast recovery, low leakage, but high
Vf
93

Reverse recovery effects EMI

Resistors/Capacit
ors

Inductors/Transfor
mers

Power MOSFETs

Rectifier Diodes

Main trade-off

Faster recovery = higher efficiency but higher EMI

Use Schottky diodes for best performance (low capacitive types like MBR series
even better)

94

Thank You

Questions?

95