Unit - I: Vlsi Fabrication Techniques
Unit - I: Vlsi Fabrication Techniques
Unit - I: Vlsi Fabrication Techniques
VLSI
FABRICATION
TECHNIQUES
EPITAXIAL GROWTH
epi
means upon
teinon means arranged .
arranging atoms in single crystal
fashion upon a single crystal substrate
so resulting layer is an extension of the
substrate crystal structure.
Chemical process-Hydrogen reduction
SYSTEM
OXIDATION
types
Wet Oxidation:
oxidizing atmosphere contains water vapor at
temperatures between 900 to1000Celcius.
Very rapid process. Used for thick field oxides.
Si 2 H 2O SiO2 2 H 2
Dry Oxidation:
oxidizing atmosphere is pure oxygen at
temperatures of 1200C.
Produces better quality oxide than wet oxidation.
Used for thin, highly controlled oxides.
Si O2 SiO2
Patterning - Photolithography
Making
of a
photographic mask
Photo
etching
Making of a photographic
mask
Etching
types
Wet
etching
above process
(chemical regents used in liquid form)
Dry
Mostly used
Smaller line opening
DIFFUSION
Diffusion
of impurities in chip
Ptype doping-boron
Ntype doping-Phosphorous-
ION IMPLATATION
Silicon
PN junction isolation
Economical
Capacitance reduce the performance in high
frequencies
DIELECTRIC ISOLATION
Isolation
ruby
Professional grade ics
Required additional fabrication step
Cost high
METALLIZATION
Interconnection
Aluminum
used
of various components
Scrubbing
and cleaving
Separating individual chips
TO-5
CMOS Fabrication
Process
CMOS can be fabricated using different
processes
N-well process for CMOS fabrication
P-well process
Twin tub-CMOS-fabrication process
Silicon On Insulator (SOI)
N Well process
Step1:
Substrate
Primarily, start the process with a Psubstrate.
Step2: Oxidation
The oxidation process is done by using
high-purity oxygen and hydrogen, which
are exposed in an oxidation furnace
approximately at 1000 degree centigrade.
Step3:
Photoresist
A light-sensitive polymer that softens
wheneverexposed to light is called as
Photoresist layer. It is formed.
Step4:
Masking
The photoresist is exposed to UV rays
through the N-well mask
Step5:
Photoresist removal
A part of the photoresist layer is removed by
treating the wafer with the basic or acidic
solution.
Step6:
Step7:
Removal of photoresist
The entire photoresist layer is stripped off, as
shown in the below figure.
Step8:
Step9:
Removal of SiO2
Using the hydrofluoric acid, the remaining
SiO2 is removed.
Step10:
Deposition of polysilicon
Step11:
Step12:
Oxidation process
Next, an oxidation layer is formed on
this layer with two small regions for the
formation of the gate terminals of NMOS
and PMOS.
Step13:
The
Step14:
Oxide stripping
The remaining oxidation layer is
stripped off.
Step15:
P-diffusion
Similar to the above N-diffusion process,
the P-diffusion regions are diffused to
form the terminals of the PMOS.
Step16:
Step17:
Metallization
Aluminum is sputtered on the whole
wafer.
Step18:
Step19:
Terminals
The terminals of the PMOS and NMOS
are made from respective gaps.
Step20:
P well
P-well
process is almost similar to the Nwell. But the only difference in p-well
process is that it consists of a main Nsubstrate and, thus, P-wells itself acts as
substrate for the N-devices.
Twin tub-CMOS
Fabrication Process
n this process, separate optimization of the n-type and ptype transistors will be provided. The independent
optimization of Vt, body effect and gain of the P-devices, Ndevices can be made possible with this process.
Formation
of the tub
Thin oxide construction
Implantation of the source and drain
Cuts for making contacts
Metallization
steps
Transistors
all sides.
The blow figure shows a typical
NMOS Transistor with Bulk CMOS
Process and with SOI Process.
The
Isotropic
etching is used
Etching types
Isotropic etch
Fully anisotropic
etch
Prefential etch
SOI process
Advantages :
20% to 50% increase in switching speed compared to
similar circuits built on conventional "bulk" silicon
wafers
the ability to operate at lower voltages (less battery
power drain and chip heating)
events from cosmic ray particle showers (reducing the
need for error correction operations in high-speed data
flow servers and memory arrays)
increased circuit packing due to simplification of the
lateral and vertical isolation structures, increasing chip
yield and die count per wafer
Disadvantage
Most expensive
CMOS Process
Enhancement
To
increase routability
To provide high quality capacitors for analog
circuits and memory
To provide resistors of variable characteristics
process include
Double
Interconnects
connections between transistors are primarily
The
fabrication
Resistors in CMOS
Technology
The
Capacitors
Capacitors in CMOS technology include poly-poly,
metal-poly, silicon-silicon and vertical and lateral
metal-metal.
analog functions have two layers of poly silicon.
second layer an extra layer of inter connect, and
also to implement floating gate memory cells that
are electrically programmable and optically erasable
with UV light.
An important aspect of the capacitor structure is the
parasitic capacitance associated with each plate.
This bottom plate parasitic capacitance is typically
ten to 30 % of the capacitor itself.
Latch-up
Parasitic
controlling latch up
bipolar
Bipolar
decoupling
highly doped substrate beneath a lightly doped
epi-layer very effectively shunts the lateral
parasitic bipolar. Reverse bias on the substrate
(or well) raises the bypass current needed to
turn on corresponding bipolar.