8.delapan (Counter Dan FSM)
8.delapan (Counter Dan FSM)
8.delapan (Counter Dan FSM)
KOM 15201
Slide 3
end if;
end process;
Agenda
Introduction
Review Sistem Digital
FPGA design dengan Xilinx
Rangkaian kombinasional
Rangkaian Enkoder, Decoder, Multiplekser dll
Konsep-konsep tambahan dalam pemrograman
Flip flop
-----------------------------------UTS-------------------------------------
Rangkaian Counter & Finite State Machine (FSM)
Materi pengayaan
Desain project dan presentasi
-----------------------------------UAS-------------------------------------
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2 December 2017
Sequential Logic Design in VHDL
The design of sequential circuits in VHDL requires the use of the process
statement.
Sequential Circuit:
Regular sequential circuit.
The state transitions in the circuit exhibit a regular pattern, as in a counter
or shift register. The next-state logic is constructed primarily by a
predesigned, regular component, such as an incrementor or shifter.
FSM.
The state transitions in the circuit do not exhibit a simple, repetitive pattern.
The next-state logic is constructed by random logic and synthesized from
scratch. It should be called a random sequential circuit, but is commonly
known as an FSM (finite state machine).
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2 December 2017
Coding style
Slide 6
2 December 2017
Basic block of VHDL sequential programming
Entity
Slide 7
Ketiga blok adalah concurrent, sehingga tidak harus urut
Ketiganya berjalan secara parallel karena concurrent
2 December 2017
4 bit counter up/down
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
Slide 8
q<=STD_LOGIC_VECTOR (r_reg);
end Behavioral;
8 bit counter up/down
Slide 9
2 December 2017
Shift register left/right
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2 December 2017
FSM
An FSM (finite state machine) is used to model a system that transits
among a finite number of internal states.
The transitions depend on the current state and external input.
Unlike a regular sequential circuit, the state transitions of an FSM do not
exhibit a simple, repetitive pattern.
This is different from the next-state logic of a regular sequential circuit,
which is composed mostly of structured components, such as
incrementors and shifters.
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2 December 2017
The basic block diagram of an FSM is the same as that of a regular sequential circuit.
It consists of a state register, next-state logic, and output logic.
An FSM is known as a Moore machine if the output is only a function of state, and is
known as a Mealy machine if the output is a function of state and external input.
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2 December 2017
FSM example
Slide 13
declaration
State declaration in architecture
Contoh:
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2 December 2017
Contoh-contoh FSM
Answering machine
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2 December 2017
Contoh-contoh FSM
Soda machine
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2 December 2017
Contoh-contoh FSM Lift manual 2 lantai
State 1 State 2
lt0 lt1
Slide 17
2 December 2017
library IEEE;
--next state logic
use IEEE.STD_LOGIC_1164.ALL;
Next_state_proc: process(state_reg,up,down,sensor_lt1,sensor_lt0)
begin
entity fsmlift is
case state_reg is
Port ( clock : in STD_LOGIC;
when lt0 =>
up : in STD_LOGIC;
if up='1' and down='0' then if sensor_lt1='1' then
reset : in STD_LOGIC;
state_next<=lt1;
down : in STD_LOGIC;
end if;
sensor_lt0 : in STD_LOGIC;
end if;
sensor_lt1 : in STD_LOGIC;
when lt1 =>
motor_up : out STD_LOGIC;
if up='0' and down='1' then if sensor_lt0='1' then
motor_down : out STD_LOGIC);
state_next<=lt0;
end fsmlift;
end if;
end if;
architecture Behavioral of fsmlift is
end case;
type state_type is (lt0,lt1);
end process;
signal state_reg: state_type;
- combinational logic and output (MEALY)
signal state_next: state_type;
output_proc: process(state_reg,up,down)
begin
begin
--clocked process
case state_reg is
state_proc: process(clock,reset)
when lt0 =>
begin
if up='1' and down='0' then
if reset='1' then
motor_up<='1';
state_reg<=lt0;
motor_down<='0';
elsif clock'event and clock='1' then
else
state_reg<=state_next;
motor_up<='0';
end if;
motor_down<='0';
end process;
end if;
when lt1 =>
if up='0' and down='1' then
motor_up<='0';
motor_down<='1';
Slide 18
else
motor_up<='0';
motor_down<='0';
end if;
end case;
end process;
end Behavioral;
TUGAS (kel. besar)
Buatlah FSM menggunakan pemrograman VHDL untuk sistem berikut:
- Memiliki 2 input berupa push button (PB1 dan PB2) dg alamat site: V4 dan K17
- Memiliki 4 output berupa LED dg alamat site:
- Jika PB2 ditekan, maka state akan direset ke state default, yakni semua LED mati
(0000)
- Buat program VHDLnya, konfigurasi planahead sekaligus file *.bit-nya untuk
Slide 19
selanjutnya di download ke board xilinx minggu depan di kelas!
2 December 2017
W-4
Slide 20
2 December 2017