Module2 - Capacitor and Resistor Model

MOS Capacitors
Reference:
Rabaey
Outline
 MOS Capacitance Models
Shiv
Nadar
University
The Big Picture
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
 Depends on terminal voltages
 Current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
 I = C (DV/Dt)  Dt = (C/I) DV
 Capacitance and current determine speed
MOS CAPACITANCE
• The current-voltage characteristics investigated here can be
applied for investigating the DC response of MOS circuits
under various operating conditions.
• In order to examine the transient response of MOSFETs and

digital circuits consisting of MOSFETs, on the other hand, we
have to determine the nature and the amount of parasitic
capacitances associated with the MOS transistor.
• In the following, we will develop simple approximations for

the on-chip MOSFET capacitances that can be used
in most hand calculations.
Capacitances of a MOS Transistor
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
 Creates channel charge necessary for operation
(intrinsic capacitance)
 Source and drain have capacitance to body
(parasitic capacitance)
 Across reverse-biased diodes
 Called diffusion capacitance
Top View of MOSFET
• In this figure, the mask length (drawn
length) of the gate is indicated by Ld, and
the actual channel length is indicated by L.
• The extent of both the gate-source and

the gate-drain overlap are xd; thus, the
channel length is given by
L = Ld – 2xd
• Based on their physical origins, device
capacitances can be classified into two major
groups:
 Oxide-related capacitances
--- Overlap Capacitance
--- Gate to Channel Capacitance
 junction capacitances
Overlap Capacitance
• It was shown earlier that the gate electrode overlaps both the
source and drain region at the edges. The two overlap
capacitances that arise as a result of this structural
arrangement are called CGS0 (overlap) and CGD0 (overlap),
respectively.
• Assuming that both the source and the drain diffusion regions
have the same width W, the overlap capacitances can be
found as
Since xd is a technology-determined parameter, it is customary to

combine it with the oxide capacitance to yield the overlap
capacitance per unit transistor width
Note that both of these overlap capacitances do not depend
on the bias conditions, i.e., they are voltage-independent.
Gate to Channel Capacitance
• Since the channel region is connected to the source, the drain, and the
substrate, we can identify three capacitances between the gate and
these regions, i.e.,Cgs, Cgd and Cgb respectively.
In Cut-off mode:
surface is not inverted. Consequently, there is no conducting
channel that links the surface to the source and to the drain.
Therefore, the gate-to-source and the gate-to-drain capacitances
are both equal to zero:
Linear Mode
Channel extends across the MOSFET, between the source

and the drain.
This conducting inversion layer on the surface effectively

shields the substrate from the gate electric field; thus:
Cgb = 0
• the distributed gate-to-channel capacitance as seen
between the gate and the source is approximated
by:
Saturation Mode
When the MOSFET is operating in
saturation mode, the inversion layer on the
surface does not extend to the drain,
Cgd = 0
Since the source is still linked

to the conducting channel, its shielding
effect also forces the gate-to-substrate
capacitance to be zero.
• Finally, the distributed gate-to-channel
capacitance as seen between the gate
and the source can be approximated
by
Total Capacitance
Diffusion Capacitance
 Csb, Cdb
 Undesired capacitance (parasitic)
 Due to the reverse biased p-n
junctions between source diffusion
and body and drain diffusion and body
 Capacitance depends on area and
perimeter
Diffusion Capacitance
• Bottom-plate junction,
with Cj the junction capacitance per unit area
• Side-wall junction
𝑪
𝒔𝒘 =𝑪 𝒋𝒔𝒘 (𝐖 +𝟐 𝑳 𝒔 )
where Cjsw is a capacitance per unit length.

Where VD is the applied reverse bias voltage
Lumped representation of the MOSFET
capacitances
DESIGN DATA of the MOSFET capacitances
Example
MOS Equivalent resistor
Reference
1. Baker
Review: MOSFET CAPACITANCE
• Effective switching resistance of MOSFET
Point A in Fig. shows the operating point of the MOSFET prior to switching for
VDD = 5 V. After switching takes place, the operating point moves to point B
and follows the curve Vgs = VDD down to ID = 0 and VDS = 0, point C.
• For an NMOS device with a specific width, W, or length,
L, we can estimate the effective switching resistance of
the device in the long-channel CMOS process (scale
factor of 1 µm) as
For the PMOS device, the transconductance

parameter, KPp, is three times smaller than the
NMOS's KPn so we can write
LONG-CHANNEL PROCESS
• The effective resistance of the PMOS device is
three times as large as the NMOS's due to the
mobility of the electrons being larger than the
mobility of the holes.
• Assignment P1: Estimate the switching

resistance of NMOS and PMOS at 180 nm node.
Express the resistance in terms of scale factor.
Scale Factor
• we do layout to a generic scale factor. If, for example, the
minimum device dimensions are 50 nm (= 0.05 µm =50 x 10-
9m), then an n-well box drawn 10 by 10, see Fig, has an actual
size after it is fabricated of 10* 50 nm or half a micron (0.5 um

= 500 nm),
• Short-Channel MOSFET Effective Switching Resistance
• scale factor of 50 nm and a VDD of 1 V.
Knowing, for the short-channel process, that the scale
factor is 50 nm, we can rewrite Eqs.
where W is the drawn width of the devices. Practically, to model the effects of
increasing switching resistance when L is greater than 1 (minimum), we can re-write Eq
SHORT-CHANNEL PROCESS

Module2 - Capacitor and Resistor Model

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Module2 - Capacitor and Resistor Model

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MOS Capacitors

• In order to examine the transient response of MOSFETs and

• In the following, we will develop simple approximations for

• The extent of both the gate-source and

Since xd is a technology-determined parameter, it is customary to

Channel extends across the MOSFET, between the source

This conducting inversion layer on the surface effectively

Since the source is still linked

with Cj the junction capacitance per unit area

where Cjsw is a capacitance per unit length.

For the PMOS device, the transconductance

• Assignment P1: Estimate the switching

size after it is fabricated of 10* 50 nm or half a micron (0.5 um

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