Contents

Characteristics of Digital IC’s :-

Voltage and Current Parameters
Fan-out
Noise Margin
Propagation Delay (Speed of Operation)
Power Dissipation
Operating Temperature
 Characteristics of Digital IC’s
Voltage and Current Parameters
Voltage parameters (Threshold Levels)
Ideally the input voltage levels of 0V & + 5V (for TTL) are called as logic 0 & 1 levels.
But practically it’s not always possible to obtain voltage levels exactly as the these values. Hence
there’s the necessity to define the worst case input voltages.

Input voltage

VCC (supply)
Logic 1 VIH (min)
Undefined VIL (max)
Logic0
0 t
(a) Input voltage parameters
(I) VIL (max) - Worst case low level input voltage :
This is the maximum value of input voltage which will be considered as a logic 0 level. If
the input voltage is higher than VIL (max), then it won’t be treated as a low (0) input level.

(II) VIH (MIN) - Worst case high level input voltage :

This is the minimum value of the input voltage which will be considered as a logic 1 level.
If the input voltage is lower than VIH (min), then it will not be treated as a high (1) input.
 Output voltage

VCC (supply)
Logic 1
VOH (min)
Undefined
Logic 0 V OL(max)
0 t
(b) Output voltage parameters
(III) VOH (max) - Worst case high level output voltage :
This is the minimum value of the output which will be considered as a logic HIGH(1)
level. If the output voltage is lower than this level then it won’t be treated as a HIGH(1)
output.
(IV) VOL (max) - Worst case low level output voltage :
This is the maximum value of the output voltage which will be considered as a logic
LOW(0) level. If the output voltage is higher than this value then it won’t be treated as a
LOW(0) output. HIGH 1 LOW
HIGH LOW
LOW HIGH +
+
+ +
LOW HIGH VOL
VOH _VIH _ _VIL
_

Voltage parameters on a logic circuit

 Current parameters :
(a) IIL - Low level input current
It is the current that flows into the input when a low level input voltage in the specified
range is applied.
(b) IIH - High level input current :
It is the current that flows into the input when a high level voltage input voltage in the
specified range is applied.
(c) IOL - Low level output current:
This is the current that flows from the output when the output voltage is in the
specified
low(0) voltage range and a specified load is applied.
(d) IOH - High level output current :
This the current flowing from the output when the output voltage is in the specified
HIGH(1) voltage range and a specified load is applied.
If the output current floes into the output terminal then it is called as a sinking current
and if the output current flows away from the output terminal then it is called as a
sourcing current. +5 V
LOW IOH IIH HIGH IOL IIL

HIGH HIGH HIGH LOW LOW

LOW

Current Parameters
 Fan – out:
Fan-out is defined as the maximum number of inputs of the same IC
family that a gate can drive without falling outside the specified output
voltage limits. Higher the fan out higher the current supplying capacity of
gate.

N number of load gates

Driver gate

Fan - out

For example, the fan – out of the driving gate which is driving N number of
gates is N. Fan – out is also called as the loading factor. If the specified fan –
out of a gate is 10 then we should not load it more than 10 gates. Fan – out
depends on the nature of input devices that are connected to an output.
 Noise Margin :
Noise Immunity is defined as the ability of a logic circuit to tolerate the
noise without causing any unwanted changes in the outputs.
A quantitative measure of noise immunity is called as noise margin.

Voltage
VOH (min) Valid logic “1”
Valid logic
l “1”
VNH

VIH (min) Invalid

Invalid
VIL (max)
VNL
Valid logic “0”
“ VOL (max) Valid logic “0”
(a) Input profile (b) Output profile

The difference between VOH (min) and VIH (min) is known as the high level noise
margin VNH. Similarly the difference between VIL (max) and VOL (max) is called
as the low level noise margin VNL.

High level noise margin, VNH = VOH (min) - VIH (min)

Low level noise margin, VNL = VIL (max) - VOL (max)
 Propagation Delay : (Speed of Operation):
Propagation delay is defined as time delay between the instant of application
of an input pulse and the instant of occurrence of the corresponding output
pulse.
Input Output +Vcc
Output
Input
H H
L 50% 50%
Input
Input
H H
Output
50% 50%
Output L
tPHL tPLH tPLH tPHL

From the above figure the two propagation delays observed are:
1. tPHL : The propagation delay measured when the output is making a transition
from HIGH(1) to LOW(0) state.
2. tPLH : The propagation delay measured when the output makes a transition
from LOW(0) to HIGH(1) state.
Power Dissipation :
There should be reduction in the power dissipation taking place in the logic IC in order to
protect the IC against damage due to excessive temperature, to reduce the loading on
power supplies.
Another importance of power dissipation is that the product of power dissipation &
propagation time is always constant. Therefore reduced power dissipation may lead to
increase in propagation delay.
We have, P = VCC X ICC where ICC = current drawn from power supply.

+VCC +VCC
ICCH ICCH = current ICCL
0 drawn with all its 1
0 1 1 0
outputs high.
0 1 1 0
1 1
1 ICCL = current 1
0 1 drawn with all 1 0
outputs “0”,
0 1 1 0
0 1
Power dissipation

The values of ICCH & ICCL are measured with open circuited outputs (no load),
because the load will change with these values. ICCH & ICCL are of different values.
Hence, ICC (avg) = (ICCH + ICCL) / 2
PD (av) = VCC x ICC (avg)
Operating Temperature
The temperature range acceptable for the consumer and industrial applications is
o o o o
0 to 70 C and that for the military applications is -55 C to 125 C.

The performance of gates will be in the specified limits over these temperature
ranges.
 Topics
 2 INPUT TTL NAND GATE

 TOTEM POLE OUTPUT STAGE

 UNCONNECTED INPUTS

 OPEN COLLECTOR OUTPUTS

 WIRED ANDING
 Multiple Emitter Transistor

 The multiple emitter transistor can have upto 8 emitters for an 8

input NAND Gate.
 D1,D2BE Junctions
 D3CB Junction.
 The transistor can be turned ON by forward biasing either D1 or
D2(or both).
 The transistor will be OFF if and only if both the BE junctions are
reverse biased.
 Two Input TTL NAND Gate

 A and B are input terminals.

 They can either be Low(0 Volts

ideally) or High(+Vcc ideally).

 Operation:-
 Case 1 :- A and B both LOW
 Case 2 :- Either A or B LOW
 Case 3 :- A and B both HIGH
 Case 1- A and B both Low
 Both BE Junctions of transistor Q1 are
forward biased.

 D1 And D2 will conduct

 Voltage at C is forced to 0.7V

 Q2 is OFF.Collector Voltage Vx Rises

to +Vcc.

 Q3 is in Emitter follower mode.

 Y=1 (HIGH)
 Case 2 – Either A or B LOW

 One input is grounded and the other is

left open or connected to Vcc.

 Voltage at C is forced to 0.7V

 Q2 is OFF.Collector Voltage Vx Rises

to +Vcc.

 Q3 is in Emitter follower mode.

 Y=1 (HIGH)
 Case 3- A and B both HIGH
 Both inputs A and B are
connected to +Vcc
 D1 and D2 are reverse biased.
 D3 is forward biased.

 Base current is supplied to

transistor Q2 via R1 and D3
 Q3 is OFF as voltage as X
drops down.

 Q4 is turned ON as voltage at
Z increases.

 As Q4 goes into saturation,

Y=0 (LOW)
 Totem Pole Output Stage

 The arrangement of Q3 and Q4 on

the Output side of TTL NAND
Gate.

 With Q3 in the circuit , current

flowing through R3 will be zero
when output Y=0,and Q4will
become ON, which reduces the
power dissipation.
 Advantages

 Q3 is ON and acting in the

Emitter follower mode. It will
therefore have a very low
output impedance.

 Therefore the output time

constant will be very short for
charging up any capacitive
load on the output.
 Unconnected Inputs

 If any input of TTL NAND Gate is left open, disconnected or floating,it

acts as if logic 1 is applied to it.
 Therefore,the corresponding BE junction of the input transistor is not
forward biased.
 Open Collector Circuit

 It is the same 2 Input TTL

NAND Gate but with R3
and Q3 removed.

 The collector point of Q4 is

brought out as output.

 External resistance R3 is
connected for proper
operation.It is known as
pull up resistance.
 Operation

 Case 1- A=B=0 Y=1

 Case 2- Either A=1,B=0

or A=0,B=1 Y=1

 Case 3- A=B=1 Y=0

 Wire ANDing

 Wire ANDing means tying the outputs

of gates together to obtain AND
function.

 Q4A & Q4B represent the output of the

transistors. A common output up
resistance is used for output of
transistors. Also the transistors Q4A and
Q4B are operated as switches.
1. MOS LOGIC FAMILY
2. MOSFET AS A SWITCH
3. N-MOS INVERTER
4. P-MOS INVERTER
5. CMOS-LOGIC
6. CMOS NAND GATE
7. CMOS CHARACTERISTICS
 MOS LOGIC FAMILY
MOSFET

Depletion Mosfet Enhancement type mosfet

or E-Mosfet

P channel Mosfet N channel Mosfet

(PMOS) (NMOS)

Gate is the Control Terminal

 MOS
TECHNOLOGY

PMOS NMOS CMOS

(Uses P Channel E-MOSFETs) (N channel E-MOSFETs) (Uses PMOS & NMOS)

ADVANTAGES OF MOSFETs:
 Easy & Inexpensive
 Small Size
 Consumes Little Power

DISADVANTAGES OF MOSFETs:
 due to accumulation of Static Charges MOSFETs can get damage
 using the proper handling procedures, it possible to minimize the possibility of damage
 MOSFET AS A SWITCH
Biasing : N-Channel MOSFET

 Drain to source voltage – Positive

 VGS Control Resistance
 VGS decide ON or OFF
MOSFET OFF

If VGS =0 ,MOSFET Turns OFF

drain current=0

MOSFET ON
If VGS > VT , MOSFET Turns ON
 N-MOS INVERTER
INVERTER with A PASSIVE LOAD

Resistor used as passive load .

OPERATION

 Vin < VT ,Mosfet Will be OFF ,output=+vDD

 Vin > VT , Mosfet Will be Fully On, output=0

 PMOS INVERTER
Schematic Diagram :-

OPERATION :-

 Vin =0 ,Y Output is High (-VDD)

 Vin= -5 V (logic 1) ,Output is Low(0).

SUMMARY INPUT Vin Q2 OUTPUT Y

0 Volts(0) OFF -VDD (1)

-VDD (1) ON 0 (Logic0)

 CMOS LOGIC
1. Use P & N channel mosfets connected in SERIES.
2. Drains Connected Together .
3. Input applied at common gate.

ADVANTAGES OF CMOS LOGIC:-

1. Faster
2. Less Power Comsumption

CMOS IS USED AS :-

1. CMOS NAND GATE

2. CMOS NOR GATE
 CMOS NAND GATE
Schematic Diagram

1.Q1 & Q2 are P – channel Mosfet.

2.Q3 & Q4 are N -channel Mosfet.

3.A controls status of MOSFETs Q1 & Q3.

4.B controls status of MOSFETs Q2 & Q4.

 OPERATION
1. When A=B=0

1. Q1 & Q2 Will be ON
2. Q3 & Q4 Will be OFF
3. Y=+VDD
 2. When A=0,B=1

1.Q1 is ON , Q3 is OFF
2. Q2 is OFF , Q4 Will Be ON

3.Output=+VDD
 3. When A=1 , B=0

1.Q1 is OFF , Q3 is ON.

2.Q2 is ON , Q4 is OFF.

3.Output Y = +VDD
 4. With A=1 , B=1

1. Q1 & Q2 Both are OFF

2. Q3 & Q4 both are ON
3. Output Y =0 (LOW)
 CMOS characteristics:
 Power supply voltage:
a) The 4000/14000 and 74c series operate over wide range of power supply
voltage(3v to15v)
b) The other cmos families such as 74HC/HCT,74 AC/ACT,74AHC/AHCT
operate over voltage range of 2 to 6

 Power dissipation:
a) power dissipation of cmos devices is very low when they are in static state
b) Power dissipation is low under dc operating condition and at low
frequencies but power dissipation increases as frequency increases

Frequency 0(dc) 100KHZ 1MHZ

Power 10nW 0.1mW mW
dissipation
 Switching speed:
a) It can be faster than the NMOS or PMOS device
b) Switching speed for various CMOS ics
Family 4000 74HC/HC 74AC/AC 74AHC
T T
Propagation 50ns 8ns 4.7ns 4.3ns
Delay

 Static sensitivity:
a)The MOS ICS are susceptible to damage due to static
electricity. such static electricity get generated due to
simple day to day action
b) Such damage is called electrostatic discharge(ESD)and
we have to use resister diode network for protection
 FAN OUT:
a)The input resistance of cmos device is very high
So their input current is very small almost zero. so
cmos gate can drive a large no of other cmos gates
Hence fan out of cmos device will be large as
compare to fan out of TTL

b)Typically the fan out is restricted to 50 for operation below

1 MHZ.
Topics:-

1.Tristate Logic o/p

2. Interfacing -
a.TTL driving CMOS
b.CMOS driving TTL
3.Comparison of CMOS & TTL
 Tristate Logic Output

Fig:-A Tristate CMOS inverter

When both MOSFETs are in the OFF state, the output is

in its high impedance state.

When E=1, the inverter operates in a normal way.So here

either Q1 or Q2 is ON depending on i/p A.

But when E=0, both Q1 & Q2 are OFF irrespective of i/p
A.
Advantages Of CMOS :-
1. Low power dissipation.
2. High fan out.
3. Capable of working over a wide range of supply
voltage.
4. High packaging density since MOS devices need
less space.
Disadvantages Of CMOS :-
1. Propagation delays longer than TTL.
2. Slower than TTL.
3. Due to static charge it may damage.
4. Need Protection circuitry.
 INTERFACING
 It means connecting the o/p of one sys. to the i/p of
another sys. with different char.
 Direct connections cannot be formed when electrical
char. of two ckt are diff.
 So “interface” circuit is inserted betn the “driver” &
“load” ckt.
 The task of interface ckt. Is to accept the o/p of the
driver ckt. & “condition” it so that it is compatible with
the load ckt.
Driver Load
Interface System
System
 TTL Driving CMOS
 The o/p current capability of TTL ICs is much
higher than the I/p current values of CMOS ICs.
So there is no problem for TTL to drive CMOS as
far as current is concerned.
 But there is problem when compare vtg. levels
TTL & CMOS bcoz VOH(min) of TTL series is very
low as compared with VIH(min) reqd for CMOS
series like 400B, 74HC etc.
 So as to raises the o/p level of TTL gate to about
+5V in the HIGH state an external pull up resistor
is introduced as shown in fig.
 Fig. TTL Driving CMOS

 Introducing external pull up resistor will provide

the sufficient vtg. Level at the i/p of the CMOS
gate.
 TTL can also drive high vtg. CMOS.
 CMOS Driving TTL

 Equivalent ckt. in HIGH state.

 Equivalent ckt. In LOW state.
 Sr Para. For driving Para. For the
No gate (CMOS) of load gate
. 4000 B series (TTL) of 74
series
1. VOH(min)=4.95 V VIH(min)=2 V

2. VOL(max)=0.05 V VIL(max)=0.8V

3. IOH(max)=0.4 mA IIH(max)=40µA

For 4. IOL(max)=0.4 mA IIL(max)=1.6mA For

low high
state state
o/p o/p
 CMOS Driving TTL in HIGH state
 Here the CMOS o/p vtg. is high (1) . From table…
 From these we come to know that the CMOS o/p can supply
sufficient vtg. & current to the TTL inputs.
CMOS Driving TTL in LOW state
 Here the CMOS o/p vtg. is low(0). From table…
 So, the low state o/p vtg. VOL of CMOS satisfy the VIL reqd.
of TTL. But IOL(max) of CMOS gate is not sufficient to drive
even a single TTL gate with IIL(max)=1.6 mA.So, use a non-
inverting buffer betn. CMOS & TTL to increase current
sourcing capacity.
 Comparison of CMOS & TTL
Sr. Parameter CMOS TTL
No.
1. Device used N-channel & P- BJT
channel MOSFET
2. Noise Better than TTL Less than
immunity CMOS
3. Switching Less than TTL Faster than
speed CMOS
4. Power PD=0.1 mW. Used 10 mW
dissi/gate for battery backup.
5. Fan out Typically 50 10
6. Power Flexible from 3V- Fixed=5V
supply vtg. 15V
University Asked Questions:-

Q.Explain Tristate logic o/p. (6M)

Q.Explain with neat diagram interfacing of a TTL

gate driving CMOS gate & vice versa. (8M)

Q.Difference between TTL & CMOS. (4M)