Gate Level Minimization

GATE LEVEL MINIMIZATION
Contents
 Introduction
 NAND and NOR implementation
 NAND Circuits
 NOR Implementation
 Nondegenerate Forms
Introduction
 Digital circuits are frequently constructed with NAND or

NOR gates rather than with AND and OR gates.
 NAND and NOR gates are easier to fabricate with electronic

components and are the basic gates used in all IC digital logic
families.
 Because of the prominence of NAND and NOR gates in the

design of digital circuits, rules and procedures have been
developed for the conversion from Boolean functions given in
terms of AND, OR, and NOT into equivalent NAND and
NOR logic diagrams.
NAND Circuits
The NAND gate is said to be a universal gate because any
logic circuit can be implemented with it.
A convenient way to implement a Boolean function with
NAND gates is to obtain the simplified Boolean function in
terms of Boolean operators and then convert the function to
NAND logic.
Three-input NAND gate
The conversion of an algebraic expression from AND,
OR, and complement to NAND can be done by simple
circuit manipulation techniques that change AND–OR
diagrams to NAND diagrams.
(xyz)’ = x’ + y’ + z’
Two-Level Implementation
The implementation of Boolean functions with NAND
gates requires that the functions be in sum-of-products
form.
F = AB + CD
F = ((AB + CD) ’ ) ’ = ((AB) ’ (CD) ’ ) ’
HDL for the above circuit:
w1
// Verilog model of two level
implementation circuit using NAND gates.
module two-level-gf (A, B, C, D, F); w2

output F;
input A, B, C, D;
wire w1, w2;
nand G1 (w1, A, B);
nand G2 (w2, C, D);
nand G3 (F, w1, w2);
endmodule
EXAMPLE
Implement the following Boolean function with NAND
gates: F (x, y, z) =∑ (1, 2, 3, 4, 5, 7)
The procedure described in the previous example indicates that a

Boolean function can be implemented with two levels of
NAND gates. The procedure for obtaining the logic diagram
from a Boolean function is as follows:
1. Simplify the function and express it in sum-of-products

form.
2. Draw a NAND gate for each product term of the expression that
has at least two literals. The inputs to each NAND gate are the
literals of the term. This procedure produces a group of first-level
gates.
3. Draw a single gate using the AND-invert or the invert-OR
graphic symbol in the second level, with inputs coming
from outputs of first-level gates.
4. A term with a single literal requires an inverter in the

first level. However, if the single literal is complemented,
it can be connected directly to an input of the second level
NAND gate.
F (x, y, z) =∑ (1, 2, 3, 4, 5, 7)
HDL for the above Boolean function:
F (x, y, z) =∑ (1, 2, 3, 4, 5, 7)
// Verilog model: Circuit with Boolean

expressions
module Circuit_Boolean_df (F, x, y, z);
output F;
input x, y, z;
assign F = (x && (!y)) || ((!x) && y) || z ;
endmodule
Multilevel NAND Circuits (SOP)
F = A (CD + B) + BC’
The general procedure for converting a multilevel
AND–OR diagram into an all-NAND diagram using
mixed notation is as follows:
1. Convert all AND gates to NAND gates with AND-invert

graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic

symbols.
3. Check all the bubbles in the diagram. For every bubble that is
not compensated by another small circle along the same line,
insert an inverter (a one-input NAND gate) or complement the
input literal.
HDL for the above Multilevel NAND Circuit (SOP)
w1
w2
w3
w4
// Verilog model of Multilevel level

implementation circuit using NAND gates.
module multi-level-gf (F, A, B, C, D);
output F;
input A, B, C, D;
wire B’, C’, w1, w2, w3, w4;
nand (B’, B, B),
(C’, C, C);
nand G1 (w1, C, D),
G2 (w2, w1,B’),
G3 (w3, A, w2),
G4 (w4, B, C’),
G5 (F, w3, w4);
endmodule
Multilevel NAND Circuits (POS)
F = (AB’ + A’B)(C + D’)
NOR Implementation
The NOR operation is the dual of the NAND operation. Therefore, all
procedures and rules for NOR logic are the duals of the corresponding
procedures and rules developed for NAND logic. The NOR gate is another
universal gate that can be used to implement any Boolean function.
Example-1
F = (A + B)(C + D)E
 The OR–AND pattern can easily be detected by the removal of the
bubbles along the same line. Variable E is complemented to
compensate for the third bubble at the input of the second-level
gate.
Example
F = (AB ’ + A ’ B)(C + D ’ )
HDL for the above Boolean function using NOR gates
F = (AB ’ + A ’ B)(C + D ’ )
w1
w3
w2
// Verilog model of Boolean function using

NOR gates.
module bolean-usingnor-gf (F, A, B, C, w4
D);
output F;
input A, B, C, D;
wire A’, B’, D’, w1, w2, w3, w4;
nor (A’, A, A),
(B’, B, B),
(D’, D, D);
nor G1 (w1, A’, B),
G2 (w2, A, B’),
G3 (w4, C, D’),
G4 (w3, w1, w2),
G5 (F, w3, w4);
endmodule
Nondegenerate Forms
The eight nondegenerate forms produce an
implementation in sum-of-products form or product-
of-sums form. The eight nondegenerate forms are as
follows:
 AND–OR
 OR–AND
 NAND–NAND
 NOR–NOR
 NOR–OR
 NAND–AND
 OR–NAND
 AND–NOR
AND–OR–INVERT Implementation
F = (AB + CD + E)’
OR–AND–INVERT Implementation
The OR–NAND and NOR–OR forms perform the
OR–AND–INVERT function.
F = (A + B)(C + D)E’
HDL for the above AND-OR-INVERT & OR-AND-INVERT Circuit
F = (AB + CD + E)’ F = (A + B)(C + D)E’

expressions
expressions
module Circuit_Boolean_df (F, A, B, C,
module Circuit_Boolean_df (F, A, B, C,
D, E);
D, E);
output F;
output F;
input A, B, C, D, E;
input A, B, C, D, E;
assign F = !((A && B) || (C&& D) || E) ;
assign F = (A || B) && (C || D) && (!E) ;
endmodule
endmodule
THANK YOU

Gate Level Minimization

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Gate Level Minimization

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GATE LEVEL MINIMIZATION

 NAND and NOR implementation

 Digital circuits are frequently constructed with NAND or

 NAND and NOR gates are easier to fabricate with electronic

 Because of the prominence of NAND and NOR gates in the

module two-level-gf (A, B, C, D, F); w2

The procedure described in the previous example indicates that a

1. Simplify the function and express it in sum-of-products

4. A term with a single literal requires an inverter in the

// Verilog model: Circuit with Boolean

1. Convert all AND gates to NAND gates with AND-invert

2. Convert all OR gates to NAND gates with invert-OR graphic

// Verilog model of Multilevel level

// Verilog model of Boolean function using

F = (AB + CD + E)’ F = (A + B)(C + D)E’

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