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    Topic 1.1 Systems Architecture

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    Topic 1.1 Systems Architecture

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    duncan
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    11. Systems_architecture_L4_L5_Teacher_PowerPoint_v1

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    96 views26 pages

    Topic 1.1 Systems Architecture

    Uploaded by

    duncan

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 26

    Topic 1.

    1 Systems architecture
    Sub topic 1.1.1 - Architecture of the CPU
    Lessons 4-5 of 9 - Von Neumann architecture
    © OCR 2020
    Contents
    Topic Allocated time
    Lesson 4 Big picture 5 minutes
    Lesson 4 – Activity 1 10 minutes
    Lesson 4 – Activity 2 10 minutes
    Plenary 5 minutes
    Talking through lesson 4 slides 30 minutes
    Lesson 5 – Big picture 5 minutes
    Lesson 5 – Activity 1 10 minutes
    Lesson 5 – Activity 2 15 minutes
    Plenary 5 minutes

    © OCR 2020
    Big picture
    • Where are instructions that are currently in use
    stored?
    • What else is stored in main memory?
    • How are instructions executed by the
    processor?

    © OCR 2020
    Learning objectives
    • To be able to label an internal diagram of the CPU
    • To be able to describe the purpose of the
    accumulator
    • To be able to explain the purposes of the ALU, CU
    and the cache
    • To be able to describe the roles of the MAR and
    the MDR in the fetch part of the fetch-execute cycle

    © OCR 2020
    Keywords

    • Von Neumann • ALU (Arithmetic Logic Unit)


    architecture • CU (Control Unit)
    • MAR (Memory Address • Cache
    Register) • Fetch/execute
    • MDR (Memory Data • Buses
    Register)
    • Program Counter
    • Accumulator

    © OCR 2020
    Activity 1

    • On the Diagram given…


    – use research to try and identify the terms on
    the sheet
    – write the definitions/explanations of what they
    do in the boxes
    – then try and label the diagram accurately.

    © OCR 2020
    Activity 1 - Answers

    Address bus 0001 INP


    0010 Add 5
    PC MAR INP
    0011
    0100 STO 8
    0101 INP
    0110 ADD 8
    0111
    1000
    MDR Data bus 1001
    1010
    1011
    1100
    ALU 1101
    Accumulator

    © OCR 2020
    Von Neumann architecture

    • In the early 1940s, computers stored data


    that was worked on in memory, the
    program was not stored and they used
    paper tape, punch cards or switches.
    • The mathematician John Von Neumann
    and colleagues had an idea to store the
    program instructions and the data all in
    memory.
    © OCR 2020
    Computer system

    Processor Main Memory I/O

    1945: John Von Neumann

    © OCR 2020
    Von Neumann architecture
    An example of how the program and the
    data are stored in the same memory to allow
    data flow between memory and the
    processor: Program
    Program
    Program
    Program

    Data
    Data
    Data
    © OCR 2020
    Processor - Registers
    • PC – Program Counter
    – Holds the location of the next instruction/data address in
    main memory
    • MAR – Memory Address Register
    – The contents of the PC are copied here and then
    transferred along the address bus

    Main
    PC MAR Address bus Memory

    © OCR 2020
    Processor - Registers
    • MDR – Memory Data Register
    – Once data/instructions are brought from the Memory
    address in main memory, they are placed in the MDR.

    Main
    MDR Data bus
    Memory

    © OCR 2020
    Processor

    Control bus (read/write signals)

    Address bus
    System Clock Processor Main
    Hz Memory

    Data bus

    © OCR 2020
    Activity 2 - Von Neumann
    architecture
    • Complete the diagram on the worksheet.

    © OCR 2020
    Activity 2 - Answers
    CPU

    CU ALU

    Registers

    ACC MAR

    PC MDR

    Cache

    © OCR 2020
    Plenary

    • Questioning
    • Produce question + Mark Scheme
    • Exit Pass – Describe the registers and
    what each do

    © OCR 2020
    Lesson 5 – Big picture

    Why have processors got smaller?

    © OCR 2020
    Learning objectives

    • To describe the importance of the Program


    Counter in the Fetch-Execute cycle
    • To understand how Fetch – Decode - Execute
    works in more detail

    © OCR 2020
    What happens in the FDE cycle?

    • Fetch part of the cycle:


    – Program counter is incremented for each
    instruction of the program being executed.
    – The contents of the Program Counter are put
    into the MAR (Memory Address Register).
    – The address is transferred along the address
    bus to main memory (this address indicates
    which part of memory to fetch the data/
    instructions from.
    © OCR 2020
    What happens in the FDE cycle?

    • Fetch part of the cycle:


    – The data/instruction that has been addressed is
    transferred back to the processor along the data
    bus.
    – This is held in the MDR (Memory Data Register).

    © OCR 2020
    What happens in the FDE cycle?

    • Decode/Execute part
    – The instruction is split into an Op-Code and
    an Operand.
    – The instruction is carried out by the ALU
    (Arithmetic Logic Unit).

    © OCR 2020
    Executing instructions
    • ALU (Arithmetic Logic Unit)
    – Performs arithmetic and logical operations
    including +, -, AND, OR
    • Accumulator
    – Results of calculations are placed into the
    Accumulator

    Accumulator
    ALU

    © OCR 2020
    Lesson 5 - Activity 1
    • Produce a labelled diagram of the internal
    components of a computer system
    – See Lesson 5 Activity 1

    • In pairs, describe in words how the Fetch-Execute


    Cycle works

    © OCR 2020
    Lesson 5 – Activity 2
    • FDE cycle

    © OCR 2020
    Plenary

    • Questioning
    • Produce question + Mark Scheme
    • Exit Pass – Describe the FDE cycle

    © OCR 2020
    OCR Resources: the small print
    OCR’s resources are provided to support the delivery of OCR qualifications, but in no way constitute an endorsed teaching method that is required by the Board, and the decision to use them lies with the individual teacher. Whilst every
    effort is made to ensure the accuracy of the content, OCR cannot be held responsible for any errors or omissions within these resources.
     
    Our documents are updated over time. Whilst every effort is made to check all documents, there may be contradictions between published support and the specification, therefore please use the information on the latest specification at
    all times. Where changes are made to specifications these will be indicated within the document, there will be a new version number indicated, and a summary of the changes. If you do notice a discrepancy between the specification and
    a resource please contact us at:
    [email protected].

    © OCR 2020 - This resource may be freely copied and distributed, as long as the OCR logo and this message remain intact and OCR is acknowledged as the originator of this work. OCR acknowledges the use of the following content:

    Please get in touch if you want to discuss the accessibility of resources we offer to support delivery of our qualifications: [email protected]

    © OCR 2020

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