Pin Assignment

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Pin Assignment

Pin Assignment
 During floorplanning, the terminal locations of nets connecting these blocks are very
important.
 I/O pins (net terminals) and their locations are usually on the periphery of a block to
reduce interconnect length.
 best locations depend on the relative placement of the blocks.

Problem formulation.
 During pin assignment, all nets (signals) are assigned to unique pin locations
 Optimization goals - maximizing routability and minimizing electrical parasitics
Pin Assignment
Pin assignment using concentric circles
Pin assignment using concentric circles
Pin assignment using concentric circles
Topological pin assignment
Improvement of concentric-circle pin assignment algorithm by taking into account external
block positions and multi-pin nets (connected to more than two pins). Specifically, this
enabled pin assignment when external pins are behind other blocks or obstacles.
Topological pin assignment
Power and Ground Routing
Power and Ground Routing

• Chip planning determines not only the layout of the power-


ground distribution network, but also the placement of supply I/O
pads (with wire-bond packaging) or bumps (with flip-chip
packaging).

• The pads or bumps are preferentially located in or near high-


activity regions of the chip to minimize the V = IR voltage drop

• Power and Ground laid our on the metal layer


Power and Ground Routing

(1) early simulation of major power dissipation components,

(2) early quantification of chip power,

(3) analyses of total chip power and maximum power density,

(4) analyses of total chip power fluctuations,

(5) analyses of inherent and added fluctuations due to clock gating, and

(6) early power distribution analysis: average, maximum and multi-cycle fluctuations.
Power and Ground Routing
• To construct an appropriate supply network, many aspects of the design and the
process technology must be considered.

For example, to estimate chip power, the designer must plan for

(1) use of low-Vth devices and dynamic circuits that consume more power

(2) use of clock gating for low power

(3) quantity and placement of added decoupling capacitors that mitigate switching
noise.
Design of a Power-Ground Distribution Network
As each cell must have both VDD and GND connections, the supply nets
(1) are large,
(2) span across the entire chip, and
(3) are routed first before any signal routing.

Routing of supply nets.


• should have dedicated metal layers to avoid consuming signal routing resources.
• supply nets prefer thick metal layers –low resistance.
• Traverses multiple layers, - sufficient vias - avoiding electromigration and reliability
issues.

 the net segment width must be chosen to keep the voltage drop, V = IR, within a specified
tolerance, e.g., 5% of VDD.
 Wider segments have lower resistance, and hence lower voltage drop
Two design approaches
• the planar approach, which is used primarily in analog or custom blocks,
• the mesh approach, which is predominant in digital ICs
Planar Routing
Power supply nets can be laid out using planar routing when

(1) only two supply nets are present in the design, and

(2) a cell needs a connection to both supply nets.

Planar routing separates the two supply regions by a Hamiltonian path that connects all the cells
Planar Routing
Step 1: Planarize the topology of the nets
Step 2: Layer assignment
Step 3: Determining the widths of the net segments
Mesh Routing
Step 1: creating a ring

Step 2: connecting I/O pads to the ring

Step 3: creating a mesh

Step 4: creating Metal1 rails

Step 5: connecting the Metal1 rails to the mesh


Construction of a mesh power-ground distribution network.
References
https://www.youtube.com/watch?v=9McvH_RPGME
Placement
Solution

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