Functions of Combinational

Logic
Adders
Comparators
Decoders
Encoders
Code Converters
Multiplexers
Demultiplexers
Parity Generators
Checkers

1
Basic adders :
Half – adder
 Basic rules for binary addition

 Half – adder accepts two binary digits on its inputs

and produces two binary digits on its outputs, a sum
bit and a carry bit.

2
 Basic adders :
Half – adder
 Logic symbol

3
 Basic adders :
Half – adder
 Truth table for half - adder

A B COUT 
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
= sum
Cout = output carry
A and B = input variables (operands) 4
Basic adders :
Half – adder
 Half – adder logic diagram

5
Basic adders :
Full – adder
 Full – adder accepts two input bits and an input
carry and generates a sum output and an output
carry.
 Logic symbol

6
Basic adders :
Full – adder
 Truth table

A B C COUT 
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
= sum
Cout = output carry 7

A and B = input variables (operands)

Basic adders :
Full – adder
 Logic circuit

8
Basic adders :
Full – adder

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The full-adder must add the two input bits and the input carry. From
the half-adder, the sum of the input bits A and B is the exclusive-OR
of those two variables. For the input carry (Cin) to be added to the
input bits, it must be exclusive-ORed, and last yield the equation for
the sum output of the full-adder

10
This is mean that to implement the full-adder sum function, two 2-
input exclusive-OR gates can be used . The first must generate the
term AB and the second has as its inputs the output of the first XOR
gate and the input carry.

The output carry is a 1 when both inputs to the first XOR gate are 1s or
when both inputs to the second XOR gate are 1s. The output carry of
full-adder is therefore produced by the inputs A ANDed with B and
AB ANDed with Cin.

11
Basic adders :
Full – adder
 Full – adder implemented with half - adders

12
Example: Determine the outputs
for the inputs shown

If A = 1, B = 1 and Cin = 1 ????

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Parallel Binary Adders
 Two or more full – adders are connected.

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Parallel Binary Adders
Four – Bit Parallel Adders
 A group of four is called nibble.

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Parallel Binary Adders
Four – Bit Parallel Adders

16
Parallel Binary Adders
Four – Bit Parallel Adders

17
 Truth Table for a 4-Bit Parallel
Adder
Cn-1 An Bn Σn Cn

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0 Use the 4-bit parallel adder truth table to

0 1 1 0 1
find the sum and output carry for the
following two 4-bit numbers if the input
1 0 0 1 0 carry (Cn-1) is 0.

1 0 1 0 1 A4A3A2A1 = 1100, B4B3B2B1 = 1100

1 1 0 0 1

1 1 1 1 1
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 11000

n=1, A1 = 0, B1 = 0 and Cn-1 = 0 Σ1 = 0 and C1 = 0

n=2, A2 = 0, B2 = 0 and Cn-1 = 0 Σ2 = 0 and C2 = 0

n=3, A3 = 1, B3 = 1 and Cn-1 = 0 Σ3 = 0 and C3 = 1

n=4, A4 = 1, B4 = 1 and Cn-1 = 1 Σ4 = 1 and C4 = 1

Try This!
1011 add with
1010 and Assume
Cn-1 = 0

10101
19
The 74LS283
4-Bit Parallel
Adder

20
Adder Expansion
8-Bits

16-Bits

21
Example:
Show how two 74LS283 adders can be connected to form an 8-bit parallel
adder. Show output bits for the following 8-bit input numbers:
A8A7A6A5A4A3A2A1 = 10111001 and B8B7B6B5B4B3B2B1 = 10011110

Σ8Σ7Σ6Σ5Σ4Σ3Σ2Σ1 = 101010111
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 Comparators
The basic function of a comparator is to compare the magnitude of two
binary quantities to determine the relationship of those quantities

 1-Bit Comparator
 2-Bit Comparator
 4-Bit Comparator

23
 1-Bit Comparator

The output is 1 when the inputs are equal

 2-Bit Comparator

The output is 1 when A0 = B0 AND A1 = B1

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• 4-Bit Comparator
One of three outputs will be HIGH:
• A greater than B (A > B)
• A equal to B (A = B)
• A less than B (A < B)

To determine an inequality of binary numbers A and B, first,

examine the highest order bit in each number. The following
conditions are possible:
1. If A3 = 1 and B3 = 0, number A is greater than number B
2. If A3 = 0 and B3 = 1, number A is less than number B
3. If A3 = B3 then you must examine the next lower bit position for
an inequality 25
Example:
Determine the A = B, A > B and A < B outputs for the input
numbers shown on Figure below:
A > B is HIGH and the
other outputs are LOW
Try This:
A3A2A1A0 B3B2B1B0
1 0 0 1 1 0 1 0
A < B is HIGH and the
other outputs are LOW

Try This:
A3A2A1A0 B3B2B1B0
1 0 1 1 1 0 1 0
26
Decoders
 Basic function of decoder is to detect the presence
of a specified combinations of bits (code) on its
inputs and to indicate the presence of that code by
a specified output level.
 Its general form, a decoder has n input lines to
handle n bits and from one to 2n output line to
indicate the presence of one or more n – bit
combinations.

27
Basic Binary Decoder
 Decoding logic for the binary code 1001 with an
active – HIGH output.

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Determine the logic required to decode the binary number
1011 by producing a HIGH level on the output
Try This:
Develop the logic
required for 10010 and
X  A3 A2 A1 A0  1011 produce an active LOW
output

29
4 – Bit Decoder
 In order to decode all possible combinations of four
bits, sixteen decoding gates are required (24 = 16).
 This decoder commonly called either a 4 – line – to
– 16 – line decoder because there are four inputs
and sixteen outputs.
 It can also be called 1 – of – 16 decoders because
for any given code on the inputs, one of the sixteen
outputs is activated.

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 4 – Bit Decoder
Decimal Binary Inputs Outputs
Decoding
A3 A2 A1 A0 Function
Digit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 A 3A 2 A 1A 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 1 A 3A 2 A 1A 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 0 0 1 0 A 3A 2 A 1A 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

3 0 0 1 1 A 3A 2 A 1A 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

4 0 1 0 0 A 3A 2 A 1A 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

5 0 1 0 1 A 3A 2 A 1A 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

6 0 1 1 0 A 3A 2 A 1A 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

7 0 1 1 1 A 3A 2 A 1A 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1

8 1 0 0 0 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

9 1 0 0 1 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1

10 1 0 1 0 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1

11 1 0 1 1 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1

12 1 1 0 0 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1

13 1 1 0 1 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1

14 1 1 1 0 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1

15 1 1 1 1 A 3A 2 A 1A 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
31
4 – Bit Decoder
 Logic symbol for a 4 – line
– to – 16 line decoder

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The 74HC154 1-of-16 Decoder
The IC will active if gate
output (EN) is HIGH

If /CS1 and /CS2 are

LOW, so EN will HIGH
and IC is active!

33
Example:
A certain application requires that a 5-bit number be decoded. Use 74HC154
decoders to implement the logic. The binary number is represented by the
format A4A3A2A1A0.

Determine the
output in Figure
that is activated for
the binary input 1
0110?

Answer: ?
Enable Disable
Disable Enable
0 1

1
0
34
BCD – to – Decimal Decoder
Decimal BCD Code
Decoding
Digit A3 A2 A1 A0 Function

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1 35
Example:
The 74HC42 is an integrated circuit BCD-to-decimal decoder. The logic symbol
is shown in Figure below. If the input waveforms shown are applied to the
inputs of the 74HC42, show the output waveforms.

0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 0 0
0 0 0 0 1 1 1 1 0 0
0 0 0 0 0 0 0 0 1 1

36
Exercise:
Construct a timing diagram showing input and output waveforms for
the case where the BCD inputs sequence through the decimal
numbers as follows: 0, 2, 4, 6, 8, 1, 3, 5 and 9

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BCD – to – 7 Segment
Decoder
 Accepts the BCD code on its inputs and
provides outputs to drive 7 – segment display
devices to produce a decimal readout.

38
Truth Table for BCD-to-7
Segment Decoder

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40
Encoders
 Combinational logic circuit that essentially performs
a “reverse” decoder function.
 Encoder accepts an active level on one of its input
representing a digit, such as a decimal or octal digit,
and convert it to a coded output, such as BCD or
binary.
 Encoders can also be devised to encode various
symbols and alphabetic characters.
 Process of converting from familiar symbols or
numbers to a coded format is called coding.
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Decimal – to – BCD Encoders
 Has 10 inputs – one
for each decimal digit
– and four outputs
corresponding to the
BCD code.
 This is a basic 10 –
line – to – 4 – line
encoder.

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 Decimal – to – BCD Encoders
Decimal
A3 A2 A1 A0
 Truth Table digit
 A3 = 8 + 9 0 0 0 0 0

 A2 = 4 + 5 + 6 +7 1 0 0 0 1

 A1 = 2 + 3 + 6 + 7 2 0 0 1 0
3 0 0 1 1
 A0 = 1 + 3 + 5 + 7 + 9
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
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Decimal – to – BCD Encoders
 Basic logic diagram

44
Decimal – to – BCD Encoders
Priority Encoder
 Encoder will produce a BCD output corresponding
to the highest – order decimal digit input that is
active and will ignore any other lower – order active
inputs.
 Example : If 6 and 3 inputs are both active, BCD
output is 0110 (represent decimal number 6).

45
8 – Line – to – 3 – Line
Encoder

46
Code Converters
 Methods of using combinational logic circuits to
convert from one code to another.

47
Code Converters
Binary – to – Gray Conversion

48
Code Converters
Gray – to – Binary Conversion

49
Multiplexers
 A device that allows a digital information from
several sources to be routed onto a single line for
transmission over that line to a common destination.
 Basic multiplexer has several data – input lines and
a single output line.
 It also has data – select inputs, which permit digital
data on any one of the inputs to be switched to the
output line.
 Also known as data selectors.

50
Multiplexers
 Logic symbol for a 4 – input multiplexer (MUX)

51
Multiplexers
 Data selection for a 1 – of – 4 – multiplexers
Data – Select Inputs
Input Selected
S1 S0

0 0 D0

0 1 D1

1 0 D2

1 1 D3

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Multiplexers
 Logic diagram

53
Example:
Determine the output waveform in relation to the inputs

54
Exercise: Determine the output waveform in relation to the inputs

55
Demultiplexers
 Reverse the multiplexing function.
 It takes digital line and distributes it to a given
number of output lines.
 Also known as data distributor.

56
Demultiplexers
 1 – line – to – 4 – line demultiplexers (DEMUX)

57
Exercise:
Determine the data-output waveforms

58
Parity Generators / Checkers
 Errors can occur as digital codes are being
transferred from one point to another within a digital
system or while codes are being transmitted from
one system to another.
 Errors can take form of undesired changes in the
bits (1 change to 0 or vice versa).
 Parity method of error detection is when a parity bit
is attached to a group of information bits in order to
make the total number of 1s either even or odd
(depending on the system)

59
Basic Parity Logic
 In order to check for or to generate the proper parity
in a given code, a basic principle can be used :

The sum (disregarding carriers) of an even

number of 1s is always 0, and the sum of an odd
number of 1s is always 1.

 To determine if a given code has even parity or odd

parity, all the bits in that code are summed.

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Basic Parity Logic

61
Parity Checker
 When the device is used as an even parity checker,
the number of input bits should always be even; and
when parity error occurs, the  Even output goes
LOW and the  Odd output goes HIGH.

 When it used as odd parity checker, the number of

input bits should always be odd; and when parity
error occurs, the  Odd output goes LOW and the 
Even output goes HIGH.

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Parity Generator
Even parity generator
 The parity bit is taken at the  Odd output because this output
is:
 0 if there is an even number of input bits
 1 if there is an odd number.

Odd parity generator

 The parity bit is taken at the  Even output because this
output is:
 0 if there is an odd number of input bits
 1 if there is an even number.

63
Examples
1. Add an even parity bit to each of the
following codes:
(a) 110100 (b) 01100011
2. Add an odd parity bit to each of the following
codes:
(a) 1010101 (b) 1000001
3. Check each of the even parity codes for an
error.
(a) 100010101 (b) 1110111001
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Even Parity Checker

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Even Parity Generator

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 Exercises
• Homework: Odd Parity Checker and Odd
Parity Generator.

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Tutorial:
1. For the parallel adder,
determine the sum and carry.

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2.The input waveforms are applied to a 2-bit
adder. Determine the waveforms for outputs.

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3. For comparator, determine the
output when A = B

70
4. You wish to detect only the presence of
the codes 1010, 1100, 0001 and 1011. An
active-HIGH output is required to indicate
their presence. Develop the minimum
decoding logic with a single output that will
indicate when any one of these codes in
on the inputs. For any other code, the
output must be LOW.

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