Register Transfer Languages (RTL)

Overview
Register Transfer Language
Register Transfer

Bus and Memory Transfers

Arithmetic Micro-operations

Logic Micro-operations
Shift Micro-operations

Arithmetic Logic Shift Unit

Basic Definitions
Digital system is a collection of digital hardware modules Modules are registers, counters, arithmetic elements, etc connected via: - data paths routes on which information is moved - control paths routes on which control signals are moved Micro operations (micro-ops) are operations on data stored in registers. The result may be transferred to another register or may replace the previous binary information of the register. Digital modules (often just called registers) are defined by their information contents and the set of micro-ops they perform Register transfer language is a concise and precise means of describing those operations

Data-paths and Control units

Data-path module comprises processing logic and

collection of registers that perform data processing Control unit module is made up of logic that determines the sequence of data processing operations carried out in the data-path

Register Transfer Operations

Registers: denoted by

upper case letters, and optionally followed by digits or letters {MAR(Memory Address Register),
PC(Program Counter), IR(Instruction Register), R1(Processor Register)}

Register transfer

operations: the movement of data stored in2registers and the R R1 processing performed on the data.
(transfer of the content of register R1 into

What is Register Transfer Language?

Register Transfer Language (RTL): used to describe

CPU organization in high-level terms RTL expressions are made up of elements which describe the registers being manipulated, and the micro-ops being performed on them Here are the basic components of RTL expressions:

Instruction Representation

Word size is 16 bits 12 bits to represent a memory address 3-bit opcode 1 bit to distinguish between direct and indirect memory addressing

Instruction Representation (cont.)

When the I (indirect) bit

is 0, the value in AD is the actual address of the operand (direct addressing) When I is 1, contains the address of an indirect word, which in turn will contain the actual operand address (indirect addressing)

Register Structure

Common Micro-Ops
There are 4 types of Micro-Ops: Transfer: transfers data from one register to another R0 <- R1
Arithmetic: performs arithmetic on data in registers

R0 <- R1 + R2
Logic/bit manipulation: performs bit (Boolean) operations on

data R0 <- R1 & R2 ; or R0 <- R1 | R2

Shift: shift data in registers by one or more bit positions

R0 <- R1 << 3; or R0 <- R2 >> 2

Micro-Ops Transfer Parallel

Parallel transfer is typically used for transfers between registers Ex: Transfer all contents of A into B on one clock pulse A <- B Control function: we can do this by structuring the RTL expression to indicate the controlling condition. The transfer occurs only under a predetermined control condition. A control function is a boolean variable either 0 or 1. EgThe transfer operation is executed by the hardware only if P=1..
if ( P 1) then ( R 2 R1) P : R 2 R1

n outputs are connected to n inputs

Micro-Ops Transfer Serial

Serial transfer is used to specify that a collection of bits are to be moved, but that the transfer is to occur one bit at a time
Ex:
S: A <- B, B <-B

Micro-Ops Transfer Bus

A bus consists of a set of parallel data lines To transfer data using a bus: connect the output of the source register to the bus; connect the input of the target register to the bus; when the clock pulse arrives, the transfer occurs A bus system will multiplex k registers of n bits each to produce an n line common bus. The no. of multiplexer needed to construct the bus is equal to n, the no. of bits in a register, with size kX1.

Bus and Memory Transfers

Common Bus A more efficient scheme for transferring information between registers in a multiple-register configuration A bus structure = a set of common lines Control signals determine which register is selected
One way of constructing a common bus system is with multiplexers The multiplexers select the source register whose binary information is place on the bus

The construction of a bus system for four registers :

4 bit register X 4 Four 4 : 1 Multiplexers Register selected S1 S0 Selection : S0, S1 Bus
0 0 1 1 0 1 0 1 A B C D

8 Registers with 16 bit

16 : 1 mux

 Bus Transfer The content of register C is placed on the bus, and the content of the bus is loaded into register R1 by activating its load control input of the destinationBus Bus C , R1 register.
R1 C

Three-State Bus Buffers A bus system can be constructed with three-state gates instead of multiplexers Tri-State : 0, 1, High-impedance(Open circuit) Buffer

A device designed to be inserted between other devices to match impedance, to prevent mixed interactions, and to supply additional drive or relay capability Buffer types are classified as inverting or noninverting When control input =1 : The outputIfis enabled(output Y = input A) Normal C=1, Output Y = A input A input =0 : The output is disabled(output Y = highWhen control If C=0, Output = High-impedance impedance) Control
input C

Tri-state buffer gate :

 The construction of a bus system with tri-state buffer :

Fig. 4-5
The outputs of four buffer are connected together to form a single

bus line(Tri-state buffer No more than one buffer may be in the active state at any given time(2 X 4 Decoder To construct a common bus for 4 register with 4 bit : (register decoderbuffer)

Overview
Register Transfer Language
Register Transfer

Bus and Memory Transfers

Arithmetic Micro-operations

Logic Micro-operations
Shift Micro-operations

Arithmetic Logic Shift Unit

Memory - RAM
Memory (RAM) can be thought as a sequential circuits containing some number of registers These registers hold the words of memory Each of the r registers is indicated by an address These addresses range from 0 to r-1 Each register (word) can hold n bits of data Assume the RAM contains r = 2k words. It needs the following data input lines 1. n data input lines n 2. n data output lines address lines 3. k address lines k RAM Read 4. A Read control line unit Write 5. A Write control line
n data output lines

Memory Transfer
Memory is usually accessed in computer systems by putting the desired address in a special register, the Memory Address Register (MAR, or AR)

M
AR Memory unit Read Write Data in

Data out

Micro-Ops Transfer Memory

Memory transfers are similar to register transfers, but Memory to register transfers are called read operations, while register to memory transfers are called write operations
RTL expressions for a read operation, assuming the use of an address registers:
AR <- address DR <- M[AR]

Memory read : A transfer information into DR from the memory word M selected by the address in AR RTL expressions for a write operation, assuming use of a data register:
AR <- address DR <- value M[AR] <- DR Memory Write : A transfer information from R1 into the memory word M selected by the address in AR

SUMMARY OF R. TRANSFER MICROOPERATIONS

A B AR DR(AD) 1.Transfer content of reg. B into reg. A 2.Transfer content of AD portion of reg. DR into reg. AR

A constant
ABUS R1, R2 ABUS time, AR DR M[R] M DR M

3.Transfer a binary constant into reg. A

4.Transfer content of R1 into bus A and, at the same transfer content of bus A into R2 5.Address register 6.Data register 7.Memory word specified by reg. R 8.Equivalent to M[AR] 9.Memory read operation: transfers content of memory word specified by AR into DR

M DR

10.Memory write operation: transfers content of DR into memory word specified by AR

MICROOPERATIONS

Computer system microoperations are of four types: Register transfer microoperations Arithmetic microoperations Logic microoperations

Shift microoperations

Arithmetic MICROOPERATIONS
The basic arithmetic microoperations are
Addition Subtraction Increment Decrement

The additional arithmetic microoperations are

Add with carry Subtract with borrow Transfer/Load etc.

Summary of Typical Arithmetic Micro-Operations

R3 R3 R2 R2 R3 R1 R1 R1 + R2 R1 - R2 R2 R2+ 1 R1 + R2+ 1 R1 + 1 R1 - 1 Contents of R1 plus R2 transferred to R3 Contents of R1 minus R2 transferred to R3 Complement the contents of R2 2's complement the contents of R2 (negate) subtraction Increment Decrement

Binary Adder
Binary Adder

B3 FA

A3 C3

B2 FA

A2 C2

B1 FA

A1 C1

B0 FA

A0 C0

C4

S3

S2

S1

S0

Binary Adder-Subtractor
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

FA

C3

FA

C2

FA

C1

FA

C0

C4

S3

S2

S1

S0

The mode input M controls the operations. When M=0 the circuit is an adder and when M=1 the circuit becomes a subtractor. When M=0 we have B 0 = B the circuit performs A plus B. When M=1 we have B 1 =B` and C0=1 . The B inputs are than complemented and a 1 is added through the input carry. So, the operation becomes A plus 2s complement of B.

Binary Incrementer
Binary Incrementer
A3 A2 A1 A0 1

y S

y S

y S

y S

HA
C

HA
C

HA
C

HA
C

C4

S3

S2

S1

S0

The half adders are connected in cascade.

Arithmetic Circuits
S1 S0 A0 S1 S0 B0 0 1 2 3 X0 C0 D0

4x1 MUX

Y0

FA C1
C1

A1
S1 S0 B1 0 1 2 3

X1

4x1 MUX

Y1

FA

D1

C2

S1 S0Cin Y O/P 0 0 0 B D=A+B 0 0 1 B D=A+B+1 0 1 0 B D = A + B 0 1 1 B D = A + B+ 1 1 0 0 0 D=A 1 0 1 0 D=A+1 1 1 0 1 D=A1 1 1 1 1 D=A

A2 S1 S0 B2 0 1 2 3

X2

C2

4x1 MUX

Y2

FA

D2

C3

A3 S1 S0 B3 0 1 2 3 0 1

X3

C3 D3

MUX

4x1

Y3

FA

C4 Cout

The basic component of an arithmetic circuit is parallel adder. By controlling data inputs, it is possible to have different operations.

Micro-Ops Arithmetic & Logic

CPU typically provides addition, subtraction, increment,

and decrement operations in its ALU (arithmetic-logic unit). Logic micro-ops are like arithmetic, but treat each bit of the register(s) separately

Applications of Logic Micro-ops

Logic microoperations consider each bit of the register separately

and treat them as binary variables

Logic microoperations are very useful for manipulating individual

bits or a portion of a word stored in a register used to change

bit values, delete a group of bits, or insert new bit values

Selective-set A A B

The selective-set operation sets to 1 the bits in register A where there are corresponding 1s in register B. It does not effect bit positions that have 0s in B

A A B
Selective-complement

The selective-complement operation complements bits in A where there are corresponding 1s in B. It does not effect bit positions that have 0s in B

 Selective-clear A B A

The selective-clear operation clears to 0 the bits in A only where there are corresponding 1s in B A Selective-mask A B The mask operation is similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0s in B

Insert

The insert operation inserts a new value into a group of bits This is done by first masking the bits and then ORing them with the required value

Clear

The clear operation compares the words in A and B and produces an all 0s result if the two numbers are equal

Micro-Ops Shift

Move the information in a register by one bit position Shifts come in three varieties:

- Logical - Arithmetic - Circular

Shift Microoperations
There are three types of shifts
Logical shift Circular shift Arithmetic shift

What differentiates them is the information that goes into the serial input A right shift operation

Serial input

A left shift operation

Serial input

Logical Shift
In a logical shift the serial input to the shift is a 0. A right logical shift operation:
0

A left logical shift operation:

0

In a Register Transfer Language, the following notation is used

shl for a logical shift left shr for a logical shift right Examples: R2 shr R2 R3 shl R3

Circular Shift
In a circular shift the serial input is the bit that is shifted out of the other end of the register.

A right circular shift operation:

A left circular shift operation:

In a RTL, the following notation is used

cil for a circular shift left cir for a circular shift right Examples: R2 cir R2 R3 cil R3

Arithmetic Shift
An arithmetic shift is meant for signed binary numbers (integer) An arithmetic left shift multiplies a signed number by two An arithmetic right shift divides a signed number by two The main distinction of an arithmetic shift is that it must keep the sign of the number the same as it performs the multiplication or division

A right arithmetic shift operation:

sign bit

A left arithmetic shift operation:

sign bit

Arithmetic Shift
An left arithmetic shift operation must be checked for the overflow
0
sign bit

Before the shift, if the leftmost two bits differ, the shift will result in an overflow

In a RTL, the following notation is used

ashl for an arithmetic shift left ashr for an arithmetic shift right Examples: R2 ashr R2 R3 ashl R3

Hardware Implementation of Shift Microoperation

Serial input (IR) Select 0 for shift right (down) 1 for shift left (up)

S 0 1 A0 A1 A2 A3 S 0 1 MUX H1

MUX

H0

S 0 1 MUX H2

S 0 1 Serial input (IL) MUX H3

Arithmetic and Logical Unit

Registers are connected to a common

operational unit which consists of various storage registers known as ALU. It performs an operation and the result of the operation is then transferred to a destination register. The ALU is combinational circuit so that the entire register transfer from register to the other register via ALU can be performed in one clock cycle.

Arithmetic Logic and Shift Unit

S3 S2 S1 S0 C i

Arithmetic Circuit

Select 0 C i+1 1 2 3

4x1 MUX

Logic
Bi A i

Circuit
shr

A
A

i-1 i+1

shl

S3 S2 S1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 X 1 1 X

S0 0 0 1 1 0 0 1 1 0 1 0 1 X X

Cin 0 1 0 1 0 1 0 1 X X X X X X

Operation F=A F=A+ 1 F=A+ B F=A+ B+ 1 F = A + B F = A + B+ 1 F=A- 1 F=A F=A B F=AB F=A B F = A F = shr A F = shl A

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