Pinouts of 8086

PINOUTS OF 8086
MICROPROCESSOR
2
Pin Diagram
of 8086
SIGNAL DESCRIPTION OF 8086:
3
• This microprocessor operates in • The 8086 signals are

single processor or categorized into 3 types:
multiprocessor configurations • Common signals for both
to achieve high performance. minimum mode and
maximum mode.
• Some of the pins serve a
• Special signals which are
particular function in minimum
meant only for minimum
mode (single processor mode) mode
and others function in • Special signals which are
maximum mode meant only for maximum
(multiprocessor mode). mode
• AD7- AD0 : The address/ data bus lines are the multiplexed address data bus
4
and contain the right most eight bit of memory address or data. The address and
COMMON data bits are separated by using ALE signal.
SIGNALS FOR • AD15- AD8 : The address/data bus lines compose the upper multiplexed
BOTH MINIMUM address/data bus. This lines contain address bit A15- A8 or data bus D15- D8 .
The address and data bits are separated by using ALE signal.
MODE AND
MAXIMUM • A19/S6- A16/ S3 The address/status bus bits are multiplexed to provide address
signals A19-A16 and status bits S6- S6 . The address bits are separated from the
MODE: status bits using the ALE signals. The status bit S6 is always a logic 0, bit S5
indicates the condition of the interrupt flag bit. The S4 and S3 indicate which
segment register is presently being used for memory access.
S4 S3 Type of Segment Register

Used
0 0 Extra segment
0 1 Stack segment
1 0 Code segment
1 1 Data Segment
5
• (BHE)’ /S7 The bus high enable (BHE) signal is used to indicate the
COMMON transfer of data over the higher order D15- D8 data bus. It goes low for
the data transfer over D15- D8 and is used to derive chip select of odd
SIGNALS FOR address memory bank or peripherals.
BOTH MINIMUM
MODE AND (BHE)’ A0 Indication
MAXIMUM
0 0 Whole word
0 1 Upper byte from or to odd
MODE: address
1 0 Lower byte from or to even
address
1 1 None
RD’ : Read: whenever the read signal is at logic 0, the data bus receives the data from
the memory or I/O devices connected to the system
READY: This is the acknowledgement from the slow devices or memory that they have
completed the data transfer operation. This signal is active high.
• INTR: Interrupt Request: Interrupt request is used to request6
a hardware interrupt of INTR is held high when interrupt
COMMON enable flag is set, the 8086 enters an interrupt
SIGNALS FOR acknowledgement cycle after the current instruction has
BOTH MINIMUM completed its execution.
MODE AND
MAXIMUM • TEST’ : This input is tested by “WAIT” instruction. If the
MODE: TEST input goes low; execution will continue. Else the
processor remains in an idle state.
• NMI- Non-maskable Interrupt: The non-maskable interrupt

input is similar to INTR except that the NMI interrupt does
not check for interrupt enable flag is at logic 1, i.e, NMI is
not maskable internally by software. If NMI is activated,
the interrupt input uses interrupt vector 2.
• RESET: The reset input causes the microprocessor to reset
itself. When 8086 reset, it restarts the execution from 7
memory location FFFF0H. The reset signal is active high

COMMON
and must be active for at least four clock cycles.
SIGNALS FOR
BOTH MINIMUM • CLK: Clock input: The clock input signal provides the basic
MODE AND timing input signal for processor and bus control operation.
MAXIMUM It is asymmetric square wave with 33% duty cycle.
MODE: • VCC (+5V): Power supply for the operation of the internal
circuit
• GND: Ground for the internal circuit
• MN/ MX’ : The minimum/maximum mode signal to select

the mode of operation either in minimum or maximum
mode configuration. Logic 1 indicates minimum mode.
• M /IO’ - Memory/IO (M/IO’) signal selects either
MINIMUM MODE memory operation or I/O operation. This line 8
SIGNALS: indicates that the microprocessor address bus

SIGNALS ARE contains either a memory address or an I/O port
FOR MINIMUM address. Signal high at this pin indicates a memory
MODE operation.
OPERATION OF • INTA’- Interrupt acknowledge: The interrupt
8086. acknowledge signal is a response to the INTR input
signal. The INTA signal is normally used to gate
the interrupt vector number onto the data bus in
response to an interrupt request.
• ALE- Address Latch Enable: This output signal
indicates the availability of valid address on the
address/data bus, and is connected to latch enable
input of latches.
MINIMUM MODE • DT/R’ : Data transmit/Receive’: This output signal is used 9
to decide the direction of date flow through the bidirectional
SIGNALS:
buffer. DT/R’= 1, Indicates transmitting and DT/R’= 0 ,
SIGNALS ARE indicates receiving the data.
FOR MINIMUM • DEN’: Data Enable: Data bus enable signal indicates the
MODE availability of valid data over the address/data lines.
OPERATION OF • 𝑊𝑅’ Write: whenever the write signal is at logic 0, the
8086. data bus transmits the data to the memory or I/O devices
connected to the system.
• HOLD: The hold input request a direct memory access
(DMA). If the hold signal is at logic 1, the micro process
stops its normal execution and places its address, data and
control bus at the high impedance state.
• HLDA: Hold acknowledgement indicates that 8086
has entered into the hold state.
• S2’ S1’ S0’ - Status lines: These are the status lines
MAXIMUM that reflect the type of operation being carried out 10
MODE SIGNAL: by the processor. These status lines are encoded as

SIGNALS ARE follows:
FOR MAXIMUM
MODE
OPERATION OF
8086.
• LOCK : The lock output is used to lock peripherals off the

system, i.e, the other system bus masters will be prevented
from gaining the system bus.
• QS1 and QS0 - Queue status: The queue status bits shows
MAXIMUM the status of the internal instruction queue. The encoding of 11
MODE SIGNAL: these signals is as follows
SIGNALS ARE
FOR MAXIMUM
MODE
OPERATION OF
8086.
• RQ1/GT1 and RQ0/GT0- Request/Grant: The request/grant
pins are used by other local bus masters to force the
processor to release the local bus at the end of the
processors current bus cycle. These lines are bidirectional
and are used to both request and grant a DMA operation.
RQ0/GT0 is having higher priority than RQ1/GT1
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PINOUTS OF 8086

• This microprocessor operates in • The 8086 signals are

S4 S3 Type of Segment Register

• NMI- Non-maskable Interrupt: The non-maskable interrupt

memory location FFFF0H. The reset signal is active high

• GND: Ground for the internal circuit

• MN/ MX’ : The minimum/maximum mode signal to select

SIGNALS: indicates that the microprocessor address bus

MODE SIGNAL: by the processor. These status lines are encoded as

• LOCK : The lock output is used to lock peripherals off the

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