Scribd Logo
Upload

Welcome to Scribd!

  • 10 views

    Xilinx xc4000 & Altera'S Flex 8000/10000 FPGA

    Uploaded by

    kumarkankipati19
    The document provides information about the Xilinx xc4000 and Altera's FLEX 8000/10000 FPGA families. It describes the basic structures and features of each, including logic blocks, interconnect structures, and capacity ranges. For the xc4000, it discusses configurable logic blocks (CLBs) containing lookup tables (LUTs) and flip-flops. For FLEX 8000/10000, it describes logic elements (LEs) containing LUTs, flip-flops, and carry logic, grouped into logic array blocks connected by long, predictable interconnect lines.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Xilinx xc4000 & Altera'S Flex 8000/10000 FPGA

    Uploaded by

    kumarkankipati19
    10 views17 pages
    The document provides information about the Xilinx xc4000 and Altera's FLEX 8000/10000 FPGA families. It describes the basic structures and features of each, including logic blocks, interconnect structures, and capacity ranges. For the xc4000, it discusses configurable logic blocks (CLBs) containing lookup tables (LUTs) and flip-flops. For FLEX 8000/10000, it describes logic elements (LEs) containing LUTs, flip-flops, and carry logic, grouped into logic array blocks connected by long, predictable interconnect lines.

    Original Description:

    Original Title

    Presentation (1) (1)

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document provides information about the Xilinx xc4000 and Altera's FLEX 8000/10000 FPGA families. It describes the basic structures and features of each, including logic blocks, interconnect structures, and capacity ranges. For the xc4000, it discusses configurable logic blocks (CLBs) containing lookup tables (LUTs) and flip-flops. For FLEX 8000/10000, it describes logic elements (LEs) containing LUTs, flip-flops, and carry logic, grouped into logic array blocks connected by long, predictable interconnect lines.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    10 views17 pages

    Xilinx xc4000 & Altera'S Flex 8000/10000 FPGA

    Uploaded by

    kumarkankipati19
    The document provides information about the Xilinx xc4000 and Altera's FLEX 8000/10000 FPGA families. It describes the basic structures and features of each, including logic blocks, interconnect structures, and capacity ranges. For the xc4000, it discusses configurable logic blocks (CLBs) containing lookup tables (LUTs) and flip-flops. For FLEX 8000/10000, it describes logic elements (LEs) containing LUTs, flip-flops, and carry logic, grouped into logic array blocks connected by long, predictable interconnect lines.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 17

    Xilinx xc4000 &

    ALTERA’s FLEX
    8000/10000 FPGA
    Xilinx xc4000 :
    • The basic structure of Xilinx FPGAs is array-based, meaning that each chip
    comprises a twodimensional array of logic blocks that can be
    interconnected via horizontal and vertical routing channels.
    • Xilinx introduced the first FPGA family, called the XC2000 series, in about
    1985 and now offers three more generations: XC3000, XC4000, and XC5000.
    • Although the XC3000 devices are still widely used, we will focus on the
    more recent and more popular XC4000 family.
    • We note that XC5000 is similar to XC4000, but has been engineered to offer
    similar features at a more attractive price, with some penalty in speed.
    • We should also note that Xilinx has recently introduced an FPGA family
    based on anti-fuses, called the XC8100.
    • The XC8100 has many interesting features, but since it is not yet in
    widespread.
    • The Xilinx 4000 family devices range in capacity from about 2000 to
    more than 15,000 equivalent gates.
    • The XC4000 features a logic block (called a Configurable Logic Block
    (CLB) by Xilinx) that is based on look-up tables (LUTs).
    • A LUT is a small one bit wide memory array, where the address lines
    for the memory are inputs of the logic block and the one bit output
    from the memory is the LUT output.
    • A LUT with K inputs would then correspond to a 2K x 1 bit memory,
    output realize any logic function of its K inputs by programming the
    logic function’s truth table directly into the memory.
    • The XC4000 CLB contains three separate LUTs.
    • There are two 4-input LUTS that are fed by CLB inputs, and the third
    LUT can be used in combination with the other two.
    • This arrangement allows the CLB to implement a wide range of logic
    functions of up to nine inputs, two separate functions of four inputs
    or other possibilities.
    • Each CLB also contains two flip-flops.
    • Toward the goal of providing high density devices that support the
    integration of entire systems, the XC4000 chips have “system
    oriented” features.
    • For instance, each CLB contains circuitry that allows it to efficiently
    perform arithmetic (i.e., a circuit that can implement a fast carry
    operation for adder-like circuits) and also the LUTs in a CLB can be
    configured as read/write RAM cells.
    • A new version of this family, the 4000E, has the additional feature
    that the RAM can be configured as a dual port RAM with a single
    write and two read ports.
    • In the 4000ports RAM blocks can be synchronous RAM.
    • Also, each XC4000 chip includes very wide AND-planes around the
    periphery of the logic block array to facilitate implementing circuit
    blocks such as wide decoders.
    • Besides logic, the other key feature that characterizes an FPGA is its
    interconnect structure.
    • The XC4000 interconnect is arranged in horizontal and vertical
    channels.
    • Each channel contains some number of short wire segments that
    span a single CLB (the number of segments in each channel depends
    on the specific part number), longer segments that span two CLBs,
    and very long segments that span the entire length or width of the
    chip.
    • Programmable switches are available (see Figure 5) to connect the
    inputs and outputs of the CLBs to the wire segments, or to connect
    one wire segment to another.
    • The figure shows only the wire segments in a horizontal channel, and
    does not show the vertical routing channels, the CLB inputs and
    outputs, or the routing switches.
    • An important point worth noting about the Xilinx interconnect is that
    signals must pass through switches to reach one CLB from another,
    and the total number of switches traversed depends on the particular
    set of wire segments used.
    • Thus, speed-performance of an implemented circuit depends in part
    on how the wire segments are allocated to individual signals by CAD
    tools.
    Flex 8000/10000 FPGA :
    • Altera’s FLEX 8000 series consists of a three-level hierarchy much like that found in CPLDs.
    • However, the lowest level of the hierarchy consists of a set of lookup tables, rather than
    an SPLDlike block, and so the FLEX 8000 is categorized here as an FPGA.
    • It should be noted, however, that FLEX 8000 is a combination of FPGA and CPLD
    technologies.
    • FLEX 8000 is SRAM-based and features a four-input LUT as its basic logic block.
    • Logic capacity ranges from about 4000 gates to more than 15,000 for the 8000 series.
    • The overall architecture of FLEX 8000 is illustrated in Figure 20.
    • The basic logic block, called a Logic Element (LE) contains a four-input LUT, a flip-flop, and
    special-purpose carry circuitry for arithmetic circuits (similar to Xilinx XC4000).
    • The LE also includes cascade circuitry that allows for efficient implementation of wide
    AND functions.
    • In the FLEX 8000, LEs are grouped into sets of 8, called Logic Array Blocks (LABs, a
    term borrowed from Altera’s CPLDs).
    • Each LAB contains local interconnect and each local wire can connect LE to any other
    LE with in the same LAB.
    • Local interconnect also connects to the FLEX 8000’s global interconnect, called
    FastTrack.
    • FastTrack is similar to Xilinx long lines in that each FastTrack wire extends the full
    width or height of the device.
    • However, a major difference between FLEX 8000 and Xilinx chips is that FastTrack
    consists of only long lines.
    • This makes the FLEX 8000 easy for CAD tools to automatically configure.
    • All FastTrack wires horizontal wires are identical, and so interconnect delays in the
    FLEX 8000configure predictable than FPGAs that employ many smaller length
    segments because there are fewer programmable switches in the longer paths.
    • Predictability is furthered aided by the fact that connections between horizontal and
    vertical lines pass through active buffers.
    • The FLEX 8000 architecture has been extended in the state-of-the-art FLEX
    10000 family.
    • FLEX 10000 offers all of the features of FLEX 8000, with the addition of
    variable-sized blocks of SRAM, called Embedded Array Blocks (EABs).
    • This idea is illustrated in Figure 23, which shows that each row in a FLEX 10000
    chip has an EAB on one end.
    • Each EAB is configurable to serve as an SRAM block with a variable aspect
    ratio: 256 x 8, 512 x 4, 1K x 2, or 2K x 1.
    • In addition, an EAB can alternatively be configured to implement a complex
    logic circuit, such as a multiplier, by employing it as a large multi-output lookup
    table.
    • Altera provides, as part of their CAD tools, several macro-functions that
    implement useful logic circuits in EABs.
    • Counting the EABs as logic gates, FLEX 10000 offers the highest logic capacity
    of any FPGA, although it is hard to provide an accurate number.

    You might also like