Advanced Microprocessor
Advanced Microprocessor
Advanced Microprocessor
Unit – 5
ADVANCED MICROPROCESSORS
What is microprocessor?
Introduced in 1993
Similar to 80386 but with 64 bit data bus
memory size is 4 gb
• CD cache disable controls the internal cache. If CD=1 ,
the cache will not fill with new data . If CD=0 misses
will cause the cache to fill with new data
• NW Not write through selects the mode of operation
for the data cache. If NW=1, the data cache is inhibited
from cache write though
• AM Alignment mask enables alignment checking when
set, it only occurs for protected mode
• WP write protect protects user level pages against
supervisor level write operations. When WP=1, the
supervisor can write to user level segments
• NE numeric error enables standard numeric
coprocessor error detection.
Intel Pentium Pro
Introduction
•Pipeline is divided in 3 sections. Fetch and decode
unit, dispatch and execution unit and retire unit.
•Intel Pentium Pro microprocessor takes Cisc
instructions and converts them into Risc micro-
operations.
Internal Structure Of Pentium Pro
Internal Structure Of Pentium Pro
•The system bus connects to L2 cache.
•BIU controls system bus access via L2 cache.
•L2 cache is integrated in Intel Pentium Pro.
•BIU generates control signals and memory address.
•BIU fetches or passes data or instruction via L1 cache.
•The IFDU can decode three instructions
simultaneously, and passes it to instruction pool.
•The IFDU has branch prediction logic.
•The DEU then executes the instructions.
• DEU contains three execution units. Two for
processing integer instruction and one for
processing floating point instruction
simultaneously.
• Lastly RU checks the instruction pool and removes
decoded instructions that have been executed.
• RU can remove three decoded instructions per
clock pulse.
Drawbacks of Intel Pentium Pro Microprocessor
•As Intel Pentium Pro uses RISC approach the first
drawback is converting instructions from CISC to
RISC. It takes time to do so.
•So Pentium pro inevitably takes performance hit
when processing instructions.
•Second is that out of order design can be
particularly affected by 16 bit code resulting in
eventual stop of process.
•ECC scheme causes additional cost of SDRAM that is
72 bits wide.
Differences Between Intel Pentium and
Intel Pentium Pro
•Level-2 cache is integrated in Intel Pentium Pro and
not in Pentium microprocessor. This speeds up
processing and reduces number of components.
•In Pentium unified cache holds both instructions
and data, but in Pentium Pro separate cache is used
for instruction and data which speeds up
performance.
•Pentium microprocessor doesn’t have jump
execution unit or address generation unit as Pentium
Pro has. It’s one of the major changes.