FPGA Roadmap - 2019
FPGA Roadmap - 2019
FPGA Roadmap - 2019
Kaj Rosengren
FPGA Designer – Beam Diagnostics
www.europeanspallationsource.se
1 August 2024
Agenda
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FPGA Roadmap - 2018
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FPGA Roadmap - 2018
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FPGA Developers forum
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FPGA Roadmap - 2018
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AXI FPGA Framework
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AXI FPGA Framework – SIS8300
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AXI FPGA Framework – Register Map
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AXI FPGA Framework – Register map
passed_tests = board_under_test.test_registers_after_reset()
board_under_test["BSP_CLK_DISTR_MUX"]["CLK_SEL"].write(0x0)
• Has worked pretty flawlessly.
• But there are a lot of features that we could use to improve
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AXI FPGA Framework – Register map
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AXI FPGA Framework – SIS8300
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Struck SIS8160
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AXI FPGA framework – sis8160
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AXI FPGA framework – sis8160
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AXI FPGA framework – sis8160
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AXI framework – IFC1410 (suggestion)
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AXI FPGA Framework – IFC1410
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FPGA Roadmap - 2018
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Verification topics from last roadmap
Simulation
• Evaluate the simulator situation.
– FPGA Forum has decided to get more Questa licenses
• Ability to run regressions.
• TB templates – How-to deal with System models and golden references
• Assertions (PSL or SystemVerilog) – could at least be used for simulation
of standard interfaces.
– Neither of these topics have gotten any attention yet
• ”top-level” test benches – would be nice to have
– Xilinx DMA solution comes with example testbench. So we now have chip-level
testbenches for sis8300/8160
– Currently its only used for sanity checks. On questasim testbench runs fine, on
Vivado simulator terribly slow.
– Could quite easily generate register test from python. Not a priority though.
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FPGA Roadmap - 2018
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Reminder – normal PV procesing
• The ”Normal” case is that the IOC clients are updating small
PV:s with heavily processed items or shorter waveforms
• But we do acquire a lot more data than this and it would be
very useful to have it available for analysis.
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Reminder – Data-on-demand
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Current status
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Data-on-demand – EPICS layer
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Data-on-demand - Timestamping
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FPGA roadmap - 2019
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FPGA Systems roadmap
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BPM Firmware status
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BPM Firmware
• Based on BPM firmware from Fredrik Kristensen, the firmware itself its
inherited from LLRF.
– Firmware was basically “duct taped” into the demo firmware from Struck.
– The processed data channels where interleaved into the default Struck output channels.
– The main problem with the firmware version is that parsing the waveforms and
publishing on PVs consumes a lot of CPU.
• Development started last autumn, main items to fix
– Port to ESS FPGA framework (IQ sampling in framework)
– Waveform channels with data conversion, gain/offset correction, decimation.
– Averaging of region-of-interest within waveform for pulse X/Y/PHASE/MAG
• Some late changes
– Add second reference line.
– Change the back-plane trigger selection to be more flexible.
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BPM Firmware overview
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BPM Firmware - components
• Goal is to have components that ”plugs” somewhat simply into the framework.
- Register bank generated from scripts, note that the current version has a “Struck” version
- Components can be added in BD, register banks connected with AXI-lite interconnect (and decoding).
More investigation needed to how we handle this in the register bank scripts.
- Components can be identified through registers. Version, which features are enabled etc.
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BPM firmware – components
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Closing
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Thank you!
• Questions?
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