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DOM Rev3 Block Diagram

easy to learn

Uploaded by

Jemima A
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11 views2 pages

DOM Rev3 Block Diagram

easy to learn

Uploaded by

Jemima A
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
Download as ppt, pdf, or txt
Download as ppt, pdf, or txt
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Digital Optical Module Block Diagram

Trigger (2) 10b


Pulser
FPGA ADC
1 megabaud

1 5
Delay x16 and 8b
DOR
DAC
4 8

x2
ATWD
10b
SOPC LPF
+/-5V, 3.3V,
x0.25
ATWD
10b 2.5V, 1.8V DC-DC
x 2.6 x 9

fADC
10b
CPU Configuration 8Mbit

MUX
Device
40 MHz DP
OB-LED
Ram 32b
SDRAM 16Mb

(n+1) 16Mb
(n–1) LC SDRAM
20 MHz

16b Flash Flash


Oscillator Monitor CPLD 4Mb 4Mb
Corning Frequency & Control
Ctl
DACs & ADCs
8b Flasher 64 Bytes
(was Toyocom)
8b, 10b, 12b
PMT Power Board

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