Digital Integrated Circuits: A Design Perspective

EE141 Digital Integrated Circuits
2nd
Combinational Circuits
1
Digital Integrated
Circuits
A Design Perspective
Designing Combinational
Logic Circuits
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikoli
November 2002.
2nd
2
Combinational vs. Sequential Logic
Combinational Sequential
Output = f ( In )
Output = f ( In, Previous In )
Combinational
Logic
Circuit
Out In
Combinational
Logic
Circuit
Out
In
State
2nd
3
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
V
DD
or V
ss
via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
2nd
4
Static Complementary CMOS
V
DD

F(In1,In2,InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
2nd
5
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X
Y
A
B
Y = X if A OR B
NMOS Transistors pass a strong 0 but a weak 1
2nd
6
PMOS Transistors
in Series/Parallel Connection
X
Y
A B
Y = X if A AND B = A + B
X
Y
A
B
Y = X if A OR B = AB
PMOS Transistors pass a strong 1 but a weak 0
PMOS switch closes when switch control input is low
2nd
7
Threshold Drops
V
DD

V
DD
0 PDN
0 V
DD

C
L

C
L

PUN
V
DD

0 V
DD
- V
Tn

C
L

V
DD

V
DD

V
DD
|V
Tp
|
C
L

S
D S
D
V
GS

S
S D
D
V
GS

2nd
8
Complementary CMOS Logic Style
2nd
9
Example Gate: NAND
2nd
10
Example Gate: NOR
2nd
11
Complex CMOS Gate
OUT = D + A (B + C)
D
A
B C
D
A
B
C
2nd
12
Constructing a Complex Gate
C
(a) pull-down network
SN1
SN4
SN2
SN3
D
F
F
A
D
B
C
D
F
A
B
C
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
D
A
A
B
C
V
DD
V
DD
B
(c) complete gate
2nd
13
Cell Design
Standard Cells
General purpose logic
Can be synthesized
Same height, varying width
Datapath Cells
For regular, structured designs (arithmetic)
Includes some wiring in the cell
Fixed height and width
2nd
14
Standard Cell Layout Methodology
1980s
signals
Routing
channel
V
DD
GND
2nd
15
Standard Cell Layout Methodology
1990s
M2
No Routing
channels
V
DD
GND
M3
V
DD
GND
Mirrored Cell
Mirrored Cell
2nd
16
Standard Cells
Cell boundary
N Well
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects

Cell height is 12 pitch
2
Rails ~10
In
Out
V
DD
GND
2nd
17
Standard Cells
In
Out
V
DD
GND
In Out
V
DD
GND
With silicided
diffusion
With minimal
diffusion
routing
Out In
V
DD
M
2
M
1
2nd
18
Standard Cells
A
Out
V
DD
GND
B
2-input NAND gate
B
V
DD
A
2nd
19
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
In
Out
V
DD
GND
Inverter
A
Out
V
DD
GND
B
NAND2
2nd
20
Stick Diagrams
C
A B
X = C (A + B)
B
A
C
i
j
j
V
DD X
X
i
GND
A B
C
PUN
PDN
A
B
C
Logic Graph
2nd
21
Two Versions of C (A + B)
X
C A B A B C
X
V
DD
GND
V
DD
GND
2nd
22
Consistent Euler Path
j
V
DD X
X
i
GND
A B
C
A B C
2nd
23
OAI22 Logic Graph
C
A B
X = (A+B)(C+D)
B
A
D
V
DD X
X
GND
A B
C
PUN
PDN
C
D
D
A
B
C
D
2nd
24
Example: x = ab+cd
GND
x
a
b
c
d
V
DD x
GND
x
a
b
c
d
V
DD x
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
a c d
x
V
DD
GND
(c) stick diagram for ordering {a b c d}
b
2nd
25
Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
2nd
26
Properties of Complementary CMOS Gates
Snapshot
High noise margins :
V
OH
and V
OL
are at V
DD
and GND , respectively.
No static power consumption :
There never exists a direct path between V
DD
and
V
SS
( GND ) in steady-state mode .
Comparable rise and fall times:
(under appropriate sizing conditions)
2nd
27
CMOS Properties
Full rail-to-rail swing; high noise margins
Logic levels not dependent upon the relative
device sizes; ratioless
Always a path to Vdd or Gnd in steady state;
low output impedance
Extremely high input resistance; nearly zero
steady-state input current
No direct path steady state between power
and ground; no static power dissipation
Propagation delay function of load
capacitance and resistance of transistors
2nd
28
Switch Delay Model
A
R
eq

A
R
p

A
R
p

A
R
n

C
L

A
C
L

B
R
n

A
R
p

B
R
p

A
R
n

C
int

B
R
p

A
R
p

A
R
n

B
R
n

C
L

C
int

NAND2
INV
NOR2
2nd
29
Input Pattern Effects on Delay
Delay is dependent on
the pattern of inputs
Low to high transition
both inputs go low
delay is 0.69 R
p
/2 C
L
one input goes low
delay is 0.69 R
p
C
L
High to low transition
both inputs go high
delay is 0.69 2R
n
C
L
C
L

B
R
n

A
R
p

B
R
p

A
R
n

C
int

2nd
30
Delay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=10
A=1, B=10
A=1 0, B=1
time [ps]
V
o
l
t
a
g
e

[
V
]

Input Data
Pattern
Delay
(psec)
A=B=01 67
A=1, B=01 64
A= 01, B=1 61
A=B=10 45
A=1, B=10 80
A= 10, B=1 81
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
C
L
= 100 fF
2nd
31
Transistor Sizing

C
L

B
R
n

A
R
p

B
R
p

A
R
n

C
int

B
R
p

A
R
p

A
R
n

B
R
n

C
L

C
int

2

2
2 2
1
1
4

4
2nd
32
Transistor Sizing a Complex
CMOS Gate
OUT = D + A (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
2nd
33
Fan-In Considerations
D C B A
D
C
B
A
C
L

C
3

C
2

C
1

Distributed RC model
(Elmore delay)

t
pHL
= 0.69 R
eqn
(C
1
+2C
2
+3C
3
+4C
L
)

Propagation delay deteriorates
rapidly as a function of fan-in
quadratically in the worst case.
2nd
34
t
p
as a Function of Fan-In
t
pL
H

t
p

(
p
s
e
c
)

fan-in
Gates with a
fan-in
greater than
4 should be
avoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
t
pH
L

quadratic
linear
t
p

2nd
35
t
p
as a Function of Fan-Out
2 4 6 8 10 12 14 16
t
p
NOR2
t
p

(
p
s
e
c
)

eff. fan-out
All gates
have the
same drive
current.
t
p
NAND2
t
p
INV
Slope is a
function of
driving
strength
2nd
36
t
p
as a Function of Fan-In and Fan-Out
Fan-in: quadratic due to increasing
resistance and capacitance
Fan-out: each additional fan-out gate
adds two gate capacitances to C
L

t
p
= a
1
FI + a
2
FI
2
+ a
3
FO
2nd
37
Fast Complex Gates:
Design Technique 1
Transistor sizing
as long as fan-out capacitance dominates
Progressive sizing
In
N C
L

C
3

C
2

C
1

In
1
In
2
In
3
M1

M2

M3

MN

Distributed RC line

M1 > M2 > M3 > > MN
(the fet closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
2nd
38
Fast Complex Gates:
Design Technique 2
Transistor ordering
C
2

C
1

In
1
In
2
In
3
M1

M2

M3

C
L

C
2

C
1

In
3
In
2
In
1
M1

M2

M3

C
L

critical path critical path
charged
1
01
charged
charged
1
delay determined by time to
discharge C
L
, C
1
and C
2
delay determined by time to
discharge C
L
1
1
01
charged
discharged
discharged
2nd
39
Fast Complex Gates:
Design Technique 3
Alternative logic structures
F = ABCDEFGH
2nd
40
Fast Complex Gates:
Design Technique 4
Isolating fan-in from fan-out using buffer
insertion
C
L

C
L

2nd
41
Fast Complex Gates:
Design Technique 5
Reducing the voltage swing

linear reduction in delay
also reduces power consumption
But the following gate is much slower!
Or requires use of sense amplifiers on the
receiving end to restore the signal level
(memory design)
t
pHL
= 0.69 (3/4 (C
L
V
DD
)/ I
DSATn
)

= 0.69 (3/4 (C
L
V
swing
)/ I
DSATn
)
2nd
42
Sizing Logic Paths for Speed
Frequently, input capacitance of a logic path
is constrained
Logic also has to drive some capacitance
Example: ALU load in an Intels
microprocessor is 0.5pF
How do we size the ALU datapath to achieve
maximum speed?
We have already solved this for the inverter
chain can we generalize it for any type of
logic?
2nd
43
Buffer Example
( )
=
+ =
N
i
i i i
f g p Delay
1
For given N: C
i+1
/C
i
= C
i
/C
i-1
To find N: C
i+1
/C
i
~ 4
How to generalize this to any logic path?
C
L
In Out
1 2 N
(in units of t
inv
)
2nd
44
Logical Effort
( ) f g p
C
C
C R k Delay
in
L
unit unit
+ =
|
|
.
|
\
|
+ =
t

1
p intrinsic delay (3kR
unit
C
unit
) - gate parameter = f(W)
g logical effort (kR
unit
C
unit
) gate parameter = f(W)
f effective fanout

Normalize everything to an inverter:
g
inv
=1, p
inv
= 1

Divide everything by t
inv
(everything is measured in unit delays t
inv
)
Assume = 1.
2nd
45
Delay in a Logic Gate
Gate delay:
d = h + p
effort delay intrinsic delay
Effort delay:
h = g f
logical
effort
effective fanout =
C
out
/C
in
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
2nd
46
Logical Effort
Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
Logical effort increases with the gate
complexity
2nd
47
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
g = 1
g = 4/3 g = 5/3
B
A
A B
F
V
DD
V
DD
A B
A
B
F
V
DD
A
A
F
1
2 2 2
2
2
1 1
4
4
Inverter 2-input NAND 2-input NOR
2nd
48
Logical Effort of Gates
Fan-out (h)

N
o
r
m
a
l
i
z
e
d

d
e
l
a
y

(
d
)

t
1 2 3 4 5 6 7
pINV
t
pNAND
F(Fan-in)
g =
p =
d =
g =
p =
d =
2nd
49
Fan-out (h)

N
o
r
m
a
l
i
z
e
d

d
e
l
a
y

(
d
)

t
1 2 3 4 5 6 7
pINV
t
pNAND
F(Fan-in)
g = 1
p = 1
d = h+1
g = 4/3
p = 2
d = (4/3)h+2
2nd
50
Intrinsic
Delay
Effort
Delay
1 2 3 4 5
Fanout f
1
2
3
4
5
I
n
v
e
r
t
e
r
:
g

=

1
;
p

=

1
2
-
i
n
p
u
t

N
A
N
D
:
g

=

4
/
3
;
p

=

2
N
o
r
m
a
l
i
z
e
d

D
e
l
a
y
2nd
51
Add Branching Effort
Branching effort:
path on
path off path on
C
C C
b

+
=
2nd
52
Multistage Networks
Stage effort: h
i
= g
i
f
i
Path electrical effort: F = C
out
/C
in
Path logical effort: G = g
1
g
2
g
N
Branching effort: B = b
1
b
2
b
N
Path effort: H = GFB
Path delay D = Ed
i
= Ep
i
+ Eh
i
( )
=
+ =
N
i
i i i
f g p Delay
1
2nd
53
Optimum Effort per Stage
H h
N
=
When each stage bears the same effort:
N
H h =
( ) P NH p f g D
N
i i i
+ = + =
/ 1
Minimum path delay

Effective fanout of each stage:
i i
g h f =
Stage efforts: g
1
f
1
= g
2
f
2
= = g
N
f
N
2nd
54
Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
inv
N
Np NH D + =
/ 1
( ) 0 ln
/ 1 / 1 / 1
= + + =
c
c
inv
N N N
p H H H
N
D
N
H h
/ 1
= Substitute best stage effort
2nd
55
Logical Effort
From Sutherland, Sproull
2nd
56
Example: Optimize Path
Effective fanout, F =
G =
H =
h =
a =
b =
1
a
b
c
5
g = 1
f = a
g = 5/3
f = b/a
g = 5/3
f = c/b
g = 1
f = 5/c
2nd
57
1
a
b
c
5
g = 1
f = a
g = 5/3
f = b/a
g = 5/3
f = c/b
g = 1
f = 5/c
Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g
2
= 2.23
c = hb/g
3
= 5g
4
/f = 2.59
2nd
58

1
a
b c
5
Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g
2
= 2.23
c = fb/g
3
= 5g
4
/f = 2.59
g
1
= 1 g
2
= 5/3 g
3
= 5/3
g
4
= 1
2nd
59
Example 8-input AND
2nd
60
Method of Logical Effort
Compute the path effort: F = GBH
Find the best number of stages N ~ log
4
F
Compute the stage effort f = F
1/N
Sketch the path with this number of stages
Work either from either end, find sizes:
C
in
= C
out
*g/f

Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.
2nd
61
Summary
Sutherland,
Sproull
Harris
2nd
62
Ratioed Logic
2nd
63
Ratioed Logic
V
DD
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
V
DD
V
SS
In
1
In
2
In
3
F
V
DD
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Resistive
Depletion
Load
PMOS
Load
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
V
T
< 0
Goal: to reduce the number of devices over complementary CMOS
2nd
64
Ratioed Logic
V
DD
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
Resistive
N transistors + Load
V
OH
= V
DD
V
OL
=
R
PN
R
PN
+ R
L
Assymetrical response
Static power consumption
t
pL
= 0.69 R
L
C
L
2nd
65
Active Loads
V
DD
V
SS
In
1
In
2
In
3
F
V
DD
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Depletion
Load
PMOS
Load
depletion load NMOS pseudo-NMOS
V
T
< 0
2nd
66
Pseudo-NMOS
V
DD
A B C D
F
C
L
V
OH
= V
DD
(similar to complementary CMOS)
k
n
V
DD
V
Tn
( )
V
OL
V
OL
2
2
-------------
\ .
|
| |
k
p
2
------ V
DD
V
Tp
( )
2
=
V
OL
V
DD
V
T
( )
1 1
k
p
k
n
------ (assuming that V
T
V
Tn
V
Tp
) = = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
2nd
67
Pseudo-NMOS VTC
0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
in
[V]
V
o

u
t

[
V
]

W/L
p
= 4
W/L
p
= 2
W/L
p
= 1
W/L
p
= 0.25
W/L
p
= 0.5
2nd
68
Improved Loads
A B C D
F
C
L
M1
M2
M1 >> M2
Enable
V
DD
Adaptive Load
2nd
69
Improved Loads (2)
V
DD
V
SS
PDN1
Out
V
DD
V
SS
PDN2
Out
A
A
B
B
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
2nd
70
DCVSL Example
B
A A
B
B B
Out
Out
XOR-NXOR gate
2nd
71
DCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0
-0.5
0.5
1.5
2.5
Time [ns]
V

o
l

t

a

g
e

[
V
]

A B
A B
A,B
A , B
2nd
72
Pass-Transistor
Logic
2nd
73
Pass-Transistor Logic
I
n
p
u
t
s
Switch
Network
Out
Out
A
B
B
B
N transistors
No static consumption
2nd
74
Example: AND Gate
B
B
A
F = AB
0
2nd
75
NMOS-Only Logic
V
DD
In
Out
x
0.5m/0.25m
0.5m/ 0.25m
1.5m/ 0.25m
0 0.5 1 1.5 2
0.0
1.0
2.0
3.0
Time [ns]
V
o
l
t
a
g

e

[
V
]

x
Out
In
2nd
76
NMOS-only Switch
A = 2.5 V
B
C = 2.5 V
C
L
A = 2.5 V
C = 2.5 V
B
M
2
M
1
M
n
Threshold voltage loss causes
static power consumption
V
B
does not pull up to 2.5V, but 2.5V - V
TN
NMOS has higher threshold than PMOS (body effect)
2nd
77
NMOS Only Logic:
Level Restoring Transistor
M
2
M
1
M
n
M
r
Out
A
B
V
DD
V
DD
Level Restorer
X
Advantage: Full Swing
Restorer adds capacitance, takes away pull down current at X
Ratio problem
2nd
78
Restorer Sizing
0 100 200 300 400 500
0.0
1.0
2.0
W / L
r
=1.0/0.25
W / L
r
=1.25/0.25
W / L
r
=1.50/0.25
W / L
r
=1.75/0.25
V
o
l
t
a
g
e

[
V
]

Time [ps]
3.0
Upper limit on restorer size
Pass-transistor pull-down
can have several transistors in
stack
2nd
79
Solution 2: Single Transistor Pass Gate with
V
T
=0
Out
V
DD
V
DD
2.5V
V
DD
0V
2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
2nd
80
Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=AB
F=AB
OR/NOR
EXOR/NEXOR AND/NAND
F
F
Pass-Transistor
Network
Pass-Transistor
Network
A
A
B
B
A
A
B
B
Inverse
(a)
(b)
2nd
81
Solution 3: Transmission Gate
A
B
C
C
A B
C
C
B
C
L
C = 0 V
A = 2.5 V
C = 2.5 V
2nd
82
Resistance of Transmission Gate
V
out
0 V
2.5 V
2. 5 V
R
n
R
p
0.0 1.0 2.0
0
10
20
30
V
out
, V
R
e
s
i
s
t
a
n
c
e
,

o
h
m
s
R
n
R
p
R
n
|| R
p
2nd
83
Pass-Transistor Based Multiplexer
A
M2
M1
B
S
S
S
F
VDD
GND
V
DD

In
1
In
2
S S
S
S
2nd
84
Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
2nd
85
Delay in Transmission Gate Networks
V
1 V
i-1
C
2.5 2.5
0 0
V
i V
i+1
C
C
2.5
0
V
n-1 V
n
C
C
2.5
0
In
V
1
V
i V
i+1
C
V
n-1 V
n
C
C
In
R
eq
R
eq
R
eq
R
eq
C C
(a)
(b)
C
R
eq
R
eq
C C
R
eq
C C
R
eq
R
eq
C C
R
eq
C
In
m
(c)
2nd
86
Delay Optimization
2nd
87
Transmission Gate Full Adder
A
B
P
C
i
V
DD
A
A A
V
DD
C
i
A
P
A
B
V
DD
V
DD
C
i
C
i
C
o
S
C
i
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry
2nd
88
Dynamic Logic
2nd
89
Dynamic CMOS
In static circuits at every point in time (except
when switching) the output is connected to
either GND or V
DD
via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type)
transistors
2nd
91
Dynamic Gate
In
1
In
2
PDN

In
3
M
e
M
p
Clk

Clk

Out

C
L
Out

Clk

Clk

A

B

C

M
p
M
e
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)

on

off

1

off

on

((AB)+C)

2nd
92
Conditions on Output
Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.

Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on C
L
2nd
93
Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (V
OL
= GND and V
OH
= V
DD
)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (C
in
)
reduced load capacitance due to smaller output loading (Cout)
no I
sc
, so all the current provided by PDN goes into discharging C
L
2nd
94
Properties of Dynamic Gates
Overall power dissipation usually higher than static
CMOS
no static current path ever exists between V
DD
and GND
(including P
sc
)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed V
Tn
, so V
M
, V
IH
and V
IL
equal to V
Tn

low noise margin (NM
L
)
Needs a precharge/evaluate clock
2nd
95
Issues in Dynamic Design 1:
Charge Leakage
C
L
Clk

Clk

Out

A

M
p
M
e
Leakage sources

CLK

V
Out
Precharge

Evaluate

Dominant component is subthreshold current
2nd
96
Solution to Charge Leakage
C
L
Clk

Clk

M
e
M
p
A

B

Out

M
kp
Same approach as level restorer for pass-transistor logic

Keeper

2nd
97
Charge Sharing
C
L
Clk

Clk

C
A
C
B
B=0

A

Out

M
p
M
e
Charge stored originally on
C
L
is redistributed (shared)
over C
L
and C
A
leading to
reduced robustness
2nd
98
Charge Sharing Example
C
L
=50fF
Clk

Clk

A

A

B
B
B

!B

C

C

Out

C
a
=15fF
C
c
=15fF
C
b
=15fF
C
d
=10fF
2nd
99
Charge Sharing
M
p
M
e
V
DD
|
Out
|
A
B = 0
C
L
C
a
C
b
M
a
M
b
X
C
L
V
DD
C
L
V
out
t
( )
C
a
V
DD
V
Tn
V
X
( )
( )
+ =
or
AV
out
V
out
t
( )
V
DD
C
a
C
L
-------- V
DD
V
Tn
V
X
( )
( )
= =
AV
out
V
DD
C
a
C
a
C
L
+
----------------------
\ .
|
| |
=
case 1) if AV
out
< V
Tn
case 2) if AV
out
> V
Tn
B
=
0
Clk
X
C
L
C
a
C
b
A
Out
M
p
M
a
V
DD
M
b
Clk
M
e
2nd
100
Solution to Charge Redistribution
Clk

Clk

M
e
M
p
A

B

Out

M
kp
Clk

Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
2nd
101
Backgate Coupling
C
L1
Clk

Clk

B=0

A=0

Out1

M
p
M
e
Out2

C
L2
In

Dynamic NAND

Static NAND

=1

=0

2nd
102
Backgate Coupling Effect
-1
0
1
2
3
0 2 4 6
Time, ns

Clk

In

Out1

Out2

2nd
103
Issues in Dynamic Design 4: Clock
Feedthrough
C
L
Clk

Clk

B

A

Out

M
p
M
e
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above V
DD
. The fast rising
(and falling edges) of the
clock couple to Out.
2nd
104
Clock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
Clk

Clk

In
1
In
2
In
3
In
4
Out

In &
Clk

Out

Time, ns

Clock feedthrough

Clock feedthrough

2nd
105
Other Effects
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)
2nd
106
Cascading Dynamic Gates
Clk

Clk

Out1

In

M
p
M
e
M
p
M
e
Clk

Clk

Out2

V

t

Clk

In

Out1

Out2

AV

V
Tn
Only 0 1 transitions allowed at inputs!
2nd
107
Domino Logic
In
1
In
2
PDN

In
3
M
e
M
p
Clk

Clk

Out1

In
4
PDN

In
5
M
e
M
p
Clk

Clk

Out2

M
kp
1 1
1 0
0 0
0 1
2nd
108
Why Domino?
Clk

Clk

In
i
PDN

In
j
In
i
In
j
PDN

In
i
PDN

In
j
In
i
PDN

In
j
Like falling dominos!
2nd
109
Properties of Domino Logic
Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition
Input capacitance reduced smaller logical effort

2nd
110
Designing with Domino Logic
M
p
M
e
V
DD
PDN
Clk
In
1
In
2
In
3
Out1
Clk
M
p
M
e
V
DD
PDN
Clk
In
4
Clk
Out2
M
r
V
DD
Inputs = 0
during precharge
Can be eliminated!
2nd
111
Footless Domino
The first gate in the chain needs a foot switch
Precharge is rippling short-circuit current
A solution is to delay the clock for each stage
V
DD
Clk M
p
Out
1
In
1
1 0
V
DD
Clk M
p
Out
2
In
2
V
DD
Clk M
p
Out
n
In
n
In
3
1 0
0 1 0 1 0 1
1 0 1 0
2nd
112
Differential (Dual Rail) Domino
A

B

M
e
M
p
Clk

Clk

Out = AB

!A

!B

M
kp
Clk

Out = AB

M
kp
M
p
Solves the problem of non-inverting logic
1 0

1 0

on

off

2nd
113
np-CMOS
In
1
In
2
PDN

In
3
M
e
M
p
Clk

Clk

Out1

In
4
PUN

In
5
M
e
M
p
Clk

Clk

Out2
(to PDN)

1 1
1 0
0 0
0 1
Only 0 1 transitions allowed at inputs of PDN
Only 1 0 transitions allowed at inputs of PUN
2nd
114
NORA Logic
In
1
In
2
PDN

In
3
M
e
M
p
Clk

Clk

Out1

In
4
PUN

In
5
M
e
M
p
Clk

Clk

Out2
(to PDN)

1 1
1 0
0 0
0 1
to other
PDNs

to other
PUNs

WARNING: Very sensitive to noise!

Digital Integrated Circuits: A Design Perspective

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EE141 Digital Integrated Circuits

Minimum path delay

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