PLA

SYED HASAN SAEED
hasansaeedcontrol@gmail.com
https://shasansaeed.yolasite.com
1
Syed Hasan Saeed, Integral University,
Lucknow

PROGRAMMABLE LOGIC ARRAY
(PLA)
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PROGRAMMABLE LOGIC ARRAY (PLA) :
• The PLA is a programmable logic device with programmable AND
gates followed by programmable OR gates.
• Best suited for the implementation of logic function in SOP form.
• A m x n PLA has m buffer inverters, 2m AND gates and n OR gates
– Inputs are applied to buffer-inverters (Normal and complement both).
– Output of buffer-inverters are connected to the AND matrix.
– Output of AND matrix is connected to the input of OR gate matrix.
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PLA STRUCTURE
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•
•
•
•
•
•
‘m’
input
lines
AND
gate
Array
OR gate
Array
•
•
•
•
•
•
•
•
•
‘n’ output
lines
•
•
•
•
•
•
Input
Buffers
Fig. 1

PROCEDURE FOE IMPLEMENTATION:
• Write the logic function in SOP form.
• Minimize the function
• Decide the input connections of AND matrix for generating the product
terms.
• Decide the input connections of OR matrix for generating the sum of
products.
• Connect the output of OR gates to the invert/non-invert matrix,
depending upon the requirement.
• Program the PLA.
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• BUFFER-INVERTER
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A
A
A A
A
A
A
(TRUE OUTPUT)
(TRUE OUTPUT)
(COMPLEMENTED OUTPUT)
(COMPLEMENTED OUTPUT)
Fig. 2

EXAMPLE 0: A combinational logic is defined by the functions
Implement the circuit with PLA having three inputs, 4 product terms
and two outputs.
(Reference: Digital Design by M. Moris Mano, Michael D. Cilleti)
• Number of inputs = 3 , Number of outputs = 2
• Each input is connected to the buffer-inverter. The buffer-inverter having
both true value and complemented value of output.
• The both output of buffer-inverter is connected to the AND gates.
• The output of AND gates are connected to the inputs of OR gates.
• The output of OR gates are connected to XOR gate.
• When the XOR input is connected to 1 then output will be inverted and if
the input of XOR gate is connected to 0 the output of XOR gate will
remain the same i.e output does not change.
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BC)(ACF
CBACABAF
2
1



• The size of the PLA is specified by the number of inputs, the
number of product terms and the number of outputs.
• PLA Programming Table:
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PRODUCT TERMS
INPUTS
OUTPUTS
(T) (C)
A B C F1 F2
1 1 0 - 1 -
A C 2 1 - 1 1 1
B C 3 - 1 1 - 1
4 0 1 0 1 -
BA
CBA
‘T’stands for TRUE and ‘C’stands for COMPLEMENT

LOGIC DIAGRAM
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A
B
C
CBAACBAF1 
BCACF2 
A
B
C
A
B
C
BA AC
INPUTS
INPUT
BUFFERS
BC CBA
Fig. 3
2F

EXAMPLE -1: A combinational circuit is defined by the following function
F1 (A,B,C)=∑m(4,5,7)
F2 (A,B,C) =∑m(3,5,7)
Implement this circuit with a PLA having 3 inputs, 3 product terms and 2
outputs. Also write the PLA programming table.
SOLUTION:
STEP 1: Write the Boolean Expression in minimum SOP form.
(Note: use minimization technique. Here we use K-map)
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0 0 0 0
1 1 1 0
A
BC
00 01 11 10
0
1
ACBAF1 
0 0 1 0
0 1 1 0
A
00 01 11 10
0
1
BC
BCACF2 

• Number of inputs = 3
• Number of product terms = 4, in which ‘AC’ is common in both
function F1 and F2 , so number of product terms = 3
• Number of AND gates = Number of product terms = 3
• Number of OR gates = Number of outputs = 2
• Logic diagram is shown in fig. 4
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STEP-2 : LOGIC DIAGRAM
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A
B
C
A
B
C
A
B
C
INPUTS
INPUT
BUFFERS

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A
B
C
A
B
C
A
B
C
BA AC BC
INPUTS
INPUT
BUFFERS

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A
B
C
A
B
C
A
B
C
BA AC BC
INPUTS
INPUT
BUFFERS

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A
B
C
ACBAF1 
BCACF2 
A
B
C
A
B
C
BA AC BC
INPUTS
TWO
OUTPUTS
INPUT
BUFFERS
Fig. 4

PLA Programming:
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PRODUCT TERMS
INPUTS OUTPUTS
A B C F1 F2
1 1 0 - 1 -
2 1 - 1 1 1
3 - 1 1 - 1
BA
AC
BC

EXAMPLE 2: A combinational logic is defined by function
F1(A,B,C)=∑m (3,5,6,7)
F2 (A,B,C)=∑m (0,2,4,7)
Implement the circuit with PLA having 3 inputs, 4 product terms and 2
outputs.
SOLUTION: STEP 1: Write the function in minimize SOP form.
(Note:Here we are using K-map)
For F1 FOR F2
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0 0 1 0
0 1 1 1
00 01 11 10
0
1
A BC
CBBACAF1 
1 0 0 1
1 0 1 0
A BC
00 01 11 10
0
1
CACBACBF2 

• There are six product terms in F1 and F2, but only 4 product terms
are allowed to use.
• Now implement
• From the last two equation it is clear that the minterms 0, 2 and 4
are common.
• Obtain the minimized expression by using them.
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C)B,(A,F1
(0,2,4,7)mC)B,(A,FBut
(0,1,2,4)mC)B,(A,F
(3,5,6,7)m),,(F
2
1
1





CBA
1 0 0 1
1 0 0 0
A
BC
00 01 11 10
0
1
CBCA(0,2,4)m 

• Remaining minterms are m(1) = and m(7) =
• Now four product terms are
• are common in both functions.
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CBAC,BA,CB,CA
CB,CA
CBACBCAF
CBACBCAF
2
1


Note: After OR gate for F1 , connect to inverter to get F11F
CBA CBA

LOGIC DIAGRAM
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A
B
C
CBACBCAF1 
CBACBCAF2 
A
B
C
A
B
C
CA
INPUTS
TWO
OUTPUTS
INPUT
BUFFERS
CBA
CB
CBA
Fig. 5

EXAMPLE 3: Implement the circuit with PLA of the following
functions
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(0,2,6,7)mF
CBAACABF
CBACBACBAF
3
2
1



For F3
1 0 0 1
0 0 1 1
A
BC
00 01 11 10
0
1
BACAF3 
Note: In F1 and F2 the third term is common, so one AND gate is
sufficient for third term of both functions. Similarly for F2 and F3 the term
AB is common therefore one AND gate is sufficient.
CBA

Therefore,
Number of AND gates = 6
Number of OR gates = 3
Number of Input Buffers = 3
logic diagram is shown in fig. 6
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LOGIC DIAGRAM
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A
B
C
A
B
C
A
B
C
INPUTS
THREE
OUTPUTS
INPUT
BUFFERS
F1
F2
F3
CBA CBA CBA
A CBA CA
AND
Matrix
OR Matrix
Fig. 6

Example 4: : Implement the circuit with PLA of the following
functions
SOLUTION:
STEP 1: Write the function in minimize SOP form. (Here we are using K-
map)
For F1:
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(0,1,2,4)mC)B,(A,F
(2,3,6,4)mC)B,(A,F
2
1




0 0 1 1
1 0 0 1
A BC
00 01 11 10
0
1
CABAF1 
1 1 0 1
1 0 0 0
00 01 11 10
A BC
0
1
CACBBAF2 
(Integral university, 2018-19)

Number of input buffer-inverters = 3
Number of product terms = 5
Number of AND gates = 5
Number of Or gates = 2
Logic diagram is shown in fig. 7
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LOGIC DIAGRAM
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A
B
C
A
B
C
A
B
C
INPUTS
TWO
OUTPUTS
INPUT
BUFFERS
F1
F2
BA CA
BA CB CA
AND
Matrix
OR Matrix
Fig. 7

THANK YOU
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PLA

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