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Introduction to VLSI

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This document provides an overview of VLSI design for a course. It discusses topics including CMOS transistors and logic gates, VLSI levels of abstraction, the VLSI design process, design styles like full custom and ASIC, and trends like Moore's Law. The roadmap outlines topics to be covered like CMOS processing, combinational and sequential circuit design, and a design project to complete a chip. Course objectives are listed relating to VLSI analysis, layout design, and system design skills.

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Lecture 1 Introduction to VLSI Design Pradondet Nilagupta [email_address] Department of Computer Engineering Kasetsart University
Acknowledgement This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished. June 9, 2009 204424 Digital Design Automation
Today’s Topics Course overview Objectives Roadmap for the Semester Administrative Details VLSI Overview Transistor Structure Static CMOS Logic Design Methods & Design Styles VLSI Trends June 9, 2009 204424 Digital Design Automation
Course Objectives (1/3) Students should be able to… VLSI Circuit Analysis: Understand MOS transistor operation, design eqns. Understand parasitics & perform simple calculations Understand static & dynamic CMOS logic Estimate delay of CMOS gates, networks, & long wires Estimate power consumption Understand design and operation of latches & flip/flops June 9, 2009 204424 Digital Design Automation
Course Objectives (2/3) CMOS Processing and Layout Understand the VLSI manufacturing process. Have an appreciation of current trends in VLSI manufacturing. Understand layout design rules. Design and analyze layouts for simple digital CMOS circuits Design and analyze hierarchical circuit layouts. Understand ASIC Layout styles. June 9, 2009 204424 Digital Design Automation
Course Objectives (3/3) VLSI System Design Understand register-transfer level design. Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL). Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL. Understand the design flows used in industrial IC design. Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation. June 9, 2009 204424 Digital Design Automation
Roadmap for the term: major topics VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools & Verilog Mixed Signal Concerns: D/A, A/D Conversion Design Project: Complete Chip June 9, 2009 204424 Digital Design Automation
VLSI Overview Why Make IC IC Evolution Common technologies CMOS Transistors & Logic Gates Structure “ Switch-Level” Transistor Model Basic gates The VLSI Design Process Levels of Abstraction Design steps Design styles VLSI Trends June 9, 2009 204424 Digital Design Automation
Why Make ICs Integration improves size speed power Integration reduce manufacturing costs (almost) no manual assembly June 9, 2009 204424 Digital Design Automation
IC Evolution (1/3) SSI – Small Scale Integration (early 1970s) contained 1 – 10 logic gates MSI – Medium Scale Integration logic functions, counters LSI – Large Scale Integration first microprocessors on the chip VLSI – Very Large Scale Integration now offers 64-bit microprocessors, complete with cache memory (L1 and often L2), floating-point arithmetic unit(s), etc. June 9, 2009 204424 Digital Design Automation
IC Evolution (2/3) Bipolar technology TTL (transistor-transistor logic) ECL (emitter-coupled logic) MOS (Metal-oxide-silicon) although invented before bipolar transistor, was initially difficult to manufacture nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market. June 9, 2009 204424 Digital Design Automation
IC Evolution (3/3) aluminum gates for replaced by polysilicon by early 1980 CMOS (Complementary MOS): n-channel and p-channel MOS transistors => lower power consumption, simplified fabrication process Bi-CMOS - hybrid Bipolar, CMOS (for high speed) GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF) June 9, 2009 204424 Digital Design Automation
June 9, 2009 204424 Digital Design Automation Silicon Manufacturing Alternatives Standard Components Application Specific ICs Fixed Application Application by Programming Semi Custom Silicon Compilation Full Custom Logic Families Hardware Programming (MASK) Software Programming TTL CMOS PLA ROM Microprocessor EPROM,EEPROM PLD
VLSI Technology - CMOS Transistors June 9, 2009 204424 Digital Design Automation 2002: L=130nm 2003: L=90nm 2005: L=65nm? Key feature: transistor length L
Transistor Switch Model NFET or n transistor on when gate H "good" switch for logic L "poor" switch for logic H "pull-down" device PFET or p transistor on when gate L "good" switch for logic H "poor" switch for logic L "pull-up" device June 9, 2009 204424 Digital Design Automation
CMOS Logic Design Complementary transistor networks Pullup: p transistors Pulldown - n transistors June 9, 2009 204424 Digital Design Automation
CMOS Inverter Operation June 9, 2009 204424 Digital Design Automation
CMOS Logic Example - What’s This? June 9, 2009 204424 Digital Design Automation P Transistors on when gate “L” N Transistors on when gate “H”
VLSI Levels of Abstraction June 9, 2009 204424 Digital Design Automation Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections
The VLSI Design Process Move from higher to lower levels of abstraction Use CAD tools to automate parts of the process Use hierarchy to manage complexity Different design styles trade off: Design time Non-recurring engineering (NRE) cost Unit cost Performance Power Consumption June 9, 2009 204424 Digital Design Automation
VLSI Design Tradeoffs (1/2) Non-Recurring Engineering (NRE) Costs Design Costs Mask “Tooling” costs Unit Cost - related to chip size Amount of logic Current technology Performance Clock speed Implementation June 9, 2009 204424 Digital Design Automation
VLSI Design Tradeoffs (2/2) Power consumption - a relatively new concern Power supply voltage Clock speed June 9, 2009 204424 Digital Design Automation
VLSI Design Styles Full Custom Application-Specific Integrated Circuit (ASIC) Programmable Logic (PLD, FPGA) System-on-a-Chip June 9, 2009 204424 Digital Design Automation
Full Custom Design Each circuit element carefully “handcrafted” Huge design effort High Design & NRE Costs / Low Unit Cost High Performance Typically used for high-volume applications June 9, 2009 204424 Digital Design Automation
Application-Specific Integrated Circuit (ASIC) Constrained design using pre-designed (and sometimes pre-manufactured) components Also called semi-custom design CAD tools greatly reduce design effort Low Design Cost / High NRE Cost / Med. Unit Cost Medium Performance June 9, 2009 204424 Digital Design Automation
Programmable Logic (PLDs, FPGAs) Pre-manufactured components with programmable interconnect CAD tools greatly reduce design effort Low Design Cost / Low NRE Cost / High Unit Cost Lower Performance June 9, 2009 204424 Digital Design Automation
System-on-a-chip (SOC) Idea: combine several large blocks Predesigned custom cores (e.g., microcontroller) - “intellectual property” (IP) ASIC logic for special-purpose hardware Programmable Logic (PLD, FPGA) Analog Open issues Keeping design cost low Verifying correctness of design June 9, 2009 204424 Digital Design Automation
Perspective on Design Styles Few engineers will design custom chips Some engineers will design ASICs & SOCs Many engineers will design FPGA systems June 9, 2009 204424 Digital Design Automation
VLSI Trends: Moore’s Law In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing: Doubled transistor density every 18-24 months Doubled performance every 18-24 months History has proven Moore right But, is the end is in sight? Physical limitations Economic limitations June 9, 2009 204424 Digital Design Automation I’m smiling because I was right! Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation www.intel.com
Microprocessor Trends (Intel) June 9, 2009 204424 Digital Design Automation Source: http://www.intel.com/pressroom/kits/quickreffam.htm
Microprocessor Trends June 9, 2009 204424 Digital Design Automation Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4 G4
Microprocessor Trends (Log Scale) June 9, 2009 204424 Digital Design Automation Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4N G4 P4
DRAM Memory Trends (Log Scale) June 9, 2009 204424 Digital Design Automation Source: Textbook, Industry Reports
Processor Performance Trends June 9, 2009 204424 Digital Design Automation Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed. , Morgan-Kaufmann, 2002. Vax 11/780
Trends in VLSI Transistor Smaller, faster, use less power Interconnect Less resistive, faster, longer (denser design) Yield Smaller die size, higher yield June 9, 2009 204424 Digital Design Automation
Summary - Technology Trends Processor Logic capacity increases ~ 30% per year Clock frequency increases ~ 20% per year Cost per function decreases ~20% per year Memory DRAM capacity: increases ~ 60% per year (4x every 3 years) Speed: increases ~ 10% per year Cost per bit: decreases ~25% per year June 9, 2009 204424 Digital Design Automation
Technology Directions: SIA Roadmap June 9, 2009 204424 Digital Design Automation
Scaling The process of shrinking the layout in which every dimension is reduced by a factor is called Scaling . Transistors become smaller, less resistive, faster, conducting more electricity and using less power. Designs have smaller die sizes, higher yield and increased performance. June 9, 2009 204424 Digital Design Automation
Can Scaling Continue? Scaling work well in the past: In order to keep scaling work in the future, many technical problems need to be solved. June 9, 2009 204424 Digital Design Automation Year 1989 1992 1995 1997 1999 Technology (  m) 0.65 0.5 0.35 0.25 0.18 2001 0.15
Can Scaling Continue? Some characteristics of the transistors do not scale uniformly, e.g., delay, leakage current, threshold voltage, etc. Mismatch in the scaling of transistors and interconnects. Interconnect delay has increased from 5-10% of the overall delay to 50-70%. June 9, 2009 204424 Digital Design Automation
Roadmap International Technology Roadmap for Semi-conductors (ITRS) Projection of future technology requirements for the next 15 years. June 9, 2009 204424 Digital Design Automation Edition Year of Publication 1st 2nd 3rd 4th 1992 1994 1997 1999 http://public.itrs.net 5th 2001 2002 updates
These trends have brought many changes and new challenges to circuit design. June 9, 2009 204424 Digital Design Automation
Complicated Design Too many transistors and no way to handle them manually. Solutions: CAD Hierarchical design Design re-use June 9, 2009 204424 Digital Design Automation
Power and Noise Huge power consumption and heat dissipation becomes a problem Noise and cross talk. Solutions: Better physical design June 9, 2009 204424 Digital Design Automation
Interconnect Area Too many interconnects Solutions: More interconnect layers (made possible by C hemical- M echanical P olishing) CAD tools for 3-D routing June 9, 2009 204424 Digital Design Automation
Interconnect Delay Interconnect delay becomes a dominating factor in circuit performance Solutions: Use copper wire Interconnect optimization in physical design, e.g., wire sizing, buffer insertion, buffer sizing. June 9, 2009 204424 Digital Design Automation
Interconnect Delay June 9, 2009 204424 Digital Design Automation 0.65 1989 0.5 1992 0.35 1995 0.25 1998 0.18 2001 0.13 2004 0.1 2007 0 5 10 15 20 25 30 35 40 Gate delay Interconnect delay Source: SIA Roadmap 1997
Gallery - Early Processors June 9, 2009 204424 Digital Design Automation Mos Technology 6502 Intel 4004 First µP - 2300 xtors L=10µm
Intel 4004 Introduction date: November 15, 1971 Clock speed: 108 KHz Number of transistors: 2,300 (10 microns) Bus width: 4 bits Addressable memory: 640 bytes Typical use: calculator, first microcomputer chip, arithmetic manipulation June 9, 2009 204424 Digital Design Automation
Gallery - Current Processors June 9, 2009 204424 Digital Design Automation PowerPC 7400 (G4) 6.5M transistors / 450MHz / 8-10W L=0.15µm Pentium® III 28M transistors / 733MHz-1Gz / 13-26W L=0.25µm shrunk to L=0.18µm
Gallery - Current Processors June 9, 2009 204424 Digital Design Automation Pentium® 4 42M transistors / 1.3-1.8GHz / 49-55W L=0.18µm Pentium® 4 “Northwood” 55M transistors / 2-2.5GHz L=0.13µm
Pentium 4 0.18-micron process technology (2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz) Introduction date: August 27, 2001 (2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache (Integrated) System Bus Speed: 400 MHz SSE2 SIMD Extensions Transistors: 42 Million Typical Use: Desktops and entry-level workstations 0.13-micron process technology (2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 512 KB Advanced Transistors: 55 Million June 9, 2009 204424 Digital Design Automation
Intel’s McKinley Introduction date: Mid 2002 Caches: 32KB L1, 256 KB L2, 3MB L3 (on-chip) Clock: 1GHz Transistors: 221 Million Area: 464mm 2 Typical Use: High-end servers Future versions: 5GHz, 0.13-micron technology June 9, 2009 204424 Digital Design Automation
Gallery - Current FPGA June 9, 2009 204424 Digital Design Automation Xilinx Virtex FPGA
Gallery - Graphics Processor June 9, 2009 204424 Digital Design Automation nVidia GeForce4 57M transistors / 300MHz / ??W L=0.15µm
What we’re going to do Chip design: MOSIS “tiny chip” June 9, 2009 204424 Digital Design Automation
What we’re going to do Fabricated MOSIS “Tiny Chip” June 9, 2009 204424 Digital Design Automation
Die Photo - 2001 Design Project June 9, 2009 204424 Digital Design Automation Chip Design by Ed Thomas Photo courtesy Ron Feiller, Agere

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Introduction to VLSI

  • 1. Lecture 1 Introduction to VLSI Design Pradondet Nilagupta [email_address] Department of Computer Engineering Kasetsart University
  • 2. Acknowledgement This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished. June 9, 2009 204424 Digital Design Automation
  • 3. Today’s Topics Course overview Objectives Roadmap for the Semester Administrative Details VLSI Overview Transistor Structure Static CMOS Logic Design Methods & Design Styles VLSI Trends June 9, 2009 204424 Digital Design Automation
  • 4. Course Objectives (1/3) Students should be able to… VLSI Circuit Analysis: Understand MOS transistor operation, design eqns. Understand parasitics & perform simple calculations Understand static & dynamic CMOS logic Estimate delay of CMOS gates, networks, & long wires Estimate power consumption Understand design and operation of latches & flip/flops June 9, 2009 204424 Digital Design Automation
  • 5. Course Objectives (2/3) CMOS Processing and Layout Understand the VLSI manufacturing process. Have an appreciation of current trends in VLSI manufacturing. Understand layout design rules. Design and analyze layouts for simple digital CMOS circuits Design and analyze hierarchical circuit layouts. Understand ASIC Layout styles. June 9, 2009 204424 Digital Design Automation
  • 6. Course Objectives (3/3) VLSI System Design Understand register-transfer level design. Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL). Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL. Understand the design flows used in industrial IC design. Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation. June 9, 2009 204424 Digital Design Automation
  • 7. Roadmap for the term: major topics VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools & Verilog Mixed Signal Concerns: D/A, A/D Conversion Design Project: Complete Chip June 9, 2009 204424 Digital Design Automation
  • 8. VLSI Overview Why Make IC IC Evolution Common technologies CMOS Transistors & Logic Gates Structure “ Switch-Level” Transistor Model Basic gates The VLSI Design Process Levels of Abstraction Design steps Design styles VLSI Trends June 9, 2009 204424 Digital Design Automation
  • 9. Why Make ICs Integration improves size speed power Integration reduce manufacturing costs (almost) no manual assembly June 9, 2009 204424 Digital Design Automation
  • 10. IC Evolution (1/3) SSI – Small Scale Integration (early 1970s) contained 1 – 10 logic gates MSI – Medium Scale Integration logic functions, counters LSI – Large Scale Integration first microprocessors on the chip VLSI – Very Large Scale Integration now offers 64-bit microprocessors, complete with cache memory (L1 and often L2), floating-point arithmetic unit(s), etc. June 9, 2009 204424 Digital Design Automation
  • 11. IC Evolution (2/3) Bipolar technology TTL (transistor-transistor logic) ECL (emitter-coupled logic) MOS (Metal-oxide-silicon) although invented before bipolar transistor, was initially difficult to manufacture nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market. June 9, 2009 204424 Digital Design Automation
  • 12. IC Evolution (3/3) aluminum gates for replaced by polysilicon by early 1980 CMOS (Complementary MOS): n-channel and p-channel MOS transistors => lower power consumption, simplified fabrication process Bi-CMOS - hybrid Bipolar, CMOS (for high speed) GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF) June 9, 2009 204424 Digital Design Automation
  • 13. June 9, 2009 204424 Digital Design Automation Silicon Manufacturing Alternatives Standard Components Application Specific ICs Fixed Application Application by Programming Semi Custom Silicon Compilation Full Custom Logic Families Hardware Programming (MASK) Software Programming TTL CMOS PLA ROM Microprocessor EPROM,EEPROM PLD
  • 14. VLSI Technology - CMOS Transistors June 9, 2009 204424 Digital Design Automation 2002: L=130nm 2003: L=90nm 2005: L=65nm? Key feature: transistor length L
  • 15. Transistor Switch Model NFET or n transistor on when gate H "good" switch for logic L "poor" switch for logic H "pull-down" device PFET or p transistor on when gate L "good" switch for logic H "poor" switch for logic L "pull-up" device June 9, 2009 204424 Digital Design Automation
  • 16. CMOS Logic Design Complementary transistor networks Pullup: p transistors Pulldown - n transistors June 9, 2009 204424 Digital Design Automation
  • 17. CMOS Inverter Operation June 9, 2009 204424 Digital Design Automation
  • 18. CMOS Logic Example - What’s This? June 9, 2009 204424 Digital Design Automation P Transistors on when gate “L” N Transistors on when gate “H”
  • 19. VLSI Levels of Abstraction June 9, 2009 204424 Digital Design Automation Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections
  • 20. The VLSI Design Process Move from higher to lower levels of abstraction Use CAD tools to automate parts of the process Use hierarchy to manage complexity Different design styles trade off: Design time Non-recurring engineering (NRE) cost Unit cost Performance Power Consumption June 9, 2009 204424 Digital Design Automation
  • 21. VLSI Design Tradeoffs (1/2) Non-Recurring Engineering (NRE) Costs Design Costs Mask “Tooling” costs Unit Cost - related to chip size Amount of logic Current technology Performance Clock speed Implementation June 9, 2009 204424 Digital Design Automation
  • 22. VLSI Design Tradeoffs (2/2) Power consumption - a relatively new concern Power supply voltage Clock speed June 9, 2009 204424 Digital Design Automation
  • 23. VLSI Design Styles Full Custom Application-Specific Integrated Circuit (ASIC) Programmable Logic (PLD, FPGA) System-on-a-Chip June 9, 2009 204424 Digital Design Automation
  • 24. Full Custom Design Each circuit element carefully “handcrafted” Huge design effort High Design & NRE Costs / Low Unit Cost High Performance Typically used for high-volume applications June 9, 2009 204424 Digital Design Automation
  • 25. Application-Specific Integrated Circuit (ASIC) Constrained design using pre-designed (and sometimes pre-manufactured) components Also called semi-custom design CAD tools greatly reduce design effort Low Design Cost / High NRE Cost / Med. Unit Cost Medium Performance June 9, 2009 204424 Digital Design Automation
  • 26. Programmable Logic (PLDs, FPGAs) Pre-manufactured components with programmable interconnect CAD tools greatly reduce design effort Low Design Cost / Low NRE Cost / High Unit Cost Lower Performance June 9, 2009 204424 Digital Design Automation
  • 27. System-on-a-chip (SOC) Idea: combine several large blocks Predesigned custom cores (e.g., microcontroller) - “intellectual property” (IP) ASIC logic for special-purpose hardware Programmable Logic (PLD, FPGA) Analog Open issues Keeping design cost low Verifying correctness of design June 9, 2009 204424 Digital Design Automation
  • 28. Perspective on Design Styles Few engineers will design custom chips Some engineers will design ASICs & SOCs Many engineers will design FPGA systems June 9, 2009 204424 Digital Design Automation
  • 29. VLSI Trends: Moore’s Law In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing: Doubled transistor density every 18-24 months Doubled performance every 18-24 months History has proven Moore right But, is the end is in sight? Physical limitations Economic limitations June 9, 2009 204424 Digital Design Automation I’m smiling because I was right! Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation www.intel.com
  • 30. Microprocessor Trends (Intel) June 9, 2009 204424 Digital Design Automation Source: http://www.intel.com/pressroom/kits/quickreffam.htm
  • 31. Microprocessor Trends June 9, 2009 204424 Digital Design Automation Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4 G4
  • 32. Microprocessor Trends (Log Scale) June 9, 2009 204424 Digital Design Automation Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4N G4 P4
  • 33. DRAM Memory Trends (Log Scale) June 9, 2009 204424 Digital Design Automation Source: Textbook, Industry Reports
  • 34. Processor Performance Trends June 9, 2009 204424 Digital Design Automation Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed. , Morgan-Kaufmann, 2002. Vax 11/780
  • 35. Trends in VLSI Transistor Smaller, faster, use less power Interconnect Less resistive, faster, longer (denser design) Yield Smaller die size, higher yield June 9, 2009 204424 Digital Design Automation
  • 36. Summary - Technology Trends Processor Logic capacity increases ~ 30% per year Clock frequency increases ~ 20% per year Cost per function decreases ~20% per year Memory DRAM capacity: increases ~ 60% per year (4x every 3 years) Speed: increases ~ 10% per year Cost per bit: decreases ~25% per year June 9, 2009 204424 Digital Design Automation
  • 37. Technology Directions: SIA Roadmap June 9, 2009 204424 Digital Design Automation
  • 38. Scaling The process of shrinking the layout in which every dimension is reduced by a factor is called Scaling . Transistors become smaller, less resistive, faster, conducting more electricity and using less power. Designs have smaller die sizes, higher yield and increased performance. June 9, 2009 204424 Digital Design Automation
  • 39. Can Scaling Continue? Scaling work well in the past: In order to keep scaling work in the future, many technical problems need to be solved. June 9, 2009 204424 Digital Design Automation Year 1989 1992 1995 1997 1999 Technology (  m) 0.65 0.5 0.35 0.25 0.18 2001 0.15
  • 40. Can Scaling Continue? Some characteristics of the transistors do not scale uniformly, e.g., delay, leakage current, threshold voltage, etc. Mismatch in the scaling of transistors and interconnects. Interconnect delay has increased from 5-10% of the overall delay to 50-70%. June 9, 2009 204424 Digital Design Automation
  • 41. Roadmap International Technology Roadmap for Semi-conductors (ITRS) Projection of future technology requirements for the next 15 years. June 9, 2009 204424 Digital Design Automation Edition Year of Publication 1st 2nd 3rd 4th 1992 1994 1997 1999 http://public.itrs.net 5th 2001 2002 updates
  • 42. These trends have brought many changes and new challenges to circuit design. June 9, 2009 204424 Digital Design Automation
  • 43. Complicated Design Too many transistors and no way to handle them manually. Solutions: CAD Hierarchical design Design re-use June 9, 2009 204424 Digital Design Automation
  • 44. Power and Noise Huge power consumption and heat dissipation becomes a problem Noise and cross talk. Solutions: Better physical design June 9, 2009 204424 Digital Design Automation
  • 45. Interconnect Area Too many interconnects Solutions: More interconnect layers (made possible by C hemical- M echanical P olishing) CAD tools for 3-D routing June 9, 2009 204424 Digital Design Automation
  • 46. Interconnect Delay Interconnect delay becomes a dominating factor in circuit performance Solutions: Use copper wire Interconnect optimization in physical design, e.g., wire sizing, buffer insertion, buffer sizing. June 9, 2009 204424 Digital Design Automation
  • 47. Interconnect Delay June 9, 2009 204424 Digital Design Automation 0.65 1989 0.5 1992 0.35 1995 0.25 1998 0.18 2001 0.13 2004 0.1 2007 0 5 10 15 20 25 30 35 40 Gate delay Interconnect delay Source: SIA Roadmap 1997
  • 48. Gallery - Early Processors June 9, 2009 204424 Digital Design Automation Mos Technology 6502 Intel 4004 First µP - 2300 xtors L=10µm
  • 49. Intel 4004 Introduction date: November 15, 1971 Clock speed: 108 KHz Number of transistors: 2,300 (10 microns) Bus width: 4 bits Addressable memory: 640 bytes Typical use: calculator, first microcomputer chip, arithmetic manipulation June 9, 2009 204424 Digital Design Automation
  • 50. Gallery - Current Processors June 9, 2009 204424 Digital Design Automation PowerPC 7400 (G4) 6.5M transistors / 450MHz / 8-10W L=0.15µm Pentium® III 28M transistors / 733MHz-1Gz / 13-26W L=0.25µm shrunk to L=0.18µm
  • 51. Gallery - Current Processors June 9, 2009 204424 Digital Design Automation Pentium® 4 42M transistors / 1.3-1.8GHz / 49-55W L=0.18µm Pentium® 4 “Northwood” 55M transistors / 2-2.5GHz L=0.13µm
  • 52. Pentium 4 0.18-micron process technology (2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz) Introduction date: August 27, 2001 (2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache (Integrated) System Bus Speed: 400 MHz SSE2 SIMD Extensions Transistors: 42 Million Typical Use: Desktops and entry-level workstations 0.13-micron process technology (2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 512 KB Advanced Transistors: 55 Million June 9, 2009 204424 Digital Design Automation
  • 53. Intel’s McKinley Introduction date: Mid 2002 Caches: 32KB L1, 256 KB L2, 3MB L3 (on-chip) Clock: 1GHz Transistors: 221 Million Area: 464mm 2 Typical Use: High-end servers Future versions: 5GHz, 0.13-micron technology June 9, 2009 204424 Digital Design Automation
  • 54. Gallery - Current FPGA June 9, 2009 204424 Digital Design Automation Xilinx Virtex FPGA
  • 55. Gallery - Graphics Processor June 9, 2009 204424 Digital Design Automation nVidia GeForce4 57M transistors / 300MHz / ??W L=0.15µm
  • 56. What we’re going to do Chip design: MOSIS “tiny chip” June 9, 2009 204424 Digital Design Automation
  • 57. What we’re going to do Fabricated MOSIS “Tiny Chip” June 9, 2009 204424 Digital Design Automation
  • 58. Die Photo - 2001 Design Project June 9, 2009 204424 Digital Design Automation Chip Design by Ed Thomas Photo courtesy Ron Feiller, Agere