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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity fa_str is
Port ( a,b,cin : in STD_LOGIC;
s,cout : out STD_LOGIC);
end fa_str;

architecture fa_struct of fa_str is
component ha
port (a,b:in std_logic;
s,c: out std_logic);
end component;
component or21
port (a,b: in std_logic;
y: out std_logic);
end component;

signal t1,t2,t3 : std_logic;



begin

h1: ha port map (a,b,t2,t1);
h2: ha port map (t2,cin,s,t3);
h3: or21 port map (t1,t3,cout);
end fa_struct;
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Vhdl

  • 1. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa_str is Port ( a,b,cin : in STD_LOGIC; s,cout : out STD_LOGIC); end fa_str; architecture fa_struct of fa_str is component ha port (a,b:in std_logic; s,c: out std_logic); end component; component or21 port (a,b: in std_logic; y: out std_logic); end component; signal t1,t2,t3 : std_logic; begin h1: ha port map (a,b,t2,t1); h2: ha port map (t2,cin,s,t3); h3: or21 port map (t1,t3,cout); end fa_struct;