2022-10-13 09:45:15
The Synopsys DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L SDRAM interfaces operating at up to 3200 Mbps. The Synopsys DDR4/3 PHY is ideal for systems that require high-speed DDR3/4 performance requiring high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 16 ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded calibration processor to execute
hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with Synopsys’ Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.
Synopsys DDR Complete Solution Datasheet
Synopsys DDR4/3 PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
- Supports up to 16 logical ranks for high capacity memory requirements
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/frequencies with <5us switching time
- I/O receiver decision feedback equalization and driver feed-forward equalization
- VT compensated delay lines for DQS centering, read/write leveling, and per bit deskew
- DFI 4.0-compliant controller interface
- Designed for rapid integration with Synopsys memory or protocol controllers for a complete DDR interface solution
Description: |
DDR4 PHY - TSMC N7 |
Name: |
dwc_ddr4_ddr3_phy_tsmc7ff18 |
Version: |
3.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Product Type: |
DesignWare Cores |
Documentation: |
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Application Notes DesignWare Cores DDR4/3 PHY APB Register Map Compression Application Note ( PDF )
DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDR43 PHY coreKit User Guide (coreKit Version: A-2020.06) ( PDF | HTML )
DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Designware Cores DDRn PHY ATE FirmWare Application Note (FW Version: A-2020.06) ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for TSMC7FF18 (PHY Version: 3.00a) ( HTML )
DesignWare Cores DDR4/3 PHY Databook for TSMC7FF18 (PHY Version: 3.10a) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.44a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys DDR4/3 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4 PHY Release Notes for TSMC7FF18 (PHY Version: 3.10a) ( TEXT )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
|
Download: |
dwc_ddr43_phy_tsmc7ff18 |
Product Code: |
C405-0 |
Description: |
DDR4/3 PHY - SS 10LPP |
Name: |
dwc_ddr4_ddr3_phy_ss10lpp |
Version: |
1.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY APB Register Map Compression Application Note ( PDF )
DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A.2017.09) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for SAMS10LPP18 (PHY Version: 1.10a) ( PDF )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.20a) ( PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys DDR4/3 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4/3 PHY Databook for SAMS10LPP18 Release Notes (PHY Version: 1.10a) ( TEXT )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
|
Download: |
DDR4-3-PHY_SS_10LPP |
Product Code: |
C401-0 |
Description: |
DDR4/3 PHY - SS 11LPP |
Name: |
dwc_ddr4_ddr3_phy_ss11lpp |
Version: |
1.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (Version 4.00a) ( PDF )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores ddr43 HY coreKit User Guide (coreKit Version: A-2018.10) ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.41a) ( PDF | HTML )
DesignWare Cores DDR43 PHY Databook for SAMS11LPP18 (PHY Version: 1.10a) ( PDF | HTML )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR43 PHY Release Notes (PHY Version: 1.10a) ( TEXT )
|
Download: |
DDR4-3-PHY_SS_11LPP |
Product Code: |
D841-0 |
Description: |
DDR4/3 PHY - SS 14LPP |
Name: |
dwc_ddr4_ddr3_phy_ss14lpp |
Version: |
2.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY APB Register Map Compression Application Note ( PDF )
DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDR43 PHY coreKit User Guide (coreKit Version: A-2020.06) ( PDF | HTML )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for SAMS14LPP18 (PHY Version:2.10a) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.44a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys DDR4/3 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4/3 multiPHY Release Notes (PHY Version:2.10a) ( TEXT )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
|
Download: |
dwc_ddr43_phy_sams14lpp18 |
Product Code: |
C399-0 |
Description: |
DDR4/3 PHY - SS 8LPP |
Name: |
dwc_ddr4_ddr3_phy_ss8lpp |
Version: |
1.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note 1.30 ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores ddr43 HY coreKit User Guide (coreKit Version: A-2019.04) ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for SAMS8LPP18 (PHY Version:1.10a) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.42a) ( PDF | HTML )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4/3 PHY Databook for SAMS8LPP18 Release Notes (PHY Version: 1.10a) ( TEXT )
|
Download: |
DDR4-3-PHY_SS_8LPP |
Product Code: |
D843-0 |
Description: |
DDR4/3 PHY - TSMC12FFC18 |
Name: |
dwc_ddr4_ddr3_phy_tsmc12ffc18 |
Version: |
2.70a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY APB Register Map Compression Application Note ( PDF )
DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDR43 PHY coreKit User Guide (coreKit Version: A-2020.06) ( PDF | HTML )
DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for TSMC12FFC18 (PHY Version: 2.70a) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.44a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys DDR4/3 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4/3 multiPHY Release Notes (PHY Version: 2.70a) ( TEXT )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
|
Download: |
dwc_ddr43_phy_tsmc12ffc18 |
Product Code: |
C408-0 |
Description: |
DDR4/3 PHY - TSMC16FF+GL |
Name: |
dwc_ddr4_ddr3_phy_tsmc16ffpgl |
Version: |
3.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY APB Register Map Compression Application Note ( PDF )
DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDR43 PHY coreKit User Guide (coreKit Version: A-2019.11) ( PDF )
DesignWare Cores DDRn PHY Diagnostics Firmware Application Note, Version A-2019.11-SP1 ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note, Version A-2019.11-SP1 ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note, Version A-2019.11-SP1 ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for TSMC16FFPGL18 (PHY Version: 3.10a) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.42a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys DDR4/3 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4/3 PHY Databook for TSMC16FFC18 Release Notes (PHY Version: 3.10a) ( TEXT )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
|
Download: |
dwc_ddr43_phy_tsmc16ffpgl18 |
Product Code: |
B126-0 |
Description: |
DDR4/3 PHY - TSMC16FFC |
Name: |
dwc_ddr4_ddr3_phy_tsmc16ffc |
Version: |
3.20a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Unsubscribe |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR4/3 PHY APB Register Map Compression Application Note ( PDF )
DesignWare Cores DDR4/3 PHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Interconnect Signal and Power Integrity Guidelines (version 5.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores DDR43 HY coreKit User Guide (coreKit Version A-2018.04) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores ddr43 HY coreKit User Guide (coreKit Version: A-2019.04) ( PDF )
Designware Cores DDRn PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
Databooks DesignWare Cores DDR4/3 PHY Databook for TSMC16FFC18 (PHY Version: 3.20a) ( PDF | HTML )
DesignWare Cores DDR4/3 PHY Utility Block Databook (PUB Version: 2.42a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys DDR4/3 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR4/3 PHY Implementation Guide (IG Version: 4.10a) ( PDF | HTML )
Release Notes DesignWare Cores DDR4/3 multiPHY Release Notes (PHY Version: 3.20a) ( TEXT )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
|
Download: |
DDR4-3-PHY_TSMC_16FFC |
Product Code: |
B893-0 |