2022-10-28 21:51:47
The Synopsys Basic Universal DDR controllers consist of the Universal DDR Protocol Controller (uPCTL) and the Universal DDR Memory Controller (uMCTL), which support the JEDEC DDR3, DDR2, Mobile DDR, LPDDR2, and LPDDR3 SDRAM standards. For DDR4, LPDDR4 and more advanced features, see the Enhanced Universal DDR Memory Controller (uMCTL2).
The uPCTL serves the memory control needs of applications with simple transactions that do not require an internal scheduler, while the uMCTL accepts memory access requests from up to 16 application-side host ports.
All the Synopsys Universal controllers connect to PHYs via the industry-standard DFI interface, and all their registers may be accessed through industry-standard APB busses.
Read more on the Synopsys blog, "Committed to Memory."
Synopsys Enhanced Universal DDR Memory Controller Datasheet
Synopsys Universal DDR Memory and Protocol Controllers Datasheet
Highlights
Products
Downloads and Documentation
- Select a complete multi-ported enhanced Universal DDR Memory Controller offering up to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Memory Controller or Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, LPDDR/Mobile DDR, LPDDR2, and LPDDR3 SDRAMs
- DFI 2.1 or DFI 3.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
- Data rates up to 2133 Mbps in 1:2 frequency ratio, using an 533 MHz controller clock and 1066 MHz memory clock (Dependent on process and PHY chosen)
- Data rates up to 1600 Mbps in 1:1 frequency ratio, using an 800 MHz controller clock and 800 MHz memory clock (Dependent on process and PHY chosen)
DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 | STARs |
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Description: |
DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2 |
Name: |
dwc_ddr_upctl2 |
Version: |
3.91a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
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Product Type: |
DesignWare Cores |
Documentation: |
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Databooks DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Databook (Version 3.91a) ( PDF | HTML )
DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Databook (Version 3.91a) - with change bars ( PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Installation Guide DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Installation Guide (Version 3.91a) ( PDF | HTML )
Release Notes DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) Release Notes (Version 3.91a) ( PDF | HTML )
Success Stories Starblaze Technology Achieves Volume Production of SSD Controller SoC With Synopsys IP Portfolio ( PDF )
新思科技与忆芯科技 忆芯科技采用新思科技的Synopsys IP系列实现SSD控制器的批量生产 ( PDF )
User Guides DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) User Guide (Version 3.91a) ( PDF | HTML )
DesignWare Cores Enhanced Universal DDR Protocol Controller (uPCTL2) User Guide (Version 3.91a) - with Change bars ( PDF )
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Toolsets: |
Qualified Toolsets |
Download: |
dw_iip_DWC_ddr_umctl2 |
Product Code: |
B624-0 |